# One-bit full modulo adder

FIELD: information technology.

SUBSTANCE: invention can be used in digital computers as well as digital signal processing devices and cryptographic applications. The device has logic elements NOT, AND, OR.

EFFECT: high speed of operation of the adder due to parallel execution of the modulo addition operation.

1 dwg, 1 tbl

The invention relates to computer technology and can be used in digital computing devices, and devices digital signal processing and cryptographic applications.

Known single-bit adder KIM containing 4 two-input logical NAND gate", 2 two-input logic element "OR", 6 two-input logic elements "And", 1 trekhgolovy logical element "And", 1 chetyrehuhogo logical element "OR", 1 trekhgolovy logical element "OR", 1 logical element "NOT"interconnected functionally (see the Handbook for integrated circuits / Bvitamin, Sviatoslavsky, Nasardinov and others; Ed. by Bvitamin. - 2nd ed., Rev. and supplementary): Energy, 1981, s).

The disadvantage of this adder are limited functionality, namely the absence of the accumulation operation for the module.

The closest to the technical nature of the claimed invention is a one-bit full adder module containing 7 logical elements "NOT", 7 two-input logic elements And, 4 chetyrehvhodovyh logical element "And", 4 trehshipovyh logical element "And", 2 trehshipovyh logic element "OR", 1 chetyrehuhogo logical element "OR", 1 Petuhova logical element "OR"connected between the FDS is th functionally (see RF patent №2427027, G06F 7/42, 20.08.2011, bull. No. 23).

The disadvantage of this device is low speed.

The aim of the invention is to increase speed.

To achieve this goal in the one-bit full adder module that contains four two-input logic element "And"three chetyrehvhodovyh logical element "And"six logic elements "NOT" and one logical element "OR", to the inputs of which are connected the outputs of the second, third, and fourth two-input logic elements "And" and the output of which is the output of the transfer of the adder, and to the input of the second two-input logic element And connected to the input of the first and second summation adder to the input of the third two-input logic element And connected to the first input number and input transfer of the adder to the input of the fourth two-input logic element And connected to the input of the second number and the carry-in input of the adder, input the first number of the adder is connected to the input of the sixth logic element "NOT"input the second number of the adder is connected to the input of the fifth logic element "NOT", the carry-in input of adder connected to the input of the fourth logic element "NOT", the input module adder connected to the input of the third logic element "NOT", the output of which is connected to the first vodopennogo and to the first input of the second chetyrehvhodovyh logic elements And, the entrance of the transfer module adder connected to the input of the second logic element and to the first input of the fifth chetyrehhodovogo logic element And the control input of the adder is connected to the input of the first logic element "NOT"introduced five chetyrehvhodovyh, sixteen Petukhova and eight settingdown logical elements "And"one dvadtsatichetyrehrunny and one desativado logical elements "OR", and input the first number of the adder is connected to the fifth input of the third, fourth, seventh, eighth, eleventh, twelfth, fifteenth, sixteenth Petuhova logic elements And, to the sixth input of the third, the fourth, seventh, eighth settingdown logic elements And, to the fourth input of the third, fourth, seventh, eighth chetyrehvhodovyh logical elements "And"input the second number of the adder is connected to the fourth input of the second, third, sixth, seventh, tenth, eleventh, fourteenth, fifteenth Petuhova logic elements And, to the fifth input of the second, third, sixth, seventh settingdown logic elements And, to the third input of the second, third, sixth, seventh chetyrehvhodovyh logical elements "And", the carry-in input of the adder is connected to the third input the first, third, fifth, seventh, ninth, the e is catego, thirteenth, fifteenth Petuhova logic elements And, to the fourth input of the second, fourth, sixth, eighth settingdown logic elements And to the second input of the first, third, fifth, seventh chetyrehvhodovyh logical elements And the input of the adder is connected to the third input of the fifth, sixth, seventh, eighth settingdown logic elements And to the second input of the thirteenth, fourteenth, fifteenth, sixteenth Petuhova logical elements "And"the entrance of the transfer module adder connected to the first input of the fifth, sixth, seventh, eighth and second the input of the ninth, tenth, eleventh, twelfth Petuhova logic elements And to the second input of the fifth, sixth, seventh, eighth settingdown logic elements And to the second input of the first two-input logic element And to the first input of the sixth, seventh, eighth chetyrehvhodovyh logical elements And the control input of the adder connected to the first input of all eight settingdown logical elements "And", the output of the first logic element "NOT" connected to the first input of the first, second, third, fourth, ninth, tenth, eleventh, twelfth Petuhova logical elements "And", the output of the second logic element "NOT" connected to second the d input of the first, the second, third, fourth and to the first input of the thirteenth, fourteenth, fifteenth, sixteenth Petuhova logic elements And to the second input of the first, second, third, fourth settingdown logical elements "And", the output of the third logic element "NOT" connected to the third input of the first, second, third, fourth settingdown logic elements And to the second input of the fifth, sixth, seventh, eighth Petuhova logic elements And to the first input of the third, fourth chetyrehvhodovyh logic elements And to the first input of the first two-input logical element And the output of the fourth logic element "NOT" connected to the third input of the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, sixteenth Petuhova logic elements And, to the fourth input of the first, third, fifth, seventh settingdown logic elements And to the second input of the second, fourth, sixth, eighth chetyrehvhodovyh elements "And", the output of the fifth logic element "NOT" connected to the fourth input of the first, fourth, fifth, eighth, ninth, twelfth, thirteenth, sixteenth Petuhova logic elements And, to the fifth input of the first, fourth, fifth, eighth settingdown logical elements "And who, to the third input of the first, fourth, fifth, eighth chetyrehvhodovyh logical elements "And", the output of the sixth logic element "NOT" connected to the fifth input of the first, second, fifth, sixth, ninth, tenth, thirteenth, fourteenth Petuhova logic elements And, to the sixth input of the first, second, fifth, sixth settingdown logic elements And, to the fourth input of the first, second, fifth, sixth chetyrehvhodovyh logical elements "And"the outputs of the sixteen Petukhova and all eight settingdown logic elements And are connected to the inputs dvadcatichetyrehletnego logic element "OR", the output of which is an information output of the adder, the output of the first input and the outputs of all eight chetyrehvhodovyh logic elements And are connected to the inputs desativado logic element "OR"whose output is the output of the transport module adder, the outputs of the second, third, fourth two-input logic elements And are connected to the inputs Tregubova logic element "OR"whose output is the output of the transfer of the adder.

The goal of improved performance is due to the fact that the reduced number of elements, through which consistently pass the signal when performing arithmetic on which erali summation module. The device prototype (see RF patent №2427027, G06F 7/42, 20.08.2011, bull. No. 23) the number of consecutive elements, through which must pass the signal when performing such operations, is 6, and the proposed device, the number of such elements is 3, i.e. the performance of the device is increased in 2 times.

The invention consists in the implementation of the following ways to add the two numbers 0≤a<m and 0≤b<m modulo m. If (a+b)<m, is the usual sum S=a+b and this sum S is the result. If (S=a+b)>m and the initial condition for the sum S if 0≤a<m and 0≤b<m may not exceed 2m-2, then the sum S is subtracted the value of m and the result is the sum of (a+b) mod m. At the output of the transfer of the adder performing the subtraction, you may receive the signal. This signal is a sign of excess of the sum S of m values and is used to select the result (a+b) or (a+b)-m. In accordance with this one-bit full adder module, which can then be compiled modulo arbitrary number of digits must sum to a_{i}and b_{i}discharges with regard to discharge transfer p_{Ini}of least significant bits, and the resulting sum S_{i}produce the output when no signal transfer module with senior level or subtract from it the discharge module m_{i}if so is the model.

Figure 1 presents the scheme of the one-bit full adder module.

Full bit adder module contains 6 logical elements "NOT" 10, 4 two-input logic elements "And" 14, 8 chetyrehvhodovyh logical elements "And" 13, 16 Petuhova logical elements "And" 11, 8 settingdown logical elements "And" 12, 1 trekhgolovy logical element "OR" 17, 1 desativado logical element "OR" 16, 1 dvadtsatichetyrehrunny logical element "OR" 15 with corresponding connections. Input 1 is the rank of the first number of summation of a_{i}on input 2 - second summation b_{i}. Input 3 is the carry-in input of the p_{Ini}. Input 4 is the discharge module m_{i}. Input 5 is the entrance of the transfer module pm_{Ini}. Entrance 6 is a control input W Output 7 is the output of the transfer p_{Outi}exit 8 - output transfer module pm_{Outi}. Exit 9 is an information output S_{i}.

One-bit adder module works in the following way. Full bit adder module consists of logic elements "is NOT", "AND", "OR"connected thereby to perform the following calculation:

Full bit adder module containing four dvwcwh the annual gate "And", three chetyrehvhodovyh logical element "And"six logical element "NOT" and one logical element "OR", to the inputs of which are connected the outputs of the second, third, and fourth two-input logic elements "And" and the output of which is the output of the transfer of the adder, and to the input of the second two-input logic element And connected to the input of the first and second summation adder to the input of the third two-input logic element And connected to the input of the first number and the carry-in input of the adder to the input of the fourth two-input logic element And connected to the input of the second number and the carry-in input of adder the entrance of the first number of the adder is connected to the input of the sixth logic element "NOT"input the second number of the adder is connected to the input of the fifth logic element "NOT", the carry-in input of adder connected to the input of the fourth logic element "NOT", the input module adder connected to the input of the third logic element "NOT", the output of which is connected to the first input of the first and to the first input of the second chetyrehvhodovyh logical elements "And"the entrance of the transfer module adder connected to the input of the second logic element and to the first input of the fifth chetyrehhodovogo logical element "And"managing the input of the adder is connected to the input of the first logical cell battery (included) is that "NOT", characterized in that it introduced five chetyrehvhodovyh, sixteen Petukhova and eight settingdown logical elements "And"one dvadtsatichetyrehrunny and one desativado logical elements "OR", and input the first number of the adder is connected to the fifth input of the third, fourth, seventh, eighth, eleventh, twelfth, fifteenth, sixteenth Petuhova logic elements And, to the sixth input of the third, fourth, seventh, eighth settingdown logic elements And, to the fourth input of the third, fourth, seventh, eighth chetyrehvhodovyh logical elements "And"input the second number adder connected to the fourth input of the second, third, sixth, seventh, tenth, eleventh, fourteenth, fifteenth Petuhova logic elements And, to the fifth input of the second, third, sixth, seventh settingdown logic elements And, to the third input of the second, third, sixth, seventh chetyrehvhodovyh logical elements "And", the carry-in input of the adder is connected to the third input of the first, third, fifth, seventh, ninth, eleventh, thirteenth, fifteenth Petuhova logic elements And, to the fourth input of the second, fourth, sixth, eighth settingdown logic elements And to the second input of the first, the third is about, fifth, the seventh chetyrehvhodovyh logical elements And the input of the adder is connected to the third input of the fifth, sixth, seventh, eighth settingdown logic elements And to the second input of the thirteenth, fourteenth, fifteenth, sixteenth Petuhova logical elements "And"the entrance of the transfer module adder connected to the first input of the fifth, sixth, seventh, eighth and to the second input of the ninth, tenth, eleventh, twelfth Petuhova logic elements And to the second input of the fifth, sixth, seventh, eighth settingdown logic elements And to the second the first input of two-input logic element And to the first input of the sixth, seventh, eighth chetyrehvhodovyh logical elements And the control input of the adder connected to the first input of all eight settingdown logical elements "And", the output of the first logic element "NOT" connected to the first input of the first, second, third, fourth, ninth, tenth, eleventh, twelfth Petuhova logical elements "And", the output of the second logic element "NOT" connected to the second input of the first, second, third, fourth and to the first input of the thirteenth, fourteenth, fifteenth sixteenth Petuhova logic elements And to the second input of the first, second, Proc. of the third, fourth settingdown logical elements "And", the output of the third logic element "NOT" connected to the third input of the first, second, third, fourth settingdown logic elements And to the second input of the fifth, sixth, seventh, eighth Petuhova logic elements And to the first input of the third, fourth chetyrehvhodovyh logic elements And to the first input of the first two-input logic gate And the output of the fourth logic element "NOT" connected to the third input of the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, sixteenth Petuhova logic elements And, to the fourth input of the first, third, fifth, seventh settingdown logic elements And to the second input of the second, fourth, sixth, eighth chetyrehvhodovyh elements "And", the output of the fifth logic element "NOT" connected to the fourth input of the first, fourth, fifth, eighth, ninth, twelfth, thirteenth, sixteenth Petuhova logic elements And, to the fifth input of the first, fourth, fifth, eighth settingdown logic elements And, to the third input of the first, fourth, fifth, eighth chetyrehvhodovyh logical elements "And", the output of the sixth logic element "NOT" connected to the fifth input of the first, second, fifth, the Estai, the ninth, tenth, thirteenth, fourteenth Petuhova logic elements And, to the sixth input of the first, second, fifth, sixth settingdown logic elements And, to the fourth input of the first, second, fifth, sixth chetyrehvhodovyh logical elements "And"the outputs of the sixteen Petukhova and all eight settingdown logic elements And are connected to the inputs dvadcatichetyrehletnego logic element "OR", the output of which is an information output of the adder, the output of the first input and the outputs of all eight chetyrehvhodovyh logic elements And are connected to the inputs desativado logic element "OR"whose output is the output of the transport module adder, the outputs of the second, third, fourth two-input logic elements And are connected to the inputs Tregubova logic element "OR"whose output is the output of the transfer of the adder.

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