Neuroprocessor

FIELD: information technology.

SUBSTANCE: invention can be used in designing computing means for systems for controlling highly manoeuvrable aviation and space-rocket objects where there is need for fast computation of functions, for example, trigonometric functions, used in matrix transformations when solving tasks of forming an inertial coordinate system based on information from angular velocity sensors, and when solving tasks for maintaining operating capacity of computers during changes in parameters of LSI elements due to the effect of natural or artificial ionising radiations. The device has a unit for communication with an on-board computer or which controls a higher level subsystem, a control device, a buffer register, a memory device, multipliers, an adder and an output register.

EFFECT: fewer faults in microchips.

5 cl, 5 dwg

 

System management of moving objects both for aviation and rocket-space technology as one of the basic parts include a subsystem inertial navigation, which has traditionally been based on gyroscopic platform. However, the limited range of angular positions of the object virtually eliminates its use for highly maneuverable objects. In this regard, in recent times become more and more widespread beskarkasnye inertial system (bins), in which no mechanical gyroscopes, specifying the basic orientation of the inertial coordinate system. In the strapdown inertial navigation system inertial coordinate system is calculated mathematically onboard computing devices according to the information received from sensors of angular velocity, which are used or ring laser sensors, or fiber-optic gyroscopes. Regardless of the type of sensor requires high-speed processing of information about the angular velocity and its translation in the inertial coordinate system. At the heart of these transformations are matrix computations, where the elements of matrices are used trigonometric functions such as sinx and cosx. Despite significant progress in the creation of airborne digital computers (computer) their performance is not what is enough for solving problems Binns, as a software calculating trigonometric functions takes significant time (several milliseconds). This raises the need for the introduction of the computer, or in addition to her specialized calculators-oriented solution Binns, and primarily on fast computation of trigonometric functions. Experts in recent times for the calculation of functions of one or several variables is proposed to use a neural network. This direction seems to be quite promising for the modernization of the computer, with the purpose of acceleration, problem solving beans. It is well known that the trigonometric functions sinx and cosx can be represented by a polynomial, representing the sum of the members of the various degrees of the variable x with the corresponding coefficients. For fast implementation of the calculations in this case, apply the neural network, in which it is necessary to implement a quick summation and multiplication. In neural solvers known proposals (See. article A.N. Gorban "Generalized approximate theorem and computational capabilities of neural networks" / Siberian journal of numerical mathematics, 1998, T1 No.1, p.12-24), where the figures (Fig.1 - Fig.4) examples of building components of neural networks on the basis of adders with a set of weights at the entrance. One is to lack in their composition hardware multipliers and means for setting coefficients for "learning" network what is required when setting up the calculation of a specific function does not allow you to use them to create specialized solvers beans. Some solutions for the components of neural networks is given in another source (See. Linacy "Introduction to artificial intelligence". Educational. manual for schools, 2nd edition. "Academy", where on page 29 describes the neuron Mac-Kalona, Pitts on the basis of several components containing adder works variable and coefficients, elements AND, OR, NOT). However, the lack of multipliers and means for setting coefficients for training is also not possible to use these solutions to accomplish the task: fast computation of trigonometric functions.

For control systems of spacecraft with a long time there is also the problem of neutralization of failures caused by natural aging of the equipment and the flow of heavy charged particles.

In this regard, when using digital computing devices in control systems also require neutralization as catastrophic failures caused by natural aging of the equipment and the flow of heavy charged particles, and parametric variations due to dose effects parameters of integrated circuits, which powers Board will calculate the global device. All this requires new solutions in building computational devices, focused on the use in the control system beans. For solving problems are encouraged to use a solution-oriented tasks beans NEUROPROCESSOR (hereinafter CPU), structure of which is shown in figure 1.

The composition processor includes a communication unit (BS) 1, a bidirectional linked by a line with a computer or processor upper level when placing neuroprocessor in the composition of the Board computer, the firmware control unit (CU) 2, buffer register (BR) 3 for storing argument, a storage device (memory) 4 for storing coefficients of education (settings) CPU n cascaded multipliers, labeled 5-1 to 5-n, the adder 6 and the output register 7 for recording the values of the calculated function whose output is the output of the processor. The first BS is connected to the SU, the second - to BR and memory. The output of the BR is connected to the first inputs of all of the multipliers, to the second inputs of which, starting from the second connected to the output of the transfer of the previous multiplier. Control and clock outputs YY connected respectively to the control and clock inputs of other blocks. When the control outputs of the memory is connected to the input offset of the SU. The outputs of the memory connected to the tuning I the ladies of the multipliers and adder, to the input of which is connected the main outputs of the multipliers. The output of the adder connected to the output register, the output of which is the output of the processor. The device contains a control register of mixing 21, the inputs of which are the inputs of the shift device, and registers the code of operations 22, base address 23 and the counter 24. Installation input registers and counter and the input of the memory 25 are input devices that are connected to the BS, and the address inputs of the drive are the outputs of the registers and the counter address output drive is connected to the input of the register base addresses. The outputs of the drive connected to the buffer elements 26, the outputs of which are the outputs of the device. An additional output buffer element is connected to the counting input of the counter.

In addition, the SU (Cm. 2) contains three channel synchronizer, each of which contains three pulse generator (27-1, 27-2 and 27-3), control inputs which are input devices, and output connected to its shapers (28-1, 28-2 and 28-3). Environment the output of each of the shapers are connected to the same inputs of the other two, and synchronicity shapers are connected to the inputs of a majority of elements 29, the outputs of which are synchronizing outputs of the device and the complementary outputs connected to the gate inputs of the registers and the counter.

Sapom the kăđẫa the device. 3) contains the first 31-1 and the second 31-2 drives, control outputs are connected respectively to the first 32-1 and the second 32-2 to the adders, and the outputs of the drives are connected to the inputs of the comparison circuit 33, the first exit which is the first control output of the memory and a second output connected to the control input of the switch drives 34 whose output is the output of the memory and inputs drives his entrance. The outputs of the first and second adders are respectively the second and third control outputs of the memory, and control inputs input memory.

The pulse generator (See 4) contains n connected in series inverters 41, the outputs of which are connected to the inputs of the multiplexer 42, the output of which is the output of the generator and is connected to the input of the first inverter and the frequency counter 43, the output of which is connected to the first input of the comparison circuit 45 to the second input of which is connected to the output of the code register frequency 46, and increment and decrement outputs of the comparison circuit is connected to the same inputs of the counter code frequency 44, the output of which is connected to the control input of the multiplexer and the input of this counter and the input of the register code frequencies are managing generator input.

The figure 5 shows the structure of the shaper. It contains the element 51, a first input which is the input of the shaper connected to the pulse generator. The output element is connected to the input of the counter 52 and the shift register 53. The outputs of the counter are connected to the inputs of the decoder 54, the output of which is connected to the trigger input trigger stop 55, the output of which is the environment the output of the driver and connected to the second input element And the first input of the majority element 57, the output of which is connected to the input of trigger trigger 56, the output of which is connected to the reset input of the trigger stop, and the second and third inputs of the majority element is connected to the outputs of the triggers binding 58, the gate input which is combined with the first input element And the inputs of the triggers are environment input shaper. Additionally, the outputs of the odd and even bits of the shift register are connected respectively to the trigger and reset inputs of n triggers shapers (59-1 to 59-n) outputs are clock outputs of the driver.

The processor works as follows.

After power on the device control start working setpoint generators and air conditioners, and after a few (3-4) periods of high frequency output are fazirovannye, past majorite, sync. In accordance with the codes stored in the registers 21 to 23 and the counter 24, the initial values of the addresses of the memory 25 are starting to get codes m is creamand, after buffer elements 26 begin to enter the units of a processor, and at the same time from the shaper 28, after majorite 29, the blocks begin to do the sync.

In the storage device 4 recorded weights to specify the weights of the inputs of each layer of neurorehabilitative for different functions. After receiving the communication unit values of its argument and the type of the function is overwritten by firmware signals the beginning come from the drive 25, the value of the argument in the buffer register 3 and the operation code in the register 22 of the control device, as well as other initial values in the other registers and the counter for the formation of the first address fetch microinstructions from the drive 25, further addresses are formed as a combination of codes recorded in the current microinstruction and entering in the register base address register offset 21 in conjunction with an external signal that transitions at the branches of firmware on the conditions, which, in particular, are the control signals memory device 4.

In the first multiplier 5-1 multiplied argument on itself, i.e. you see a value of x2on the second multiplier is multiplying the obtained value by the argument, i.e. there is a third degree argument x3.

Next retrieves the next the degrees of argument in accordance with the required accuracy. The obtained values are received at the inputs of the adder 6, a tuning input of which receives the values of weight coefficients from the storage device 4.

As a result, the output of the adder appears the value of the computed function, which can be read from the output register 7. This construction provides a relatively fast calculation functions, as times are determined only by the delay of combinational elements multiplier and adder, which when implemented in the form of BIS small enough, for example, when used as a multiplier BIS 1825 VR, and the adder BIS 1825 VSF function sinx is calculated for 2 microseconds versus milliseconds when calculating program the on-Board computer that provides the desired speed of solving tasks beans. In addition, the introduction of backup drives memory with control of their health by the comparison circuit 33 and the determination of the location of the failure using hashing arrays of coefficients of the adders 32-1 and 32-2, and then selecting a good device for the firmware in the control device and connected to the output of a good device to neutralize certain catastrophic failures of character in one of the main nodes of neuroprocessor his memory coefficients. And the presence of the s contact of the memory through the communication unit 1 with an external subsystem that allows you to customize ("training") the processor calculating the various functions, what can be done on the factory equipment, and process activities onboard computers, and the presence control to disconnect the drive with distorted ratios excludes "retraining" neuroprocessor. To keep the processor and, moreover, optimal for the current state of the digital elements of the performance in the control unit implements the mode frequency, which entered the control setpoint generators reference codes of the desired frequency in the counter code frequency 45 and register code frequency 4. Maintaining the desired value is selected, for example, on the basis of test checks, automatically changing the value of the counter 45 by signals of the comparison circuit that compares the current frequency value determined by the counter 44, with the value set in the register 47. Thus, the proposed solution can not only significantly, by about an order, to reduce the computation time of functions, but also to change the type of the calculated functions "training" of the processor by writing the desired arrays of coefficients in the storage device 4. But also significantly improve the stability of the processor not only in cases of catastrophic failure caused, for example, distortion of information in storage is equip a hit of heavy charged particles, and also to expand the scope maintain optimal performance (speed) when changing the parameters of elements (transistors) BIS caused dose effects of ionizing radiation, both natural and artificial. All this makes the application of the proposed processor is preferred in comparison with the known solutions.

1. Neuroprocessor containing the adder, characterized in that the composition additionally introduced the communication unit, the input-output which is the input-output processor, a first output connected to the control device, and the second to the input buffer register and a storage device, controlling and synchronizing the outputs of which are connected to other blocks of the processor, and the output buffer register connected to the first inputs of n cascaded multipliers, which, starting from the second, second input connected to the output of the transfer of the previous multiplier, and the outputs of the multipliers are connected to the inputs of the adder, the output of which is connected to the output register, the output which is the output of the processor, and the control input of the storage device connected to the same output control device, and the first and second groups of the set outputs of the storage devices are connected respectively to the same inputs of the multiplier, the adder, and the first, second and third control outputs of the storage devices are connected to the inputs of the shift control device.

2. Neuroprocessor according to claim 1, characterized in that the control unit contains registers offset, code of operations, base and counter installation inputs which are input devices, and outputs connected to the address inputs of the drive, the entrance of which is an input device, an address output connected to the input of the register database, the input offset register offset are the same input device, and outputs the drive connected to the inputs of buffer elements, the outputs of which are control outputs, and an additional output connected to the counting input of the counter, where the device contains three master oscillator, a control input which is the input device, and outputs connected to its shapers, environment the output of each of which is connected to environment inputs of the other two shapers, and clock outputs are connected to a majority of elements, the outputs of which are synchronizing outputs of the device and the complementary outputs connected to the clock inputs of registers, memory and counter.

3. Neuroprocessor according to claim 1, wherein the storage device contains first and second drive inputs to the x are the input device, and their outputs connected to the inputs of the switch drives and inputs of the comparison circuit, a signal output which is the first control output and a control output connected to the control input of the switch, the outputs of which are the outputs of the device, and the additional outputs of the first and second drives connected to the same inputs of the adders, the control inputs are the same the device inputs, and their outputs are respectively the second and third control outputs of the device.

4. Neuroprocessor according to claim 2, wherein the pulse generator comprises n cascaded inverters whose outputs are connected to inputs of a multiplexer whose output is the output of the generator and is connected to the input of the first inverter and the input of the frequency counter, the output of which is connected to the first input of the comparison circuit to the second input of which is connected to the output of the register code frequency, and increment and decrement outputs of the comparison circuit is connected to the same inputs of the counter code frequency, the output of which is connected to the control input of the multiplexer and the input of the counter code frequency and code register frequencies are managing generator input.

5. Neuroprocessor according to claim 2, characterized in that the former contains an element And the first input to which is the input of the shaper, and the output connected to the inputs of the shift register and counter whose outputs are connected to the input of the decoder, the output of which is connected to the trigger input trigger stop, the output of which is the output of the driver and connected to the second input element And the first input of the majority element, the output of which is connected to the input of trigger start, the output of which is connected to the reset input of the trigger stop, and the second and third inputs of the majority element is connected to the outputs of the triggers binding, Gating input which is combined with the first input element And, as the inputs are environment inputs of the driver, and outputs the odd-numbered and even-numbered bits of the shift register is connected to the trigger and dropping the inputs of flip-shapers, the outputs of which are clock outputs of the shaper.



 

Same patents:

Neuroprocessor // 2473126

FIELD: information technology.

SUBSTANCE: invention can be used in designing computing means for systems for controlling highly manoeuvrable aviation and space-rocket objects where there is need for fast computation of functions, for example, trigonometric functions, used in matrix transformations when solving tasks of forming an inertial coordinate system based on information from angular velocity sensors, and when solving tasks for maintaining operating capacity of computers during changes in parameters of LSI elements due to the effect of natural or artificial ionising radiations. The device has a unit for communication with an on-board computer or which controls a higher level subsystem, a control device, a buffer register, a memory device, multipliers, an adder and an output register.

EFFECT: fewer faults in microchips.

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