Thin-film transistor, shift register, circuit of scan signals bus control, display device and method to tune thin-film transistor

FIELD: electricity.

SUBSTANCE: thin-film transistor comprises the first capacitor, comprising an area, in which the first electrode of the capacitor connected with an electrode of source, and the second electrode of the capacitor are arranged one on the other in direction of thickness at opposite sides of the first layer of a dielectric, formed between them, the second capacitor, comprising an area, in which the third and fourth electrodes of the capacitor are arranged one above the other in direction of thickness at the opposite sides of the second layer of the dielectric, formed between them, four output buses, stretching from the appropriate electrode of the capacitor in a plane direction, the first connection crossing the second and fourth output buses, when looking in direction of thickness, and the second connection crossing the first and third output buses, when looking in direction of thickness, besides, the second electrode of the capacitor and the gate electrode are connected to each other via the second output bus, the third electrode of the capacitor and the source electrode are not connected to each other, the fourth electrode of the capacitor and the gate electrode are not connected to each other.

EFFECT: invention makes it possible to create a thin-film transistor, occurrence of a defect in which may be prevented even in case of leakage in a capacitor connected to a transistor body.

37 cl, 13 dwg

 

The technical field

The present invention relates to a thin-film transistor, which includes a capacitor connected between the gate and the source.

The level of technology

In recent years, with the aim of reducing costs was developed monolithic integrated circuit driver of the shutter. Shaper shutter in a monolithic integrated circuit made of amorphous silicon on the liquid crystal display panel. The term "monolithic shaper shutter" is also associated with such terms as "free shaper shutter", "built-in panel shaper shutter and the shutter panel". For example, in the Patent document 1 discloses shift registers, monolithic shapers shutter.

Figure 11 presents a diagram of each stage of the shift register disclosed in Patent document 1. The following describes the basic structure and operation of this scheme. Figure 11 shows the structure of the n-th stage shift register, the stages of which a cascading one after another. Input 12 serves the exit gate of the previous stage. This signal enables the output transistor 16 through the drain of transistor 18. Between the gate and source of the output transistor 16 is enabled accelerating the capacitor 30. When applying the clock signal S1 of a high level on output transistor 16 from its drain potential is its shutter rises sharply to a level exceeding the supply voltage, due to the presence of capacitive coupling between the gate and source of the transistor 16 through a capacitor 30. This essentially reduces the resistance between the source and the drain of the output transistor 16. Further, the signal S1 of a high level is fed to the bus 118 of the shutter, and the output signal of this gate served to the input of the next stage.

On Fig presents a top view of the elements used when embedding accelerating capacitor in the panel display.

Shown in Fig accelerating capacitor 101b made as part of the thin-film transistor 101 and is connected to the housing 101A. If the display panel is made of amorphous silicon or similar material with low mobility, the integral built-in display thin film transistors often form a relief to obtain a substantially higher bandwidth than standard width to reduce the resistance between the inlet and the outlet of the casing 101A thin-film transistor. Thus, figure 11 shows the housing 101A provides greater bandwidth, and GrEbner electrode 102 of the source and the electrode 103 of the flow are opposite to each other in such a way that they interact with each other. Below the interaction region of the electrodes 102 and 103 is an electrode 104 of the shutter. The capacitor 101b SFOR is new so the first electrode 102A of the condenser, passing from the electrode 102 of the housing 101A and the second electrode a condenser, passing from electrode 104 of the housing 101A, are located opposite each other through the dielectric layer.

In addition, the electrode 102A is connected to the OUT-stage shift register, and the output OUT, in turn, is connected to the bus GL shutter via the contact hole 105.

On Fig shows a section along line x-X'marked on Fig.

As shown in Fig, on the glass substrate 100 in the order placed on the foot following layers: GM metal gate layer 106 of the gate dielectric, silicon i-layer 107, a silicon n+ layer, the metal SM source and a passive layer 109. The electrode 104, the electrode a and bus GL is made of a metal layer GM, formed in the parallel production process. The electrodes 102, 103 and 102A made of a metal layer SM source formed in the parallel production process. Layer 107 performs the function of a channel forming region of the casing 101A. Layer 108 performs the function of a contact layer between the source and drain which is located between the layer 107 and the electrode 102, and between the layer 107 and the electrode 103.

The above-described transistor containing accelerating the capacitor is also disclosed in Patent document 2.

Patent documents

Patent document 1

The Japan patent No. 3863215 (date register of the AI: 6 October 2006).

Patent document 2

Patent application Japan, Tokunaga, No. 8-87897 A (publication date: April 2, 1996).

The invention

As described above, the conventional thin-film transistor containing accelerating the capacitor must be large in size to provide a large bandwidth in the housing. Thus, the production of thin-film transistors with a low percentage of output transistors inevitably significantly reduces the percentage of defect-free panels. Despite the increase in load on the output thin film transistor containing accelerating capacitor, the value of the capacitance needed to obtain sufficient accelerating effect increases. Accordingly, accelerating the capacitor occupies a large area on the panel. The magnitude of the value of this capacitance depends on the topology diagram and the technical characteristics of the display panel. For example, the value of capacitance for 7-inch panel is at least 3 pF. With increasing size of the screen increases the value of the capacitance. Thus, depicted on Fig capacitor 101b has an extremely large size. In an example 7-inch WVGA display with a monolithic driver gate that performs a sweep of the three colored lines RGB color model, provided that the value of the capacitance of the capacitor 101b is 3 pF. If the config is then, in which the driver of the shutter is located in one of the two adjacent area of the display areas, the point size of the screen in the direction of the sweep is 63 μm, and the dielectric layer of the gate (SiNx) has a relative dielectric constant of 6.9 and thickness 4100 Å, the capacitor 101b selected so that the length of its sides N, passing in the sweep direction, equal to 50 μm, and the length of the other side of W equal to 400 microns.

Such a large footprint accelerating capacitor, leads to a higher likelihood of leakage between the two opposite electrodes of the accelerating capacitor. If accelerating the condenser has a leak in at least one place, a thin-film transistor is completely out of order. This reduces the yield of thin-film transistors and, thus, significantly reduces the yield of the display panel.

Thus, the disadvantage of conventional thin-film transistor with accelerating capacitor is a low yield of products as a result of leaks in accelerating the condenser.

In light of the above drawbacks in the prior art, the present invention is a thin film transistor, the occurrence of a defect can be prevented even in the event of a leak in the condenser, combined the with the body of the transistor. Adaca of the present invention is a shift register, the control circuit bus signals scan and display devices that contain such a thin-film transistor, and method of adjustment thin-film transistor.

For solving the aforementioned problem is proposed thin-film transistor that includes the first capacitor with the area in which the first electrode of the capacitor connected to the source electrode and the second electrode are located above each other in the thickness direction from opposite sides of the first dielectric layer, formed between them; a second capacitor having a region in which the third and fourth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the second dielectric layer, formed between them; the first output bus, passing from the first electrode of the capacitor in a planar direction; a second output bus, passing from the gate electrode in a planar direction; a third output bus, passing from the third electrode of the capacitor in a planar direction; a fourth output bus, passing from the fourth electrode of the capacitor in a planar direction; a first connection crossing the second and fourth output bus in the direction of thickness; and a second connection, rescause first input bus and a third output bus in the direction of thickness, moreover, the second electrode of the capacitor and the gate electrode are connected to each other through the second output bus, the third electrode of the capacitor and the source electrode are not connected to each other, and the fourth electrode of the capacitor and the gate electrode are not connected to each other.

As a method of adjusting the above-described thin-film transistor, a method, according to which sever the second electrode of the capacitor and the gate electrode by melting the second output bus, weld the first and third output bus to the second connection; and weld the second and fourth output bus to the first connection.

According to the present invention, the first capacitor is attached to the body of the thin-film transistor for providing his work with electricity. In case of any leakage in the first capacitor second electrode of the capacitor is separated from the second output bus by melting with a laser beam or similar method so that the second electrode of the capacitor and the gate electrode are separated from each other. Then, laser welding or equivalent means connecting the second and fourth output bus with the first connection and the first and third output bus is connected with a second connection that allows connection of the second capacitor with corpus the thin-film transistor, and therefore, the second capacitor with electricity.

Thus, the occurrence of leakage in the first capacitor thin-film transistor does not lead to a General failure of the thin-film transistor. Such thin-film transistor suitable for operation in the second capacitor as an additional capacitor.

As described above, the present invention allows to create thin-film transistor, the occurrence of a fault can be prevented even in the event of a leak in the condenser, which is connected with the housing of the thin-film transistor.

For solving the above problem is proposed thin-film transistor that includes the first capacitor, is made in such a way that the first electrode of the capacitor connected to the source electrode and the second electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the first dielectric layer located between them; the second capacitor is designed so that the third electrode of the capacitor and the fourth electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the second dielectric layer located between them; the first output bus, passing from the first electrode in flatness is direction;

a second output bus, passing from the gate electrode in a planar direction;

the third output bus, passing from the third electrode in a planar direction;

the fourth output bus, passing from the fourth electrode in a planar direction; a first connection crossing the second and fourth output bus, when viewed in the thickness direction; and

a second connection crossing the first and third output bus, when viewed in the thickness direction, and the second electrode of the capacitor and the gate electrode are not connected to each other; the first and third output bus is connected to the second connection so that the third electrode of the capacitor and the source electrode Sweeney with each other, the second and fourth output bus connected to the first connection so that the fourth electrode and the gate electrode are connected to each other.

According to the present invention, a second capacitor that is selected from the first and second capacitors, connected to the housing of the thin-film transistor with the possibility of his work with electricity.

Thus, the occurrence of leakage in the first capacitor thin-film transistor does not lead to a General failure of the thin-film transistor. Such thin-film transistor suitable for operation when used in the research Institute of the second capacitor as an additional capacitor.

As described above, the present invention allows to create thin-film transistor, the occurrence of a fault can be prevented even in the event of a leak in the condenser, which is connected with the housing of the thin-film transistor.

To solve the above problem, in the thin-film transistor according to the present invention the first electrode of the capacitor, the third electrode of the capacitor, the first input bus, a third input bus, and a first connection made from a metal source, and the second electrode of the capacitor, the fourth electrode of the capacitor, the second input bus, the fourth input bus and a second connection is made of a metal shutter.

The present invention makes it easy to create first and second capacitors using a material with metallic properties, which is the main material of the thin-film transistor.

To solve the above problems in the thin-film transistor according to the present invention the first and second dielectric layers are layers of dielectric shutter.

The present invention makes it easy to create first and second capacitors with the use of insulating material, which is the main material of the thin-film transistor.

For solving the above problem is proposed that kaplinksy transistor, which contains the output bus connected to the source electrode, and the capacitor containing the area in which the first electrode of the capacitor and the second electrode of the capacitor connected to the gate electrode, are located one above the other in the thickness direction from opposite sides of a dielectric layer formed between them, and the first electrodes of the capacitor are from the output bus in a planar direction.

Further, as a method of adjusting the above-described thin-film transistor, a method, according to which at least one of the first electrode of the capacitor is disconnected from the output bus using melting method.

According to the present invention, the capacitance formed between the electrodes of the first capacitor and the second electrode of the capacitor (hereinafter referred to as partial capacity), which are parallel to each other. These tanks form the total capacitance (hereinafter referred to as the full capacity). If partial capacity rather small compared to the full capacity, then disconnecting from the output bus of the first electrode of the capacitor leakage by melting with a laser beam or a similar method leads to a slight difference in values full capacity before and after disconnecting the first electrode of the capacitor.

Thus, the occurrence of leakage in the Kona is instore thin film transistor does not lead to malfunction of the transistor as a whole. Such thin-film transistor suitable for operation after a fault in the capacitor.

As described above, the present invention allows to create thin-film transistor, the occurrence of a fault can be prevented even in the event of a leak in the condenser, which is connected with the housing of the thin-film transistor.

To do this, in the thin-film transistor according to the present invention, each of the first electrode of the capacitor has a steam room part, forming a pair with those located in the region of the capacitor of the second and third electrodes of the capacitor, which is located closer to the lead bus, and a single part, not forming a pair with the second and third electrodes of the capacitor and passing from the output bus to the pair.

The present invention provides a simple disconnecting the first electrode of the capacitor leakage through melting with a laser beam or similar way in the unpaired part.

To do this, in the thin-film transistor according to the present invention in the first electrode of the capacitor on the border between the unpaired part and part of the steam and/or lead in the bus, in place of razvetvleniya the first electrode of the capacitor and the output bus, made the cut.

In the present invention neckline used as labeling when disconnecting the first is electrode capacitor leakage by melting with a laser beam or similar way in the unpaired part.

To solve the above problem in the thin-film transistor according to the present invention, the first electrode of the capacitor and discharging the tire is made of a metal source and the second electrode of the capacitor is made of a metal shutter.

The present invention allows to create first and second capacitors using a material with metallic properties, which is the main material of the thin-film transistor.

To solve the above problem in the thin-film transistor according to the present invention as a dielectric layer selected dielectric layer of the gate.

The present invention allows to create first and second capacitors with the use of insulating material, which is the main material of the thin-film transistor.

To solve this problem thin-film transistor according to the present invention includes a first capacitor, which has an area in which the first electrode of the capacitor connected to the source electrode and the second electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the first dielectric layer, formed between them, and the area in which the first and third electrodes of the capacitor are located one above the other in the thickness direction from the opposite side is N. the second dielectric layer, formed between them, so that the connection between the first and third electrodes of the capacitor and the connection between the first and second electrodes of the capacitor are made on mutually opposite surfaces of the first electrode of the capacitor; a second capacitor, which has an area in which the fourth and fifth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the third dielectric layer formed between them; and the area in which the fourth and sixth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the fourth dielectric layer, formed between them, so that the connection between the fourth and sixth electrodes of the capacitor and the connection between the fourth and fifth electrodes of the capacitor are made on mutually opposite surfaces of the fourth electrode of the capacitor; a first output bus, passing from the first electrode of the capacitor in a planar direction; a second output bus, passing from the second electrode of the capacitor in a planar direction; the output bus of the shutter extends from the gate electrode in a planar direction; a third output bus, passing from the third electrode of the capacitor in a planar direction; a fourth output bus, about Adamou from the fourth electrode of the capacitor in a planar direction; the fifth pin bus that goes from the fifth electrode of the capacitor in a planar direction; a first connection, cross pin bus speed and the fifth pin of the bus, when viewed in the thickness direction; vtoroe connection crossing the first and the fourth output bus, when viewed in the thickness direction, and the third electrode of the capacitor and the gate electrode are connected to each other through a third output bus, the sixth electrode of the capacitor is connected to the fifth pin of the bus, the second electrode of the capacitor and the gate electrode are connected to each other through the second input bus input bus speed and the fifth pin bus is not connected with the first connection, lead bus speed and the fourth lead bus is not connected with the second connection.

As the method of adjustment thin-film transistor according to the present invention, a method, according to which the third electrode of the capacitor and the gate electrode are to be separated by melting the third output bus; weld the sixth electrode of the capacitor to the fifth pin of the bus; the second electrode of the capacitor and the gate electrode are to be separated by melting the second output bus output bus speed and the fifth output bus are welded to the first connection; and the first and fourth output bus are welded to the second connection.

According to the present invention, the first capacitor is connected to the body of the thin-film transistor for providing work using electricity. In case of any leakage in the first capacitor second electrode of the capacitor are separated from the gate electrode by melting the laser beam of the second output bus or in a similar way, and the third electrode of the capacitor are separated from the gate electrode by melting the laser beam of the third output bus or in a similar way. Then, laser welding or equivalent means connecting the output bus speed and the fifth pin bus with the first compound and the first and fourth output bus with the second connection, allowing the connection of the second capacitor to the chassis of the thin-film transistor and, therefore, the second capacitor with electricity.

Thus, the occurrence of leakage in the first capacitor thin-film transistor does not lead to malfunction of the thin-film transistor as a whole. Such thin-film transistor suitable for operation in the second capacitor as an additional capacitor.

As described above, the present invention allows to create thin-film transistor, the occurrence of a fault can be prevented even in the event of a leak in the condenser, which is connected with the housing of the thin-film transistor.

To solve this problem thin-film transistor according to the present is obreteniyu contains the first capacitor, which is the area in which the first electrode of the capacitor connected to the source electrode and the second electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the first dielectric layer, formed between them, and the area in which the first and third electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the second dielectric layer, formed between them, so that the connection between the first and third electrodes of the capacitor and the connection between the first and second electrodes of the capacitor are made on mutually opposite surfaces of the first electrode of the capacitor; a second capacitor that has a scope, in which the fourth and fifth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the third dielectric layer formed between them; and a second area in which the fourth and sixth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the fourth dielectric layer, formed between them, so that the connection between the fourth and sixth electrodes of the capacitor and the connection between the fourth and fifth electrodes of the capacitor are made on mutually opposite surfaces of the fourth the second electrode of the capacitor; the first output bus, passing from the first electrode in a planar direction; a second output bus, passing from the second electrode in a planar direction; the output bus of the shutter extends from the gate electrode in a planar direction;

the third output bus, passing from the third electrode in a planar direction;

the fourth output bus, passing from the fourth electrode of the capacitor in a planar direction; a fifth pin bus that goes from the fifth electrode in a planar direction; a first connection, cross pin bus speed and the fifth pin of the bus, when viewed in the thickness direction; and a second connection crossing the first and the fourth output bus, when viewed in the thickness direction, and the third electrode of the capacitor and the gate electrode are not connected to each other, the sixth electrode of the capacitor is connected to the fifth pin of the bus, the second electrode and the gate electrode are not connected to each other, pin the bus speed and the fifth output bus connected with the first connection so that the fifth and sixth electrodes of the capacitor connected to the gate electrode, the first and the fourth output bus is connected to the second connection so that the fourth electrode of the capacitor and the source electrode are connected.

According to this izobreteny the second capacitor, selected from the first and second capacitors, connected to the housing of the thin-film transistor with the possibility of a second capacitor with electricity.

Thus, the occurrence of leakage in the first capacitor thin-film transistor does not imply failure of the transistor as a whole. Such thin-film transistor suitable for operation in the second capacitor as an additional capacitor.

As described above, the present invention allows to create thin-film transistor, the occurrence of a fault can be prevented even in the event of a leak in the condenser, which is connected with the housing of the thin-film transistor.

To solve the above problem, in the thin-film transistor according to the present invention the first and fourth electrodes of the capacitor, the first and the fourth output bus, and a first connection is made from a material source, the second and fifth electrodes of the capacitor, the second and fifth output bus, and a second connection is made from a metal shutter, and the third and sixth electrodes of the capacitor and the third lead, the tire is made of transparent electrodes.

The present invention allows to create first and second capacitors using a material with metallic properties, the which is the main material of the thin-film transistor.

To solve the above problems in the thin-film transistor according to the present invention the first and third dielectric layers are a layer of gate dielectric, and the second and fourth dielectric layers are a passivating layer.

The present invention allows to create first and second capacitors with the use of insulating material, which is the main material of the thin-film transistor.

To solve these tasks, thin-film transistor according to the present invention includes: the output bus connected to the source electrode; and a capacitor, which has an area in which the first electrodes of the condenser, passing from the output bus in a planar direction, and a second electrode connected to the gate electrode, are located one above the other in the thickness direction from opposite sides of the first dielectric layer, formed between them, and the area in which the first electrode of the capacitor and the third electrode of the capacitor connected to the gate electrode, are located one above the other in the thickness direction from opposite sides of the second dielectric layer, formed between them, so that the connection between the first and third electrodes of the capacitor and the connection between the first and second electrodes conden atora performed on mutually opposite surfaces of the first electrode of the capacitor.

Further, as a method of adjusting the above-mentioned thin film transistor, a method, according to which at least one of the first electrode of the capacitor is disconnected from the output bus by melting.

According to the present invention, the capacitance formed between the first electrode of the capacitor and the second electrode of the capacitor (hereinafter referred to as the first partial capacitance) connected in parallel with each other, and the capacitance formed between the first electrode of the capacitor and the third electrode of the capacitor (hereinafter referred to as the second partial capacitance) connected in parallel with each other. These tanks form the total capacitance (hereinafter referred to as the full capacity). If the sum of the first and second partial vessels is small enough compared to the full capacity, then disconnecting the first electrode of the capacitor with leakage from the output bus by melting with a laser beam or a similar method leads to a slight difference in values full capacity before and after disconnecting the first electrode of the capacitor.

Thus, the occurrence of leakage in the capacitor thin-film transistor does not lead to malfunction of the thin-film transistor as a whole. Such thin-film transistor suitable for operation after a fault in the capacitor is.

As described above, the present invention allows to create thin-film transistor, the occurrence of a fault can be prevented even in the event of a leak in the condenser, which is connected with the housing of the thin-film transistor.

To solve the above problems in the thin-film transistor according to the present invention, each first electrode of the capacitor includes: a section; forming a pair with the second or the third electrodes of the capacitor near pin bus electrodes which are located in the area of the capacitor; and the plot, which does not form a pair with the second and third electrodes, which passes from the output bus to the site, forming a pair.

The present invention provides a simple disconnecting the first electrode of the capacitor leakage through melting by the laser beam or in a similar way to the unpaired part.

To solve the above problems in the thin-film transistor according to the present invention in the first electrode of the capacitor on the border between the unpaired part and part of the steam and/or lead in the bus, in place of razvetvleniya the first electrode of the capacitor and the output bus, made the cut.

In the present invention neckline used as labeling when disconnecting the first electrode of the capacitor with leakage through the melting usernamecol or equivalent means for unpaired part.

To solve the above problems in the thin-film transistor according to the present invention the first electrode of the capacitor and discharging the tire is made from a metal source, the second electrode of the capacitor made of a metal shutter, and the third electrode of the capacitor is made of a transparent electrode.

The present invention allows to create first and second capacitors using a material with metallic properties, which is the main material of the thin-film transistor.

To solve the above problems in the thin-film transistor according to the present invention as the first dielectric layer used in the dielectric layer of the gate, and as the second layer used passivating layer.

The present invention allows to create first and second capacitors with the use of insulating material, which is the main material of the thin-film transistor.

To solve these tasks, thin-film transistor according to the present invention fabricated using amorphous silicon.

The present invention avoids significant reduction in yield of thin-film transistors by increasing the output capacitor, due to the fact that thin-film transistors made of and what Ortega silicon, have a large bandwidth, which may result in lower yield products.

To solve these tasks, thin-film transistor according to the present invention manufactured using the microcrystalline silicon.

Thin-film transistor of the microcrystalline silicon has a higher mobility than a transistor made of amorphous silicon. Therefore, the present invention enables the manufacture of a transistor whose dimensions are small compared to a transistor made of amorphous silicon. In addition, the use of microcrystalline silicon allows to obtain thin-film transistor, which occupies a small area, which is useful when it is used in thin frames of the image. It also allows you to limit the fluctuations of threshold voltage caused by DC offsets.

To solve above problems, the shift register according to the present invention includes the steps consisting of transistors, at least one of which represents the above-mentioned thin-film transistor.

The present invention provides a production shift registers with a high yield of products.

To solve these tasks, the control circuit bus scan signals according to the present invention contains the above-mentioned shift register, used to generate a sweep signal to the display device.

The present invention provides the production of schemes of management bus signals scan with a high yield of products.

To solve the above-mentioned task, the control circuit bus scan signals according to the present invention is made with the possibility of using thin-film transistor as an output transistor that outputs a signal sweep.

The present invention enables the manufacture of thin-film transistor, which can be used as an output transistor that outputs a signal sweep, high management capability.

To solve these tasks, display device according to the present invention contains the above-mentioned control circuit bus signals of the scan.

The present invention allows manufacturing a display device with a high yield of products.

To solve the above problems in the display device according to the present invention, the control circuit bus signals of the scan performed on the display panel and integrally United with the display area.

The present invention allows to compensate for the disadvantages caused by the fact that the display device requires use of the project for a large emkosti, and thin-film transistor must necessarily have a wide channel. Consequently, it is possible to manufacture a display device with high yield products in which the circuit control bus signals of the scan performed on the display panel and integrally United with the display area.

To solve these tasks, display device according to the present invention includes a display panel containing the above-mentioned thin-film transistor.

The present invention allows to create a display device, the malfunction can be prevented even when there is leakage in the capacitor connected to the body of the thin-film transistor.

In the description below, with reference to the accompanying drawings provides further clarification of the objectives, characteristics and advantages of the present invention.

Brief description of drawings

Figure 1 shows a top view of one embodiment implementing the present invention, and the structure of the thin-film transistor according to the first example.

Figure 2 shows a section along line a-a'indicated in figure 1.

Figure 3 shows a top view of one embodiment implementing the present invention, and the structure of the thin-film transistor according to the second example.

Figure 4 shows a top view of one the C variants of realization of the present invention, as well as the structure of the thin-film transistor according to the third example.

Figure 5 shows a cross section of the thin-film transistor shown in figure 4, and (a) is a cross-section on the line-In', a (b) - section on the line C-SU.

Figure 6 shows a top view of one embodiment implementing the present invention, and the structure of the thin-film transistor according to the fourth example.

Figure 7 shows the schematic diagram of one embodiment implementing the present invention, showing the construction of the display device.

On Fig principle diagram of the shift register contained in the display device shown in Fig.7.

Figure 9 shows an explanatory diagram of the stages of the shift register shown on Fig, and (a) schematic diagram of the stages of the shift register, and (b) is a timing chart of the operation of the circuit shown in Fig.9(a).

Figure 10 shows a timing chart of the operation of shift register depicted in Fig.

Figure 11 shows a diagram of a known stage shift register.

On Fig shows a top view of a known thin-film transistor.

On Fig shows a section along line x-X'marked on Fig.

Indicate on drawings

1 - liquid crystal display device

61, 71, 81 and 91 - thin-film transistors

61b - capacitor (first capacitor)

61C - capacitor (second capacitor)

62 - electrode source

64 - electrode shutter

A first electrode of the capacitor

64A second electrode of the capacitor

62b - the third electrode of the capacitor

64b - the fourth electrode of the capacitor

62i - lead bus (first pin bus)

64h - lead bus (second lead bus)

62j - lead bus (the third pin bus)

64i - lead bus (the fourth pin bus)

66 - the layer of gate dielectric, the first dielectric layer, second dielectric layer and the dielectric layer)

71A - capacitor

72h - lead bus

72A is a first electrode of the capacitor

A the second electrode of the capacitor

73, 74, and 75 - cuts

81b - capacitor (first capacitor)

81s with capacitor (second capacitor)

82 - electrode source

84 - electrode shutter

A first electrode of the capacitor

A the second electrode of the capacitor

80A - the third electrode of the capacitor

82b - the fourth electrode of the capacitor

84b - fifth electrode of the capacitor

80b - sixth electrode of the capacitor

82i - lead bus (first pin bus)

84h - lead bus (second lead bus)

80C - lead bus (the third pin bus)

84d - lead bus (pin bus gate)

82j - lead bus (the fourth pin bus)

E - pin tire is (fifth pin bus)

86 - the layer of gate dielectric, the first dielectric layer, the third dielectric)

89 - passivating layer (second dielectric layer, the fourth dielectric layer)

A capacitor

92h - lead bus

92A first electrode of the capacitor

A the second electrode of the capacitor

90A - the third electrode of the capacitor

93, 94, 95 - cut

Tr4 - transistor (thin film transistor)

CAP - capacitor (first capacitor and the second capacitor)

The implementation of the invention

Below with reference to Fig 1-10 describes one of the options for implementing the present invention.

Figure 7 illustrates the design of the liquid crystal display device 1 according to the present invention.

The device 1 includes a display panel 1, a flexible printed circuit Board 3 and Board 4 management.

As panel 2 used in an active matrix display panel in which the glass substrate deposited amorphous silicon, polycrystalline silicon, silicon with a continuous crystal structure, microcrystalline silicon or silicon with similar properties, the region 2A of the display, tires GL shutter bus SL source and shapers 5A and 5b of the shutter. In area 2A, the pixels PIX are arranged in a matrix. Each pixel PIX includes a thin-film transistor 21, i.e., the element of choice pixel PIX, idcatart lichecki capacitor CL and an auxiliary capacitor Cs. The gate of the transistor 21 is connected to the bus GL, and the source of transistor 21 is connected to the bus SL. Capacitors CL, Cs is connected to the drain of transistor 21.

The tyres GL include bus GL1, GL2, GL3, ..., GLn. Tyres GL of the first group, consisting of alternating tires GL1, GL3, GL5, etc., connected to respective outputs of the shaper 5A and tires GL of the second group, consisting of the remaining alternating tires GL2, GL4, GL6, etc. gate connected to respective outputs of the shaper 5b. The SL tires are tires SL1, SL2, SL3, ..., SLm, which are connected to respective outputs of the driver 6, which will be described below. The circuit of the auxiliary capacitor (not shown) is used to supply the voltage of the auxiliary capacitor in each capacitor Cs of the pixel PIX.

Driver 5A is located along the tire GL in one of the two regions adjacent to the region 2A of the panel 2, and sequentially supplies a gate pulse to each bus gate GL1, GL3, GL5, etc. of the first group. Shaper 5b is located in another area adjacent to the area 2A of the panel 2, and sequentially supplies a gate pulse to each bus shutter GL2, GL4, GL6, etc. of the second group. These shapers 5A and 5b are built into the panel 2 and monolithic integrated area 2A. Examples shapers 5A and 5b can serve all the shapers of gates, which are denoted by the terms "monolithic shaper shutter", "svobodnosformulirovannoy shutter", "built-in panel shaper shutter and the shutter panel".

Card 3 contains the driver 6. Driver 6 supplies the data signal on each bus SL. Board 4 is connected to the plate 3 and supplies the necessary signals and power to the generators 5A, 5b and 6. Signals and power are served from the Board 4 through the card 3 driver 15 panel 2.

On Fig shows the structure of the respective shapers 5A and 5b.

The imaging unit 5A includes a first shift register 51A with cascaded stages SR (SRI, SR3, SR5, and so on). Each stage SR contains the input Qn-1 signal setup, output GOUT, log Qn+1 is zero, the clock inputs of the SKA and the VCS and the input VSS source of low power. Fee 4 generates the clock signal W1, the clock signal W2, triggering the strobe pulse GSP1 and the VSS power source low power (for convenience, used the same symbol VSS and VSS input source low power). Source VSS may have a negative potential, a zero potential or a positive potential. However, in the present description source VSS is a negative potential to provide off-state thin-film transistor.

In the first shift register 51A output signal from the output GOUT (j-th stage SRi shift register (j=1, 2, 3..., i=l, 3, 5..., j=(i+l)/2) represents the output strobe pulse Gi filed the i-th bus GLi shutter.

Triggering the strobe pulse GSP1 served on the input Qn-1 first stage SRI, which is located in one of the opposite ends in the direction of the sweep. To corresponding inputs of Qn-1 of the second and subsequent stages of SRi served the output signal Gi-2 of the previous stages SRi-2. Next, to corresponding inputs of Qn+1 serves the output signal Gi+2 the following steps SRi+2.

In alternate j-th stages SR, starting with the first stage SR1, the clock signal W1 served on the clock inputs of the SKA, and the clock signal W2 is served on the clock inputs of SLE. In alternate j-th stages SR, starting from the second stage SR2, the clock signal W2 is served on the clock inputs of the SKA, and the clock signal W1 served on the clock inputs of SLE. Thus, the first and second steps are alternately in the first shift register 51A.

The shape of the signals W1 and W2 shown in Fig.9 (b) (see SKA and SLE for W1 and W2, respectively). The signals W1 and W2 are served so that their clock pulses do not overlap each other. In addition, the time signals W1 and W2 are selected so that the clock pulse signal W1 serves delayed by one clock pulse after the filing of the clock pulse signal W2, and the clock pulse signal W2 serves delayed by one synchronise the store pulse after the filing of the clock pulse signal W1.

The imaging unit 5b includes a second shift register 51b, which has cascaded stages SR (SR2, SR4, SR6, and so on). Each sting SR contains the input Qn-1 signal setup, output GOUT, log Qn+1 is zero, the clock inputs of the SKA and the VCS and the input VSS source of low power. Fee 4 generates the clock signal TC3, the clock signal SK4, triggering the strobe pulse GSP2, and the power source VSS of the low power.

In the register 51b output signal from the output GOUT of the k-th stage SRi (k=l, 2, 3..., i=l, 4, 6..., k=i/2) represents the output strobe pulse Gi supplied to the i-th bus GLi.

Triggering the strobe pulse GSP2 served on the input Qn-1 of the first stage SR1,_ which is located on one of opposite ends in the direction of the sweep. To corresponding inputs of Qn-1 second and the following stages of SRi served the output gate pulse Gi-2 previous stages of shift register SRi-2. Next, to corresponding inputs of Qn+1 serves the output gate pulse Gi+2 the following stages of shift register SRi+2.

In alternating k-x stages SR, starting from the first step SR2, the clock signal TC3 served on the clock inputs of the SKA, and the clock signal SK4 served on the clock inputs of SLE. In alternating k-x stages SR, since the second step SR4, the clock signal SK4 served on the clock inputs SKA, and clock C is cash TC3 served on the clock inputs of SLE. Thus, the third and fourth stages are arranged alternately in the second shift register 51b.

The form of the synchronizing signal TC3 and SK4 shown in Fig.9(b) (see SKA and SLE for TC3 and SK4, respectively). Clock signals TC3 and SK4 are served so that their clock pulses do not overlap each other. In addition, the time signal TC3 and SK4 selected so that the clock pulse signal TC3 serves delayed by one clock pulse after the clock pulse signal SK4, and the clock pulse signal SK4 serves delayed by one clock pulse after the clock pulse signal.

Next, as shown in Figure 10, the signals W1, W2, TC3, and SK4 are not synchronized with each other. Time signals W1, W2, TC3 and SK4 selected so that the clock pulse signal W1 is served after the clock pulse signal SK4, the clock pulse signal TC3 served after the clock pulse signal W1, the clock pulse signal W2 is served after the clock pulse signal TC3, and the clock pulse signal SK4 served after the clock pulse signal W2.

As shown in Figure 10, triggering the strobe pulses GSP1 and GSP2 filed one after another, and the strobe pulse GSP1 precedes the article is about-the pulse GSP2. The strobe pulse GSP1 synchronized with a synchronizing pulse signal W2, and the strobe pulse GSP2 synchronized with a synchronizing pulse signal SK4.

Below with reference to Fig.9 (a) shows the structure of the degrees SRi shift registers 51A and 51b.

Stage SRi shift register contains transistors Tg, Tg, Tg, and Tg. In particular, the transistor Tr4 includes a capacitor CAP, which is accelerating the capacitor. All these transistors are thin film transistors n-channel type.

The gate and drain of the transistor Tg connected to the input Qn-1, and a source connected to the gate of the transistor Tg. The drain of transistor Tg connected to the clock input of SKA, and a source connected to the output of GOUT. Thus, the transistor Tg serves as a transmission gate, which provides the passage and interruption of the clock signal applied to the input of SKA. Between the gate and source of the transistor Tg installed capacitor CAP. The node netA has the same potential as the gate of the transistor Th.

The gate of the transistor Tg connected to the clock input of SLE, a drain connected to the output of GOUT, and a source connected to the input source VSS of low power. The gate of the transistor Tg connected to the input Qn+1, a drain connected to the node netA and the source of Saedinenie input source VSS.

Below with reference to Fig.9 (b) shows the description of the stupa and SRi, depicted in Fig.9 (a).

When applying the momentum shift to the input Qn-1, the transistor Tr1 turns on and charges the capacitor CAP. In respect of the stages SR1 and SR2, the momentum shift corresponds to triggering the strobe pulses GSP1 and GSP2, respectively. In relation to other stages of the SRi momentum shift corresponds to the output strobe pulses Gj-1 and Gk-1 from the previous steps of the shift register. Charging of the capacitor CAP increases the potential of the node netA and causes the transistor Tg. This causes the source of the transistor Th clock signal applied through input SKA. At the time of submission of the next clock pulse on input SKA potential of the node netA is increasing rapidly due to the influence of accelerating capacitor CAP, and the input clock pulse is output GOUT stage SRi, and is output from the output GOUT in the form of strobe.

After submitting the strobe input Qn-1 transistor Tg returns to the off state. Further, for preventing the accumulation of charge caused by the floating node netA and the output GOUT stage SRi, the reset pulse fed to the input Qn+1, causes the transistor Tg. Due to this, the potential of the node netA and the output GOUT is set equal to the potential source VSS.

Then before re-submitting the momentum shift to the input Qn-1 transistor Tg periodically starts the clock pulse, the hearth is aimim to the sync input of the SCR. This leads to the restoration potential of the node netA and the output GOUT steps to SRi potential source of low power, i.e. voltage drop on the bus GLi.

Thus, the gate pulses are sequentially deposited on the tires G1, G2, G3, etc. as shown in Figure 10.

The following examples describes the structure of the elements used in the transistor Tg depicted in Fig.9(a).

Example 1

Below with reference to figures 1 and 2 describes the thin-film transistor according to this example implementation.

Figure 1 shows a top view of the structure of the proposed thin-film transistor 61, made with the possibility of use as a transistor Tg and installed on the panel 2.

The transistor 61 includes a housing 61A, the capacitor 61b and 61C and connections s and s. Each of the capacitor 61b and 61 may perform the function of accelerating capacitor and used as a capacitor CAP.

Case 61A has greneway electrode 62 source and greneway electrode 63 runoff, located opposite each other in the plane of the top electrode 64 of the shutter in the direction of thickness so that the electrodes 62, 63 communicate with each other, which provides greater bandwidth. However, this is only one example of possible configurations. The electrodes 62, 63 and 64 can be placed in any positions and amerilube form.

The capacitor (first capacitor) 61b has an area in which the first electrode a and the second electrode 64A are located one above the other in the thickness direction from opposite sides of the layer 66 of dielectric shutter (first dielectric layer, see Figure 2)located between them. The first electrode a condenser passes from electrode 62 of the housing 61A through the output bus 62h in a planar direction. The second electrode 64A passes from electrode 64 of the housing 61A through the output bus 64h (second lead bus) in a planar direction.

The first electrode a connected to the OUT-stage shift register SR through the output bus 62i (first pin bus) in a planar direction. The output OUT is connected via the contact hole 65 bus GL shutter below in the thickness direction.

The capacitor 61 (second capacitor) is located near the capacitor 61b and has a region in which the third electrode 62b and the fourth electrode 64b are located one above the other in the thickness direction from opposite sides of the layer 66 of dielectric shutter (second dielectric layer)located between them. The first and second dielectric layers may differ from each other. In this case, the capacitor 61b and 61C have the same value of capacitance. Lead bus 62j (third pin bus) runs from the third electrode 62b in a planar direction. Vivodin the I bus 62i (fourth pin bus) runs from the fourth electrode 64b in a planar direction.

Connection s (first connection) crosses the output bus 64h and 64i in the top positions in the thickness direction. Connection s (second connection) crosses the output bus 62i and 62j lower positions in the thickness direction.

Figure 2 presents a cross-section along the line a-a'indicated in figure 1.

As can be seen from Figure 2, according to the configuration depicted in figure 1, on the glass substrate 60 in order are the GM metal gate layer 66 formed of silicon i-layer 67 formed of silicon n+ layer 68, the metal SM source and a passive layer 69. The electrodes 64 and 64A, lead bus 64h, connection s and bus GL is formed of metal GM made in the parallel production process. For example, metal GM can be used in the form of a separate layer (or TaN), Ti (or TiN), Al (or alloy, the main component of which Al), Mo (or Mos), SG or in the form of the foot with any combinations of these metals. The electrodes 62, 63 and a, lead bus 62i and the connection is formed from metal SM made in the parallel production process. Metal SM can be formed from the same material or materials as the metal GM. For example, the metal SM can be used as a separate layer (or TaN), Ti (or TiN), Al (or alloy, the main component of which Al), Mo (or Mos), SG or in the form of the foot with any combinations of these meta is fishing. Layer 67 performs the function of a channel forming region in the housing 61A. Layer 68 is a contact layer between the source and drain which is located between the layer 67 and the electrode 62, and between the layer 67 and the electrode 63.

In addition, as shown in figure 1, the fourth electrode 64b and output bus 64i formed from metal GM, and the third electrode 62b and output bus 62j formed from metal SM.

As a layer 66 can be used, for example, SiN, SiO2or similar material. As a layer 69 can be used SiN, SiO2the film is based on organic resin or similar material.

When manufacturing the above-described transistor 61, the capacitor 61b is electrically connected to the housing 61A through output bus 62h and 64h, a capacitor 61 is not electrically connected to the housing 61A, the third electrode 62b and the fourth electrode 64b is connected with the electrodes 62 and 64, respectively. After manufacturing in the case of the survey designated L1 leakage between the first electrode a and the second electrode 64A or similar defect to the capacitor 61b do not apply voltage through the output bus 62h and 64h, and the capacitor 61 is electrically connected to the housing 61A through the output bus 62j and the connection s, and through the output bus 64i and connection s. The examination may include control of electric parameters or visa is local control.

In particular, the connection s and output bus 64h and 64i connect with each other in places P1 and P2 of intersection by laser welding so that the fourth electrode 64b is connected to the electrode 64, and the connection s and output bus 62i and 62j connect with each other in places P3 and P4 crossing by laser welding so that the third electrode 62b is connected to the electrode 62. Further, the output bus 64h are melted by a laser beam in place of Q1 between the second electrode 64A and place P1 in such a way that the second electrode 64A is separated from the output bus 64h. In addition, the second electrode 64A is separated from the electrode 64.

Thus, the occurrence of leakage in the capacitor 61b does not lead to malfunction of the transistor 61 in General. This transistor 61 is operable when using the capacitor 61 as an additional accelerating capacitor.

It should be noted that as additional capacitor, such as capacitor 61 are not required to use one additional capacitor. In some implementations you can use a few extra capacitors. In this case, one of them can be selected one additional capacitor for use in the event of a leak.

Example 2

Below with reference to Figure 3 shows opionionated transistor according to this example implementation. The elements denoted by the same positions with the elements depicted in figure 1 and 2 perform the same functions, except when indicated otherwise.

Figure 3 presents a top view of the proposed thin-film transistor 71 is made with the possibility of use as a transistor Tg and installed on panel 2 of the display.

Transistor 71 includes a housing 61A, the capacitor 71 and the connection 72h and 74h. The capacitor 71A performs the function of accelerating capacitor and can be used as a capacitor CAP.

Capacitor 71 is the area in which the first electrodes 72A of the capacitor and the second electrodes a condenser are located one above the other in the thickness direction from opposite sides of the layer 66 of dielectric shutter located between them. The electrodes 72A are in a planar direction with the formation of the comb-like structure from output bus 72h, which, in turn, passes from electrode 62 of the housing 61A. The second electrode a passes from electrode 64 of the housing 61A through connection 74h.

Lead bus 72h connected to the OUT-stage SR, which, in turn, is connected through a contact hole 65 bus GL below in the thickness direction.

The electrodes 72A and output bus 72h formed from metal SM, and the electrode a and lead 74h tire formed the metal GM.

If after making the survey identified the leak that occurred in location L2 leakage in the capacitor 71A at least between one of the electrodes 72A and the electrode a or other reasons, the electrode 72A with space L2 is disconnected from the output bus 72h. In particular, the bus 72h placed at a distance from the region above the electrode a in the thickness direction. The electrode 72A with space L2 upravlyaut laser beam in place Q2. Place Q2 is on an appropriate electrode 72A between the lead bus 72h and the area above the second electrode a in the thickness direction. Thus, the first electrode 72A with space L2 is separated from the output bus 72h. The examination may include control of electric parameters or visual inspection. In case of difficulties in the localization space L2 in any of the electrodes 72A method of monitoring electrical parameters of appropriate conduct visual inspection.

In the electrode 72A can be performed neckline 73 overlapping the boundary on which the electrode 72A, passing from the bus 72h, overlaps the electrode a. In addition, the notches 74 and 75 may be made in the branching pin bus 72h and electrode 72A, i.e. in two locations adjacent to the electrode 72A. This simplifies the determination of the location of the melting by the laser beam, since the notches 73, 74 and 75 can be considered as labels. It should be noted that the electrode 72A is there to be done a few notches 73, and cut-outs 74 and 75 may be made in the electrode 72A.

Capacitance formed between the electrodes 72A and the electrode a (hereinafter referred to as partial tanks), which are parallel to each other. These tanks form a total capacity of 71 (hereinafter referred to as the full capacity). If these partial capacity rather small compared to the full capacity, then removing a small number of electrodes 72A with space L2 from the output bus leads to a slight difference in values full capacity before and after disconnection of the electrodes 72A.

Thus, the leakage in the transistor 71 does not lead to malfunction of the transistor 71 in General. This transistor 71 suitable for operation after a fault in the capacitor 71A.

Example 3

Below with reference to Figure 4 and 5 describes the thin-film transistor according to this example implementation.

4 shows a top view tankcleaning transistor 81, made with the possibility of use as a transistor Tg and installed on panel 2 according to this example implementation.

Transistor 81 includes a housing a, the capacitor 81b and 81s with and connection s and s. Each of the capacitors 81b and 81s with performs the function of accelerating capacitor and can be used as a capacitor CAP.

Case a thin-film transistor them is no grabdevice electrode 82 source and the electrode 83 of the flow, located opposite each other in the plane of the panel above the gate electrode 84 in the direction of thickness so that they interact with each other, which provides greater bandwidth. However, this is only one example of possible configurations. The electrodes 82, 83 and 84 can be placed in any positions and be of any shape.

The capacitor 81b has a region in which the first electrode a and the second electrode a are located one above the other in the thickness direction from opposite sides of the layer 86 of the gate dielectric, the first dielectric layer, see Figure 5)formed between them. The capacitor 81b is also the area where the first electrode a and the third electrode 80A are arranged one above the other in the thickness direction from opposite sides pestiviruses layer 89 (second dielectric layer, see Figure 5)formed between them, and the connection between the first electrode a and the third electrode 80A and between the first electrode a and the second electrode a performed on mutually opposite surfaces of the electrode a. The first electrode a passes from electrode 82 of the housing a through the output bus 82h in a planar direction. The second electrode 84a passes from electrode 84 of the housing a through the output bus 84h (second lead bus) in a planar direction. The third electrode of the capacitor 80A is formed of a transparent electrode T is (see 5). Lead bus 80C (third pin bus) runs from the third electrode 80A and lead bus 80 is connected through a contact hole 85 C lead bus 84d, which passes from electrode 84 in a planar direction.

The first electrode a connected to the OUT-stage SR via the output bus 82i (first pin bus) in a planar direction. The output OUT is connected via the contact hole 85C bus GL, which is located below in the thickness direction.

The capacitor 81s with is located near the capacitor 81b and has a region where the fourth electrode 82b of the capacitor and the fifth electrode of the capacitor 84b are located one above the other in the thickness direction from opposite sides of the layer 86 of the dielectric gate of the third dielectric layer)formed between them. The capacitor also has 81s with the area where the fourth electrode 82b of the capacitor and the sixth electrode 80b of the capacitor are located one above the other in the thickness direction from opposite sides pestiviruses layer 89 (fourth dielectric layer)formed between them, and the connection between the fourth electrode 82b and the sixth electrode 80b and between the fourth electrode 82b and the fifth electrode 84b performed on mutually opposite surfaces of the fourth electrode. The first and third layers of dielectric can be made of different materials. Similarly, W is Roy and fourth dielectric layers can be made of different materials. The sixth electrode. 80b is formed of a transparent electrode TM (see Figure 5). Lead bus 80d runs from the sixth electrode 80b in a planar direction. Lead bus 80d are connected via the contact hole 85b with pin bus e (fifth pin bus), which runs from the fifth electrode 84b in a planar direction. Next, pin the bus 82j (fourth pin bus) runs from the fourth electrode 82b in a planar direction.

In this case, the capacitor 81b and 81s with have the same capacity value.

Connection s (first connection) passes through the output bus 84d and e from above in the thickness direction. Connection s (second connection) passes through the output bus 82i and 82j bottom in the thickness direction.

Figure 5(a) shows a cross-section on the line-In', indicated in figure 4, and figure 5 (b) is a cross-section on the line C-C'indicated in figure 4.

As can be seen from Figure 5, according to the configuration depicted in figure 4, on the glass substrate 60 according to the procedure laid at the foot of the metal layer GM gate layer 86 formed of Si n+layer 87 formed of Si 88 bee, the metal layer SM source, a passive layer 89 and the transparent electrode TM. The electrode 84, the electrode a, lead bus 84d, the connection s and output bus GL is made of a metal layer GM, which is formed in the parallel production process. For example, the metal shutter GM can be is used in the form of a separate layer (or Tap), Ti (or TiN), Al (or alloy, the main component of which Al), Mo (or Mos), SG or in the form of the foot with any combination of these metals. The electrodes 82, 83 and a, lead bus 82i and composition is made of metal SM

which is formed in the parallel production process. Metal SM can be made of the same material or materials as the metal GM. For example, the metal SM can be used as a separate layer (or Tap), Ti (or TiN), Al (or alloy, the main component of which Al), Mo (or Mos), SG or in the form of the foot with any combination of these metals. Further, the third and sixth electrodes 80A, 80b are made of a transparent electrode TM, manufactured simultaneously with the transparent electrode TM is used as the pixel electrode. As a transparent electrode TM can be used, for example, indium oxide and tin, indium oxide and zinc or similar material.

As a layer 86 may be used, for example, SiN, SiO2or similar material. As a layer 89 may be used, for example, SiN, SiO2the film is based on organic resin or similar material.

Layer 87 serves as a channel forming region in the case a. Layer 88 serves as a contact layer between the source and drain which is located between the layer 87 and the electrode 82, and between the layer 87 and the electrode 83.

In addition, as is provided in figure 4, the fifth electrode 84b and output bus e formed from metal GM, and the fourth electrode 82b and tires 82h and 82j formed from metal SM.

When manufacturing the above-described transistor 81 capacitor 81b is electrically connected to the housing a through output bus 82h, 84h and 80C, and the capacitor 81s with not electrically connected to the housing a, since the electrodes 82b, 84b are not connected with the electrodes 82 and 84, respectively. If the survey after fabrication identified leakage resulting from the presence of designated L1 leakage between the first electrode a and the third electrode 80A, to the capacitor 81b do not apply voltage through the output bus 82h and 84h, and lead 82h tires and 80C, and a capacitor electrically connected to the casing 81a through the output bus 82j and connections s and s. The examination may include control of electric parameters or visual inspection.

In particular, the connection s and output bus 84d and I connect with each other in places P5 and P6 crossing by laser welding so that the fifth electrode 84b and the sixth electrode 80b is connected to the electrode 84 and the connection s and output bus 82i and 82j are connected to each other in places P7 and P8 crossing by laser welding so that the fourth electrode 82b is connected to the electrode 82. Further, the output bus 84h upravlyaut laser beam at the midpoint Q3x, a lead bus 80C in the middle point Q3 thus, the second electrode a and the third electrode 80A are separated from the electrode 84.

Thus, the occurrence of leakage in the capacitor 81b thin-film transistor 81 does not lead to malfunction of the transistor 81 in General. This transistor 81 is operable when using condenser 81s with as advanced accelerating capacitor.

Further, the capacitor 81b is placed so that the capacitance formed between the first electrode a and the second electrode a included in parallel with the capacitance formed between the first electrode a and the third electrode 80A. In addition, the capacitor 81s with is so that the capacitance formed between the fourth electrode 82b and the fifth electrode 84b, are connected in parallel with the capacitance formed between the fourth electrode 82b and the sixth electrode 80b. Thus, if the thickness of the layer 86 is equal to the thickness of the layer 89, the area occupied by each capacitor 81b and 81s with panel and defined as H×W (Fig)can be reduced to about half in comparison with the known scheme without parallel. Next, assuming that the thickness of the layer 89 is half of the thickness of the layer 86, the area occupied by each capacitor 81b and 81s with, can be reduced to approximately one third in comparison with the known scheme without parallel. The trail is therefore an additional capacitor can be used to eliminate the negative effect due to the occurrence of leakage without increasing the footprint on the panel all capacitive element.

It should be noted that as additional capacitor, such as capacitor 81s with, not necessarily to use a single capacitor. In some implementations you can use a few extra capacitors. In this case, one of them can be selected one additional capacitor for use in the event of a leak.

Example 4

Below with reference to Fig.6 describes the thin-film transistor according to this example implementation. The elements denoted by identical items with the items shown on Figure 4 and 5 perform the same functions except when specified otherwise.

Figure 6 presents a top view of the thin-film transistor 91, made with the possibility of use as a transistor Tg and installed on panel 2 of the display according to the present primarially.

The transistor 91 includes a housing a, condenser a and connections 92h and 94h. The capacitor a performs the function of accelerating capacitor and can be used as a capacitor CAP.

The condenser 91b has a region in which the first electrodes 92A of the capacitor and the WTO the second electrode a condenser are located one above the other in the thickness direction from opposite sides of the layer 86 of the dielectric gate (first dielectric layer), located between them. The condenser 91b is also the area where the electrodes 92A and the electrode 90A are located one above the other in the thickness direction from opposite sides pestiviruses layer 89 (second dielectric layer)formed between them, and the connection between the electrode 92A and the electrode 90A and between the electrode 92A and the electrode a performed on mutually opposite surfaces of the first electrode of the capacitor. Electrodes 92A are in a planar direction with the formation of the comb-like structure from output bus 92h, which, in turn, passes from the electrode 82 of the housing a. The second electrode a passes from electrode 84 of the housing a through the output bus 94h in a planar direction. Pin bus bar 90 extends from the third electrode 90A, and lead bus 90 is connected through a contact hole 95b with pin bus 84d.

Lead bus 92h connected to the OUT-stage SR, which, in turn, is connected through a contact hole 85C bus GL below in the thickness direction.

The electrodes 92A and lead 92h tire formed from metal SM, and the second electrode a and lead 94h tire formed from metal GM. The third electrode of the capacitor 90A is formed of a transparent electrode TM.

If the survey after manufacturing the above-described transistor 91, identified the leak caused SLE is due to the availability of places L4 leak in the condenser a at least between one of the first electrodes 92A and the second electrode a or at least between one of the first electrodes 92A and the third electrode 90A or caused by other reasons, the first electrode 92A with the location L4 is electrically disconnected from the output bus 92h. In particular, the output bus 92h placed at a distance from the field, the top electrode a in the thickness direction, and a region located below the electrode 90A in the thickness direction. The first electrode 92A with space L4 upravlyaut laser beam in place Q4. Place Q4 are located on the respective first electrode 92A between the lead bus 92h and one of the two regions closest to pin bus 92h: region (i), located on top of the second electrode a in the thickness direction, and the region (ii), below the third electrode 90A in the thickness direction. Thus, the first electrode 92A with the location L4 is separated from the lead 92h tires. The examination may include control of electric parameters or visual inspection. In case of difficulties of localizing L4 in any of the electrodes 92A method of monitoring electrical parameters of appropriate conduct visual inspection.

In the electrode 92A can be performed neckline 93 overlapping the boundary on which the electrode 92A, passing from the output bus 92h, overlaps closest to pin bus 92h electrode: electrode a or 90A. In addition, the notches 94 and 95 can be made in the branching pin bus 72h and electrode 92A, i.e. in two places, premikudu is to electrode 92A. This simplifies the determination of the location of the melting by the laser beam, since the cutouts 93, 94 and 95 can be considered as labels. It should be noted that the electrode 92A can be performed several notches 93 and the notches 94 and 95 can be made in the electrode 72A.

Capacitance formed between the electrodes 92A and the second electrode a (hereinafter referred to as the first partial tanks), one parallel to each other. In addition, capacitance generated between the first electrodes 92A and the third electrode 90A (hereinafter referred to as the second partial vessels), which are parallel to each other. These tanks form the total capacitance a (hereinafter referred to as the full capacity). If the sum of the first and second partial vessels is small enough compared to the full capacity, then disconnecting the first electrode of the capacitor with the location L4 from the output bus 92h leads to a slight difference in values full capacity before and after disconnection of the electrodes 92A.

Thus, the occurrence of leakage in the transistor a does not lead to malfunction of the transistor 91 in General. This transistor 91 suitable for operation after a fault in the capacitor a.

The condenser 91b is set so that the capacitance formed between the first electrode 92A and the second electrode a included in parallel with the containers to form the data between the first electrodes 92A and the third electrode 80A. Thus, the total area grebnevidnoi electrodes 92A can be selected smaller areas of accelerating electrodes of the capacitor is designed as one planar capacitor without increasing the area occupied on the panel all capacitive element.

Above were considered examples of implementation of the invention. In examples 1 and 2, the metal layer SM is located above the metal layer GM, when viewed in the thickness direction. However, this is not the only option. The metal layer SM may be located on the bottom of the metal GM, when viewed in the thickness direction. Further, in examples 3 and 4, the mutual arrangement of the metal layer GM and a transparent electrode TM can be changed to the opposite, provided that the metal layer SM is located between the metal layer GM and a transparent electrode TM.

Further, the shapers of the shutter can be made adjacent to opposite sides of the area 2A or adjacent to one of these parties. Thus, the shaper or shaper shutter can be placed in the correct location.

In addition, thin-film transistor can be used anywhere in the display devices or in applications other than display devices.

The present invention can be used not only in liquid crystal display devices, but also in any other display the devices, for example electroluminescent display device.

The present invention is not limited to the above variants of implementation and includes various changes in the volume of the enclosed formula. Scope of the present invention also includes the combination of technical means disclosed in different embodiments of the invention.

Industrial applicability

The present invention can be used in a display device containing a thin-film transistor.

1. Thin-film transistor containing
the first capacitor containing the area in which the first electrode of the capacitor connected to the source electrode and the second electrode of the capacitor are located on top of each other in the thickness direction from opposite sides of the first dielectric layer, formed between them;
a second capacitor that contains the area in which the third and fourth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the second dielectric layer, formed between them;
the first output bus, passing from the first electrode of the capacitor in a planar direction;
a second output bus, passing from the gate electrode in a planar direction;
the third output bus, passing from the third electrode of the capacitor in the plane on which the sun was behind a cloud;
the fourth output bus, passing from the fourth electrode of the capacitor in a planar direction;
the first connection crossing the second and fourth output bus, when viewed in the thickness direction; and
a second connection crossing the first and third output bus, when viewed in the thickness direction, and
the second electrode of the capacitor and the gate electrode are connected to each other through the second output bus,
the third electrode of the capacitor and the source electrode are not connected with each other,
the fourth electrode of the capacitor and the gate electrode are not connected to each other.

2. Thin-film transistor according to claim 1, in which
the first and third electrodes of the capacitor, the first and third output bus, and a first connection is made from a metal source, and the second and fourth electrodes of the capacitor, the second and fourth output bus, and a second connection is made from a metal shutter.

3. Thin-film transistor according to claim 1, in which
the first and second dielectric layers are dielectric layer of the gate.

4. Thin-film transistor according to claim 1, which is fabricated using amorphous silicon or microcrystalline silicon.

5. Thin-film transistor containing
the first capacitor is designed so that the first electrode of the capacitor connected to the e is STRADOM source, and the second electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the first dielectric layer located between them;
the second capacitor is designed so that the third electrode of the capacitor and the fourth electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the second dielectric layer located between them.
the first output bus, passing from the first electrode in a planar direction;
a second output bus, passing from the gate electrode in a planar direction;
the third output bus, passing from the third electrode in a planar direction;
the fourth output bus, passing from the fourth electrode in a planar direction;
the first connection crossing the second and fourth output bus, when viewed in the thickness direction; and
a second connection crossing the first and third output bus, when viewed in the thickness direction, and
the second electrode of the capacitor and the gate electrode are not connected to each other;
the first and third output bus is connected to the second connection so that the third electrode of the capacitor and the source electrode Sweeney with each other,
the second and fourth output bus connected to the first connection so that the fourth e is ctred and the gate electrode are connected to each other.

6. Thin-film transistor according to claim 5, in which
the first and third electrodes of the capacitor, the first and third output bus, and a first connection is made from a metal source, and
the second and fourth electrodes of the capacitor, the second and fourth output bus, and a second connection is made from a metal shutter.

7. Thin-film transistor according to claim 5, in which
the first and second dielectric layers are dielectric layer of the gate.

8. Thin-film transistor according to claim 5, which is fabricated using amorphous silicon or microcrystalline silicon.

9. Thin-film transistor containing the output bus connected to the source electrode; and a capacitor that contains the area in which the first electrode of the capacitor and the second electrode of the capacitor connected to the gate electrode, are located one above the other in the thickness direction from opposite sides of a dielectric layer formed between them, and the first electrodes of the capacitor are from the output bus in a planar direction.

10. Thin-film transistor according to claim 9, in which
each of the first electrode of the capacitor includes a steam bath part, forming a pair with the second electrode of the capacitor, located in the area of the capacitor, and a single part, not forming a pair with the second electrode and in passing from the water bus to the pair.

11. Thin-film transistor of claim 10, in which
in the first electrode of the capacitor on the border between the unpaired part and part of the steam and/or lead in the bus, in place of razvetvleniya the first electrode of the capacitor and the output bus made the cut.

12. Thin-film transistor according to any one of p-11, in which
the first electrode of the capacitor and discharging the tire is made of metal source, and
the second electrode of the capacitor made of a metal shutter.

13. Thin-film transistor according to any one of p-11, in which
as the dielectric layer used in the dielectric layer of the gate.

14. Thin-film transistor according to any one of p-11, which
manufactured using amorphous silicon
or microcrystalline silicon.

15. Thin-film transistor, comprising:
the first capacitor, which has an area in which the first electrode of the capacitor connected to the source electrode and the second electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the first dielectric layer, formed between them, and the area in which the first and third electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the second dielectric layer, formed between them, so that the connection between the first and third electrodes is of condensator and the connection between the first and second electrodes of the capacitor are made on mutually opposite surfaces of the first electrode of the capacitor;
a second capacitor, which has an area in which the fourth and fifth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the third dielectric layer formed between them; and the area in which the fourth and sixth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the fourth dielectric layer, formed between them, so that the connection between the fourth and sixth electrodes of the capacitor and connecting the fourth and fifth electrodes of the capacitor are made on mutually opposite surfaces of the fourth electrode of the capacitor;
the first output bus, passing from the first electrode of the capacitor in a planar direction;
a second output bus, passing from the second electrode of the capacitor in a planar direction;
the output bus of the shutter extends from the gate electrode in a planar direction;
the third output bus, passing from the third electrode of the capacitor in a planar direction;
the fourth output bus, passing from the fourth electrode of the capacitor in a planar direction;
the fifth pin bus that goes from the fifth electrode of the capacitor in a planar direction;
the first connection, cross pin bus speed and the fifth vivado the bus, when viewed in the thickness direction; and
a second connection crossing the first and the fourth output bus, when viewed in the thickness direction, and
the third electrode of the capacitor and the gate electrode are connected to each other through a third output bus
the sixth electrode of the capacitor is connected to the fifth pin of the bus, the second electrode of the capacitor and the gate electrode are connected to each other through the second output bus,
lead bus speed and the fifth pin bus is not connected with the first connection,
lead bus speed and the fourth lead bus is not connected with the second connection.

16. Thin-film transistor according to item 15, in which
the first and fourth electrodes of the capacitor, the first and the fourth output bus, and a first connection is made from a material source,
the second and fifth electrodes of the capacitor, the second and fifth output bus, and a second connection is made from a metal shutter, and
the third and sixth electrodes of the capacitor and the third lead, the tire is made of transparent electrodes.

17. Thin-film transistor according to item 15, in which
the first and third layers of dielectric used as a dielectric layer of the gate, and
the second and fourth dielectric layers used as pestiviruses layer.

18. Thin-film transistor according to clause 15, which
manufactured using the receiving amorphous silicon
or microcrystalline silicon.

19. Thin-film transistor, comprising:
the first capacitor, which has an area in which the first electrode of the capacitor connected to the source electrode and the second electrode of the capacitor are located one above the other in the thickness direction from opposite sides of the first dielectric layer, formed between them, and the area in which the first and third electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the second dielectric layer, formed between them, so that the connection between the first and third electrodes of the capacitor and the connection between the first and second electrodes of the capacitor are made on mutually opposite surfaces of the first electrode of the capacitor;
a second capacitor, which has an area in which the fourth and fifth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the third dielectric layer formed between them; and a second area in which the fourth and sixth electrodes of the capacitor are located one above the other in the thickness direction from opposite sides of the fourth dielectric layer, formed between them, so that the connection between the fourth and sixth electrodes of the capacitor and the connection is between the fourth and fifth electrodes of the capacitor are made on mutually opposite surfaces of the fourth electrode of the capacitor;
the first output bus, passing from the first electrode in a planar direction;
a second output bus, passing from the second electrode in a planar direction;
the output bus of the shutter extends from the gate electrode in a planar direction;
the third output bus, passing from the third electrode in a planar direction;
the fourth output bus, passing from the fourth electrode of the capacitor in a planar direction;
the fifth pin bus that goes from the fifth electrode in a planar direction;
the first connection, cross pin bus speed and the fifth pin of the bus, when viewed in the thickness direction; and
a second connection, purescale the first and fourth output bus, when viewed in the thickness direction, and
the third electrode of the capacitor and the gate electrode are not connected with each other,
the sixth electrode of the capacitor is connected to the fifth pin of the bus,
the second electrode and the gate electrode are not connected with each other,
lead bus speed and the fifth output bus connected to the first connection so that the fifth and sixth electrodes of the capacitor is connected to the electrode of the gate,
the first and the fourth output bus is connected to the second connection so that the fourth electrode of the capacitor and the source electrode are connected.

20. The tone is openecry transistor according to claim 19, in which
the first and fourth electrodes of the capacitor, the first and the fourth output bus, and a first connection is made from a material source,
the second and fifth electrodes of the capacitor, the second and fifth output bus, and a second connection is made from a metal shutter, and
the third and sixth electrodes of the capacitor and the third lead, the tire is made of transparent electrodes.

21. Thin-film transistor according to claim 19, in which
the first and third layers of dielectric used as a dielectric layer of the gate, and
the second and fourth dielectric layers used as pestiviruses layer.

22. Thin-film transistor according to claim 19, which
manufactured using amorphous silicon
or microcrystalline silicon.

23. Thin-film transistor, comprising:
the output bus is connected to the source electrode; and
the capacitor, which has an area in which the first electrodes of the condenser, passing from the output bus in a planar direction, and a second electrode connected to the gate electrode, are located one above the other in the thickness direction from opposite sides of the first dielectric layer, formed between them, and the area in which the first electrode of the capacitor and the third electrode of the capacitor connected to the gate electrode, are located one above the other in EmOC is the thickness t from opposite sides of the second dielectric layer, formed between them, so that the connection between the first and third electrodes of the capacitor and the connection between the first and second electrodes of the capacitor are made on mutually opposite surfaces of the first electrode of the capacitor.

24. Thin-film transistor according to item 23, in which
each of the first electrode of the capacitor has a steam room part, forming a pair with those located in the region of the capacitor of the second and third electrodes of the capacitor, which is located closer to the lead bus, and a single part, not forming a pair with the second and third electrodes of the capacitor and passing from the output bus to the pair.

25. Thin-film transistor according to paragraph 24, in which
in the first electrode of the capacitor on the border between the unpaired part and part of the steam and/or lead in the bus, in place of razvetvleniya the first electrode of the capacitor and the output bus, made the cut.

26. Thin-film transistor according to any one of p-25, in which
the first electrode of the capacitor and lead a tire formed from a metal source,
the second electrode of the capacitor made of a metal shutter, and
the third electrode of the capacitor is made of a transparent electrode.

27. Thin-film transistor according to any one of p-25, in which
as the first dielectric layer selected layer of gate dielectric, and kacestvennogo dielectric layer is selected passivating layer.

28. Thin-film transistor according to any one of p-25, which is fabricated using amorphous silicon or microcrystalline silicon.

29. Shift register containing stage consisting of transistors, in which
at least one of the transistors is a thin film transistor according to any one of claims 1 to 11 and 15 to 28.

30. The control circuit bus signals sweep containing the shift register according to clause 29, which
the shift register used to generate a sweep signal to the display device.

31. The control circuit bus signals scan on item 30, in which
as a thin-film transistor used in an output transistor that outputs a signal sweep.

32. Display device containing the circuit control bus signals scan on item 30 or 31.

33. The display device according to p, in which
the control circuit bus scan signals formed on the display panel and monolithic integrated with the display area.

34. Display device containing the display panel, in which is formed a thin-film transistor according to any one of claims 1 to 11 and 15 to 28.

35. The method of adjustment thin-film transistor according to claim 1, according to which
the second electrode of the capacitor and the gate electrode are to be separated by melting the second output bus;
the first and third turn is derivative tires are welded to the second connection; and
the second and fourth output bus are welded to the first connection.

36. The method of adjustment thin-film transistor according to claim 9 or 23, according to which
at least one of the first electrode of the capacitor is disconnected from the output bus by melting.

37. The method of adjustment thin-film transistor according to § 15, according to which:
the third electrode of the capacitor and the gate electrode are to be separated by melting the third output bus;
weld the sixth electrode of the capacitor to the fifth pin of the tire;
the second electrode of the capacitor and the gate electrode are to be separated by melting the second output bus;
lead bus speed and the fifth output bus are welded to the first connection; and
the first and fourth output bus are welded to the second connection.



 

Same patents:

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FIELD: electricity.

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7 cl, 10 dwg

FIELD: physics.

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9 cl, 13 dwg, 6 ex

FIELD: chemistry.

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6 cl, 8 dwg

Field transistor // 2390072

FIELD: electricity.

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4 cl, 4 dwg, 2 ex

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9 cl, 25 dwg

FIELD: physics.

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6 cl, 8 dwg

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FIELD: physics, radio.

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21 cl, 12 dwg

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4 cl, 2 dwg

FIELD: electricity.

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33 cl, 18 dwg

FIELD: physics.

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1 tbl

FIELD: electricity.

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6 cl, 6 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: manufacturing method of SHF LDMOS transistors includes growth of thick field dielectric at surface of high-ohmic epitaxial p- -layer of source silicone p-p+-substrate at periphery of transistor configurations, formation of source p+-junctions and p-wells of transistor cells in epitaxial p- -layer of substrate not covered with field dielectric, growth of gate dielectric and formation of polysilicone electrodes of transistor cells gate in the form of narrow lengthwise teeth of rectangular section with close adjoining tapped contact pads from source side over p-wells, creation of high-alloy n+-areas of sink, source and low-alloy n-area of transistor cells by introduction and further diffusion redistribution of donor dopant using gate electrodes as protective mask, formation of metal electrodes of sinking, source, screens and buses shunting gate electrodes of transistor cells through tapped contact pads at substrate face and common metal source electrode of transistor configuration at backside, the first degree of low-alloy multistage n-area of transistor cell source is formed after formation of source p+-junctions by introduction of donor dopant to epitaxial p--layer of substrate without usage of protective masks, p-wells, sink and source areas of transistor cells are created with use of additional dielectric protective mask identical in configuration and location of lengthwise teeth of polysilicone gate electrode without tapped contact pads adjoining to them, simultaneously with p-wells similar areas are formed at edges of low-alloy n-area of transistor cells sink and gate electrodes with tapped contact pads adjoining to teeth are formed after removal of additional dielectric protective mask and subsequent growth of gate dielectric, at that width of polysilicone gate electrode teeth are selected so that it exceeds length of transistor cell induced channel per overlay error value.

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7 dwg

FIELD: electricity.

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11 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: in manufacturing method of semiconductor device, which involves processes of ion implantation and formation of active areas of instrument on silicon substrate, after formation of active areas there created is hidden p-layer under channel of instrument by alloying of substrate with Be ions with energy of 125-175 keV, dose of (2-5)·1012 cm-2 and with further annealing at 650-750°C during 20-30 minutes and H2 atmosphere.

EFFECT: reducing leakage current values in semiconductor devices, providing processibility, improving parameters, reliability and increasing percentage yield.

FIELD: physics.

SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.

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9 cl, 13 dwg, 6 ex

FIELD: physics; semiconductors.

SUBSTANCE: invention concerns electronic semiconductor engineering. Essence of the invention consists in the manufacturing method of SHF powerful field LDMOS-transistors, including forming of a primary sheeting on a face sheet of an initial silicon body with top high-resistance and bottom high-alloy layers of the first type of conductance, opening of windows in a primary sheeting, sub-alloying of the revealed portions of silicon an impurity of the first type of conductance, cultivation of a thick field dielectric material on the sub-alloying silicon sites in windows of a primary sheeting thermal oxidising of silicon, creation in a high-resistance layer of a substrate in intervals between a thick field dielectric material of elementary transistor meshes with through diffused gate-source junctions generated by means of introduction of a dopant impurity of the first type of conductance in a substrate through windows preliminary opened in a sheeting and its subsequent diffused redistribution, forming of connecting busbars and contact islands of a drain and shutter of transistor structure on a thick field dielectric material on a face sheet of a substrate and the general source terminal of transistor structure on its back side, before silicon sub-alloying and cultivation of a thick field dielectric material in windows of a primary sheeting a high-resistance layer of a substrate is underetched on the depth equal 0.48 - 0.56 of thickness of a field dielectric material, and before dopant impurity introduction in the formed source crosspieces of transistor meshes in a high-resistance layer of a substrate in sheeting windows etch a channel with inclined lateral walls and a flat bottom depth of 1.5 - 2.6 microns.

EFFECT: improvement of electric parametres of SHF powerful silicon LDMOS transistors and increase of percentage output of the given products.

5 dwg, 2 tbl

FIELD: physics.

SUBSTANCE: invention relates to semiconductor technology. The method of making power insulated-gate field-effect transistors involves making a protective coating with a top layer of silicon nitride on the face of the initial silicon nn+ or pp+ - substrate, opening windows in the protective coating, making channel regions of transistor cells in the high-resistivity layer of the substrate and heavily-doped by-pass layers and source regions inside the channel regions using ion implantation of doping impurities into the substrate through windows in the protective coating and subsequent diffusion distribution of implanted impurities. When making by-pass layers, the doping mixture is implanted into the substrate through windows in the protective coating without using additional masking layers. After diffusion redistribution of implanted impurities in by-pass layers on the entire perimetre of windows in the protective coating, selective underetching of lateral ends of the protective coating under silicon nitride is done. The silicon nitride layer is then removed from the entire face of the substrate and source regions of the transistor cells are formed through implantation of doping impurities into the substrate through windows in the protective coating.

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5 dwg, 1 tbl

FIELD: integrated-circuit manufacture on silicon-on-insulator substrate; transistor structures of extremely minimized size for ultra-high-speed integrated circuits.

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EFFECT: reduced length of transistor structure channel.

2 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: substrate comprises outer connecting contact outputs, lower conductors stretching below outer connecting contact outputs, an interlayer insulating film, placed between outer connecting contact outputs and lower conductors, and connecting holes, through which outer connecting contact outputs are connected to lower conductors. A display device comprising a substrate.

EFFECT: reduced area of a frame and increased reliability due to prevention of connection damages.

12 cl, 23 dwg

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