System and method for selectively applying negative voltage to wordlines during memory device read operation

FIELD: information technology.

SUBSTANCE: read signal is applied to a bit line connected to a memory array including a plurality of memory cells, each of the plurality of memory cells having a magnetic tunnel junction (MTJ) device; positive voltage is applied to a selected word line connected to a selected memory cell of the memory array; negative voltage is applied to unselected word lines connected to the memory array; and the negative voltage is applied to each word line during a standby state.

EFFECT: reduced stray current in magnetic random access memory.

25 cl, 7 dwg

 

The technical field to which the invention relates

The present disclosure entity, in General, relates to a system and method of reducing leakage current in a magnetic random access memory device (MRAM).

Description of the prior art

Technological improvements have led to more compact and with high computational power of personal computing devices. For example, today there are many portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and pagers, which are small, lightweight and conveniently worn by the user. More specifically, portable wireless telephones, such as cellular phones and IP phones can transmit the voice packets and data packets over wireless networks. Additionally, many of these cordless phones include other types of devices that are contained within them. For example, a wireless telephone may also include a digital camera, digital video camera, a digital recorder and audio player. In addition, these wireless phones can handle executable instruction, which includes applications such as prilojenie browser, which can be used to access the Internet. In fact, these cordless phones include significant computing capabilities.

Improvements in the design of electronic circuits provide improved performance of electronic devices, including increasing the speed and reducing the power consumption to improve battery life for portable devices. Although new technologies storage devices such as magnetic random access memory (MRAM) and magnetoresistive storage device with random access (STT-RAM), offer the potential for rapid operation of the read/write low power, these devices often have a small stock of reading, which leads to difficulties in reliable current reading and detection of reading. In addition, such devices are often subject to leakage current. Leakage current often affects the device's ability to read data at low voltages, because the stock of the read current is reduced by the leakage current.

The invention

In a specific embodiment, disclosed a method of reading data from the matrix memory comprising a device for magnetic tunnel junctions (MTJ). The method includes the signal of sityva the Oia bit bus, connected to the matrix memory that includes multiple memory cells. Each of the multiple memory cells includes a MTJ device. The method includes the application of a positive voltage to a selected bus of words connected with the selected memory cell matrix memory. The method further includes a negative voltage to unselected buses words, connected to the matrix memory.

In another specific embodiment, the memory device includes a matrix of memory cells. Each of the memory cells in the matrix of memory cells includes a device for magnetic tunnel junctions (MTJ). The memory device also includes a set of bit tire, connected to the matrix of memory cells. The memory device additionally includes many tyres words connected with a matrix of memory cells. The memory device includes a logic bit bus connected to the set of bit tire and made with the possibility to signal read one of the many bit of the tire, connected with the selected memory cell matrix of memory cells. The memory device includes a logic circuit bus words connected with many tyres words and configured to selectively apply a positive voltage to the selected bus words the C set of tyres words. The selected tyre words connected with the selected memory cell. Logic bus words applies a negative voltage to unselected buses words, connected to the matrix memory. Unselected bus words include each of the tires of words, in addition to the selected bus words.

In another specific embodiment, the memory device includes a logic circuit bus words connected with many tyres words and configured to selectively apply a positive voltage to a selected bus of words connected with the selected memory cell, which includes a device for magnetic tunnel junctions (MTJ), and applying a negative voltage to unselected buses words.

In another specific embodiment disclosed storage device. The memory device includes a means for the application of the signal read to the bit bus connected to the matrix memory that includes multiple memory cells. Each of the multiple memory cells includes a device for magnetic tunnel junctions (MTJ). The memory device also includes a means for application of a positive voltage to a selected bus of words connected with the selected memory cell matrix memory. The memory device additionally includes cf the rotary for the application of negative voltage, at least one unselected bus words connected with the matrix memory.

In another specific embodiment, disclosed is a wireless device that includes a processor and a wireless controller, responsive to the processor. The wireless device also includes a storage device, coupled to the processor. The memory device includes a logic circuit bus words connected with many tyres words and configured to selectively apply a positive voltage to a selected bus of words connected with the selected memory cell containing a device for magnetic tunnel junctions (MTJ), and applying a negative voltage to unselected buses words.

One particular advantage provided by disclosed embodiments is to improve the performance at low operating voltages due to increased maximum allowable current reading memory. Another particular advantage is the reduction of the power consumption due to reduced leakage current in the matrix memory.

Other aspects, advantages and features of the present invention should become apparent from reading the entire proposal, including the following sections: Brief description of the drawings, Detailed description of the invention" is "claims".

Brief description of drawings

Figure 1 is a block diagram of a particular illustrative variant implementation of the system for the application of negative voltage, at least one bus word during read operations from the memory;

figure 2 is a diagram of a second illustrative variant implementation of the system for the application of negative voltage, at least one bus word during read operations from the memory;

figure 3 is a diagram illustrating reserves perception of current when reading data;

figure 4 is a diagram of a third illustrative variant implementation of the system for the application of negative voltage, at least one bus word during a read operation of the memory device;

figure 5 is a diagram illustrating reserves perception voltage when reading data;

6 is a flowchart of the sequence of operations of a particular variant of the method of reading data from the matrix memory comprising a device for magnetic tunnel junctions (MTJ); and

7 is a block diagram of a wireless communication device that includes the memory device with logic read a negative voltage.

Detailed description of the invention

Referring to figure 1, illustrated in particular is Ariant the implementation of the system for the application of negative voltage to the bus words during read operations from the memory, generally denoted 100. The system 100 includes a matrix 102 of the memory cells connected to the logic circuit 106 bit bus through a set of bit tire 104. The matrix 102 of the memory cells are also connected to the logic circuit 110 bus words through multiple bus 108 words. Logic circuit 110 bus words connected to a source 112 of a positive voltage (V)ground (GRD) system 114 and the source 116 negative voltage (NV).

In a particular embodiment, the matrix 102 of the memory cells includes a matrix of devices on magnetic tunnel junctions (MTJ). Each MTJ device stores at least one data value is represented by the resistance across the MTJ device. Resistance may result from the relative alignment of the two magnetic fields in the MTJ device that can be programmed by applying the write current to the MTJ device. In a specific embodiment, each cell in the memory matrix 102 of the memory cells can be read by application of a signal to select a cell to a corresponding one of the multiple tires of words 108 and a corresponding one of the multiple bit tire 104.

In a particular embodiment, the logic circuitry 110 bus words performed with the ability to selectively apply a positive voltage to a selected bus of words, which is distesa with the selected memory cell, and selectively applying a negative voltage to unselected buses words, connected to the matrix memory. Unselected bus words may include each of the multiple tires of 108 words, in addition to the selected bus words. For example, the logic circuitry 108 bus may be configured to selectively connect one of the multiple tires of words 108 source 112, a positive voltage (V) and simultaneously to connect the rest of the multiple tires of words 108 source 116 negative voltage (NV). In a particular embodiment, although some or all of the electronic components (not shown) in the logic circuit 110 bus words operate using a source 112 of a positive voltage (V) and the system ground (GND) 114, the logic circuitry 110 bus words applies only positive or negative voltage, and not the system grounding to multiple tire 108 words.

During operation, the logic circuitry 110 bus may determine the selected tyre words corresponding to the selected memory cell matrix 102 of memory cells, and logic circuitry 106 bit bus can determine the selected bit bus corresponding to the selected memory cell. Logic circuit 110 bus may apply a positive voltage to a selected bus of the words and the negative voltage to unselected buses words, then what and how logic bit bus can make a positive voltage to the selected bit bus and the system ground to the unselected bit buses. Through the application of a negative voltage to unselected buses words leakage current of the memory cells connected to unselected dictionary tires is reduced, providing a more precise determination of the current and, consequently, the resistance of the selected memory cell. In a specific embodiment, the reduced leakage current also provides a smaller element size and provides increased density matrix memory, lower the system voltage, reduced currents during data records due to more sensitive reads data, the increased number of memory cells on the bus words and the large size of the matrix, or any combination of the above.

As illustrative, non-limiting example, a positive voltage may be between approximately 3.3 V (standard voltage for other electronic devices) and approximately 0.7 V (for example, for technology 22 nm or 32 nm), and in the specific example may be between approximately 1.2 and approximately 2 C. Similarly, in the illustrative, non-limiting example, the negative voltage may be in the range of approximately of-0.2 V to about-0.5 In, so that a negative voltage may be large enough to significantly reduce the leakage current, but not large enough to that is ativate a negative effect on your device performance. Although provided illustrative examples of the ranges of electric potential, any positive and negative voltages can be used depending on the particular implementation.

Referring to figure 2, illustrates the second illustrative version of the implementation system for the application of negative voltage to the bus words during read operations from memory, generally denoted 200. The system 200 includes a matrix of memory cells, such as the typical cell of the memory 220. The buffer 202 tyres words connected with a set of tyres words (WL0, WL1, ..., WLn) 204, which are connected with a matrix of memory cells. The set of bit buses (BL0, BL1, ..., BLn), which includes a typical bit bus BL0 212, is connected with a matrix of memory cells and additionally connected with the logic circuit 214 bit bus. The matrix of memory cells are additionally connected with a set of tyres source (SL0, SL1, ..., SLn). The device 230 comparison compares the signal in a typical bit bus 212 to the signal at the reference bus 232 to generate an output signal 234, which indicates the value stored in the selected memory cell.

In a particular embodiment, each memory cell includes a device for magnetic tunnel junctions (MTJ), such as a typical MTJ device 222 that is connected to the switching device, such as a typical transistor 224. Each MT device may include a free layer, fixed layer and the tunnel junction, for example a typical free layer 260, the tunneling 262 and a fixed layer 264 MTJ device 222. Fixed layer 264 may include virtually fixed magnetic field having a first orientation, and a free layer 260 may include a magnetic field having a programmable orientation. When the magnetic field in the free layer 260 is oriented so as to coincide with the first orientation, the resistance to an electric current through the free layer 260 and the fixed layer 264 through the tunnel passage 262 is lower than in the case when the field have opposite orientation. In a particular embodiment, the MTJ device operates as a magnetoresistive device (spin transfer torque) (STT).

Logic circuit 214 bit bus is configured to alert the reader to one of the set of bit tire BL0, BL1, ..., BLn, which is connected with the selected memory cell matrix of memory cells. In a particular embodiment, the signal read is the voltage readout applied to bit bus 212, when the cell memory 220 is selected.

In a particular embodiment, the buffer 202 tyres words includes a logic circuit 240 controls connected with a set of agents, which includes the typical causative agent 242. It is jdy exciter is connected with the corresponding dictionary bus from a set of tyres words 204, a source of positive voltage (Vdd) and the source of negative voltage (NV). Each agent can be configured to selectively connect the Vdd source or NV-source with the corresponding bus of words based on the input received from the logic circuit 240 controls.

In a particular embodiment, the logic circuitry 240 is a control with the ability to selectively apply a positive voltage Vdd to the selected bus of words, which is connected with the selected memory cell, and applying a negative voltage to unselected buses words, connected to the matrix memory. In a particular embodiment, the logic circuitry 240 is a control with the ability to apply a negative voltage to each of a set of tyres words 204, in addition to the selected bus words, by instructing each device excitation unselected bus words to connect unselected bus words with a source of negative voltage (NV). In a particular embodiment, control logic 240 may also be configured to provide the negative voltage to each of the set of tires of 204 words, when none of the tires of the words is not selected, for example, during the waiting state.

During operation, in a particular embodiment, the memory cell is selected for operation when edyvane, such as cell memory 220. The buffer 202 tyres words can selectively connect the selected tyre words (WL0) with a source of positive voltage and connect unselected bus words (WL1, ..., WLn) with a source of negative voltage using the logical control circuit to instruct each excitation device for selectively connecting the corresponding bus words or with a source of positive voltage (Vdd)or to a source of negative voltage (NV). In a specific embodiment, the unselected bus words include at least one from a set of tyres words 204, in addition to the selected bus words.

In a particular embodiment, the application of the negative voltage increases the stock of reading the selected cell 220 memory, since the negative voltage is sufficient to reduce the leakage current of the unselected memory cells. Thus, when a negative voltage is applied to unselected buses words WL1, ..., WLn, but is not applied to the selected bus words WL0, the resulting current Iread read mainly determined by the current Iread1 read through the selected cell 220 memory, and not by leakage currents from other memory cells connected to bit bus 212. Thus, the data values specified by the different levels of read current is of consequence magnetoresistive effects in the selected cell memory 220, may vary according to the "noise" in the current reading, caused by leakage current. In a specific embodiment, the negative voltage is less than 0.5 volts, and as a non-limiting example may be about 0.2 volts less than the voltage system grounding.

In a particular embodiment, the device 230 comparison includes a read amplifier current (CSA)made with the possibility to compare current Iread read in bit bus 212 with the reference current Iref and to generate an output signal 234 on the basis of comparison. For example, when Iread<Iref, the output signal 234 may be a logical value "1", and when Iread>=Iref, the output signal 234 may be a logical value "0". Although the device 230 comparison is illustrated as comparing the current reading with the reference current, which is sensitive to voltage in the memory cell (for example, the potential difference applied between bit bus BL0 and bus SL0 source), other modes of operation will be obvious to experts in the art as being within the scope of the present disclosure. For example, as further described in connection with figure 4, the device 230, the comparison may compare the voltage in bit bus 212 with a reference voltage in response to the flow of current in the cell memory 220. As another example the a, the device 230 of comparison may be configured to determine the amplitude and sign of the input signal, and not to perform a direct comparison with a reference signal.

In a particular embodiment, the system 200 may be included in one or more other components or devices. For example, the system 200 may be part of a random access memory (RAM). In the illustrative embodiment, each MTJ device, such as a typical MTJ device 222 may be located in the bit cell magnetoresistive memory with random access (STT-RAM), and the amplifier of the read current may connect to one or more of the bit cell.

Referring to figure 3, is shown an illustration of stocks read current to read data associated with the read storage device for magnetic tunnel junctions (MTJ), generally denoted 300. Level 302 of the reference current (Iref) is illustrated as a lower level 304 current read value "0" (Iread0) and higher than the level 306 current reading for the value "1" (Iread1) on the vertical axis. Stock 312 reads ' 1 ' indicates the difference between the level 302 of the reference current and the level 306 current reading for the value "1". Stock 310 read "0" illustrates the difference between the level 304 current read value "0" and level 302 of the reference current.

the illustrative embodiment, level 302 of the reference current may correspond to a reference signal Iref 232, and the levels 304 and 306 current reading may correspond to the respective values of current Iread1 read, when the data value "0" or "1" is read in the cell memory 220 of the system 200 of figure 2, in the absence of leakage current from the other memory cells. Each of the stocks 310 and 312 reader can imagine the tolerance for noise associated with the read operation, so that the maximum acceptable level of random noise is the lesser of the stocks 310 and 312 are read. Thus, tolerance to random noise increases when stocks 310 and 312 are read approximately equal.

However, the leakage current generated through the unselected memory devices connected to the bus, the read data is added to the full current on the bus reading data, shifting the level of current reading for the values "0" and the level of current reading for the value "1" to the lagged levels 322 and 324, respectively. When the level 302 of the reference current does not move, the new stock of 326 reading "0" is incremented, and the new stock 328 shift to read "1" is reduced in comparison with previous inventories 310 and 312, respectively. The total tolerance for noise, therefore, decreases as the amplitude of noise that exceeds the lesser of the two new stocks 326 and 328 shift to read, the mod is no lead to erroneous result.

The leakage current generated through the unselected memory devices, may be reduced by application of negative voltage to the tires of words connected with the unselected devices. The negative voltage may be selected to return the stocks read almost equal to the values 310 and 312. Thus, the dimensions of the elements of the matrix memory can be reduced, additional devices to be added to the tires of reading data, the working voltage can be reduced, or any combination of the above to be performed with reduced negative effects.

Referring to figure 4, illustrated is a third illustrative version of the implementation system for the application of negative voltage to the bus words during read operations from memory, generally denoted 400. The system 400 includes a matrix of memory cells, such as a typical cell in the memory 420. The buffer 402 tyres words connected with a set of tyres words (WL0, WL1, ..., WLn) 404, which are connected with a matrix of memory cells. The set of bit buses (BL0, BL1, ..., BLn), which includes a typical bit bus BL0 412 connects to the matrix of memory cells and additionally connected with a logic circuit 414 bit bus. The matrix of memory cells are additionally connected with a set of tyres source (SL0, SL1, ..., SLn). The device 430 comparison voltage, compares the voltage Vread in obichnoi bit bus 412 with reference voltage Vref 432, in order to form an output signal 434, which indicates the value stored in the selected memory cell.

In a particular embodiment, each memory cell includes a device for magnetic tunnel junctions (MTJ), such as a typical MTJ device 422, coupled with the switching device, such as a typical transistor 424. Each MTJ device may include a free layer, a fixed layer and the tunnel junction, for example, a typical free layer 460, the tunneling 462 and a fixed layer 464 MTJ device 422. Fixed layer 464 can include almost fixed magnetic field having a first orientation, and a free layer 460 may include a magnetic field having a programmable orientation. When the magnetic field in the free layer 460 is oriented so as to coincide with the first orientation, the resistance to an electric current through the free layer 460 and the fixed layer 464 through the tunnel passage 462 is lower than in the case when the field have opposite orientation. In a particular embodiment, the MTJ device operates as a magnetoresistive device (STT).

In a particular embodiment, the logic circuitry 414 bit bus is configured to alert the reader to one of the set of bit tire BL0, BL1, ..., BLn, which soy is inane with the selected memory cell matrix of memory cells, by application of a current read bit to bus 412, when the cell memory 420 is selected.

In a particular embodiment, the buffer 402 tyres words includes a logic circuit 440 controls connected to the set of devices of excitation, which includes typical excitation device 442. Each device excitation is connected with the corresponding bus of words from a set of tyres words 404, a source of positive voltage (Vdd) and the source of negative voltage (NV). Each excitation device may be configured to selectively connect the Vdd source or NV-source with the corresponding bus of words based on the input received from the logic circuit 440 controls.

In a particular embodiment, the logic circuitry 440 control is configured to selectively apply a positive voltage Vdd to the selected bus of words, which is connected with the selected memory cell, and applying a negative voltage to unselected buses words, connected to the matrix memory. In a particular embodiment, the logic circuitry 440 control is designed with the ability to apply a negative voltage to each of the set of tires of words 404, in addition to the selected bus words, by instructing each device excitation unselected bus words to not connect the selected tyre words with a source of negative voltage (NV). In a particular embodiment, control logic 440 may also be performed with the opportunity to apply the negative voltage to each of the set of tires of 404 words, when none of the tires of the words is not selected, for example, during the waiting state.

During operation, in a particular embodiment, the memory cell selected for read operations, such as cell 420 memory. The buffer 402 tyres words can selectively connect the selected tyre words (WL0) with a source of positive voltage and connect unselected bus words (WL1, ..., WLn) with a source of negative voltage using the logical control circuit to instruct each excitation device for selectively connecting the corresponding bus words or with a source of positive voltage (Vdd)or to a source of negative voltage (NV). In a specific embodiment, the unselected bus words include at least one from a set of tyres words 404, in addition to the selected bus words.

In a particular embodiment, the application of the negative voltage increases the stock of reading the selected cell 420 memory, since the negative voltage is sufficient to reduce the leakage current of the unselected memory cells. Thus, when a negative voltage is applied to unselected tire is m words WL1, ..., WLn, but is not applied to the selected bus words WL0, the resulting voltage Vread read mainly determined by the current Iread1 read through the resistance of the selected cell 420 memory with reduced effects due to leakage currents in the other memory cells connected to bit bus 412. Thus, the data values specified by the different levels of voltage reading due to the magnetoresistive effects in the selected cell in the memory 420 may vary, "noise"caused by leakage current.

In a particular embodiment, the device 430 comparison voltage includes a power reading (perception) voltage (VSA)made with the possibility to compare the voltage Vread read in bit bus 412 with reference voltage Vref 432 and to generate an output signal 434 on the basis of comparison. For example, when Vread<Vref, the output signal 434 may be a logical value "0", and when Vread>= Vref, the output signal 434 may be a logical "1"value.

In a particular embodiment, the system 400 may be included in one or more other components or devices. For example, the system 400 may be part of a random access memory (RAM). In the illustrative embodiment, each MTJ device, such as a typical MTJ device 422 may be located is prohibited in the bit cell magnetoresistive memory with random access (STT-RAM), and the amplifier of the read voltage can connect with one or more of the bit cell.

Referring to figure 5, is shown an illustration of stocks readout for the voltage reading data associated with the read storage device for magnetic tunnel junctions (MTJ), generally denoted 500. Level 502 of the reference voltage (Vref) is illustrated as a lower level 504 voltage reading the value "1" (Vread1) and higher than the level 506 voltage reading the value "0" (Vread0) on the vertical axis. The stock 512 reading of "0" indicates the difference between the level 502 of the reference voltage and the level 506 voltage reading the value "0". Stock 510 read "1" illustrates the difference between the level 504 voltage reading values "1" and level 502 of the reference voltage.

In the illustrative embodiment, the level 502 of the reference voltage may correspond to a reference signal Vref 432, and the levels 504 and 506 voltage reading may correspond to the respective values of voltage reading due to Iread1 through the resistance of the cell 420 memory when the data value "0" or "1" is read in the cell 420 memory system 400 in figure 4, in the absence of leakage current from the other memory cells. Each of the stocks 510 and 512 reading can provide tolerance for noise associated with the read operation, so that the maximum is s ' acceptable level of random noise is the lesser of the stock 510 and 512 are read. Thus, tolerance to random noise increases when stocks 510 and 512 read approximately equal.

However, the leakage current generated through the unselected memory devices connected to the line reading data, removes the current reading applied to the line data read from the selected memory cell, shifting the voltage level of the read values "1" and the voltage level of the read value "0" to the lagged levels 522 and 524, respectively. When the level 502 of the reference voltage does not move, a new supply 526 read "1" is reduced, and a new supply 528 shift for reading "0" is increased compared with the previous inventory 510 and 512, respectively. The total tolerance for noise, therefore, decreases as the absolute value of the noise that exceeds the lesser of the two new stocks 526 and 528 shift for reading, can lead to erroneous results.

The leakage current generated through the unselected memory devices, may be reduced by application of negative voltage to the tires of words connected with the unselected devices. The negative voltage may be selected to return the stocks read almost equal to the values 510 and 512. Thus, the dimensions of the elements of the matrix memory can be reduced, additional devices we use the change to the tires of reading data, working voltage can be reduced, or any combination of the above to be performed with reduced negative effects.

Referring to Fig.6, illustrated by concrete variant of the method of reading data from the matrix memory comprising a device for magnetic tunnel junctions (MTJ). At step 602, the signal read is supplied to the bit bus connected to the matrix memory that includes multiple memory cells. Each of the multiple memory cells includes a MTJ device. In a specific embodiment, each of the MTJ device includes a free layer, a fixed layer and the tunnel junction, so that the data value may be represented by the orientation of the magnetic field in the free layer relative to the magnetic field in the fixed layer. In a particular embodiment, the signal readout includes a voltage readout, and data value can be read by comparing the current in the MTJ device with a reference current, as illustrated in Fig.2-3. In another embodiment, the signal reading includes the current reading, and the data value can be read by comparing the voltage of the MTJ device with a reference voltage, as illustrated in figure 4-5.

Proceeding to step 604, a positive voltage is applied to the selected bus words connected with the selected memory cell matrix memory. Proceeding to step 606, a negative voltage is applied to unselected buses words, connected to the matrix memory. In a specific embodiment, the positive voltage and negative voltage are determined by logic bus words, such as logic circuitry 110 bus words, illustrated in figure 1, logic diagram 240 control, illustrated in figure 2, or logic circuit 440 control, illustrated in figure 4. In a particular embodiment, the application of the negative voltage increases the stock of reading the selected memory cell by reducing the leakage current of the memory cells connected to unselected dictionary tires.

Proceeding to step 608, in a particular embodiment, a negative voltage is applied to each tire of the words during the waiting state. The total power consumption may be reduced due to the reduced leakage current in the matrix memory during the waiting state, when a negative voltage is applied to each tire of the words.

7 is a block diagram illustrative of a variant of implementation of the device 700 of communication, such as wireless communication device that includes the memory device with logic 732 read OTP is negative voltage, which is connected with the processor, such as processor 710 digital signal processor (DSP). In the specific example, the memory device with logic 732 read a negative voltage includes a matrix of memory cells in magnetic tunnel junctions (MTJ) and a logic circuit bus words connected with several dictionary tires and executed with the opportunity to apply the negative voltage to the tires of words unselected MTJ cells during a read operation, as described relative to figure 1-6. In a particular embodiment, the memory device with logic 732 read a negative voltage includes a magnetoresistive memory device with random access (STT-RAM).

Fig.7 also shows the controller 726 display, which is connected to the processor 710 digital signals and display 728. Coder/decoder (codec) 734 may also communicate with the processor 710 digital signals. Speaker 736 and the microphone 738 can connect to the codec 734.

7 also indicates that a wireless controller 740 can communicate with a wireless antenna 742 and to respond to processor 710 digital signals. In a particular embodiment, the device 730 input and 744 source of power connected with the system 722 in the crystal. In addition, in a particular embodiment, as proell is reported in Fig.7, display 728, the device 730 input, speaker 736, the microphone 738, wireless antenna 742 and 744 source of power external to the system 722 on the chip. However, each of them can connect to the system component 722 on the chip, such as an interface or a controller.

Specialists in the art will additionally must take into account that the various illustrative logical blocks, configurations, modules, circuits, and steps of the algorithm described in connection with the disclosures provided in this document variants of implementation may be implemented as electronic hardware, computer software, or combinations of the above. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps described above, in General, on the basis of their functionality. Implemented this functionality as hardware or software depends upon the particular application and design constraints imposed on the system as a whole. Qualified professionals can implement the described functionality in varying ways for each particular application, but such solutions should not be interpreted is as being a departure from the scope of the present disclosure.

The stages of a method or algorithm described in connection with the disclosures provided in this document variants of implementation, can be implemented directly in hardware, in a software module, executable by a processor, or combinations thereof. A software module may be posted permanently in memory type RAM, flash memory, memory type ROM memory PROM, memory, EPROM, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of media data storage known in the art. A typical storage medium connected to the processor so that the processor can read information from and write information to the data carrier. In an alternative embodiment, the media data may be embedded in the processor. The processor and the storage medium can be placed in the ASIC. ASIC may be posted permanently in the computing device or the user terminal. In the alternative, the processor and the storage medium can be placed as discrete components in the computing device or the user terminal.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosed variants implement the Oia. Various modifications to these embodiments, the implementation should be obvious to a person skilled in the art, as described in this document, the General principles can be applied to other variants of implementation without departure from the essence and scope of the disclosure. Thus, the present disclosure entity has no intention to be limited shown in this document variant implementation, and must satisfy the widest possible extent consistent with the principles and novel traits defined by the attached claims.

1. The method of reading data from the matrix memory comprising a device for magnetic tunnel junctions (MTJ), the method includes the steps are:
- put signal is read to the bit bus connected to the matrix memory that includes multiple memory cells, each of the multiple memory cells contains a device for magnetic tunnel junctions (MTJ);
- apply a positive voltage to a selected bus of words connected with the selected memory cell matrix memory; and
- apply a negative voltage to unselected buses words, connected to the matrix memory, and apply the negative voltage to each tire of the words during the waiting state.

2. The method according to claim 1, in to the or each MTJ device includes a free layer, fixed layer and the tunnel junction.

3. The method according to claim 1, in which the application of a negative voltage to unselected buses words increases the stock of reading the selected memory cell.

4. The method according to claim 3, wherein the application of a negative voltage to unselected buses words increases the stock of reading the selected memory cell by reducing the leakage current of the memory cells connected to unselected tyres words.

5. The method according to claim 1, wherein the signal reading includes the current read or voltage reading.

6. A storage device containing:
a matrix of memory cells, each of the memory cells in the matrix of memory cells contains a device for magnetic tunnel junctions (MTJ);
- the set of bit tire, connected to the matrix of memory cells;
many tyres words connected with a matrix of memory cells;
- logic bit bus connected to the set of bit tire and made with the possibility to signal read one of the many bit of the tire, connected with the selected memory cell matrix of memory cells; and
- logic bus words connected with many tyres words and configured to selectively apply a positive voltage to a selected bus of words from a set of tyres words, and the selected tyre words connected with the selected acaca the memory, and if this logic bus words applies a negative voltage to unselected buses words, connected to the matrix memory, and unselected bus words include each of the tires of words, in addition to the selected bus words and logic bus words applies the negative voltage to each of a large number of tyres words during the waiting state.

7. A storage device containing:
- logic bus words connected with many tyres words and configured to selectively apply a positive voltage to a selected bus of words connected with the selected memory cell containing a device for magnetic tunnel junctions (MTJ), and applying a negative voltage to unselected buses words, and the negative voltage is applied to each set of tyres words during the waiting state.

8. The storage device according to claim 7, further containing a source of negative voltage, is configured to apply a negative voltage to unselected buses words.

9. The memory device of claim 8, wherein the logical circuit bus words selectively connects the source of negative voltage to unselected tyres words.

10. The memory device of claim 8, further containing a matrix of memory cells, being the m each memory cell in the matrix of memory cells contains the MTJ device.

11. The storage device according to claim 7, further comprising:
a matrix of memory cells, each memory cell in the matrix of memory cells contains the MTJ device, the set of tyres words are connected with the matrix of memory cells;
- the set of bit tire, connected to the matrix of memory cells; and
- layout logic bit bus connected to the set of bit tire and made with the possibility to signal read one of the many bit of the tire, connected with the selected memory cell matrix of memory cells.

12. The storage device according to claim 11, in which unselected bus words include at least one from a set of tyres words, in addition to the selected bus words.

13. The storage device 12, in which each MTJ device includes a free layer, a fixed layer and the tunnel junction.

14. The storage device according to claim 7, in which the application of a negative voltage to unselected buses words increases the stock of reading the selected memory cell.

15. The storage device according to claim 11, in which the signal reading includes the current read or voltage reading.

16. The storage device according to claim 7, in which the negative voltage is applied to unselected buses words, is sufficient to reduce the leakage current of the unselected memory cells

17. The storage device according to claim 7, in which a negative voltage is applied to unselected buses words, but not applied to the selected bus words during read operations.

18. The storage device according to claim 7, in which the MTJ device is located within a bit cell device memory transfer time back (STT-RAM).

19. A storage device for p, optionally containing an amplifier of the read current is connected to the bit cell.

20. The storage device according to claim 7, in which the negative voltage is greater -0,5 Century

21. The storage device according to claim 20, in which a negative voltage of approximately -0,2 Century

22. A storage device containing:
- a means to signal the read bit bus connected to the matrix memory that includes multiple memory cells, each of the multiple memory cells contains a device for magnetic tunnel junctions (MTJ);
- a means for the application of a positive voltage to a selected bus of words connected with the selected memory cell matrix memory; and
- a means for the application of a negative voltage of at least one unselected bus words connected with the matrix memory; and
means for application of a negative voltage for each bus of the words attached to the matrix memory with the situation of waiting.

23. The storage device according to item 22, further containing a source of negative voltage connected to the means for application of a negative voltage.

24. A wireless device, comprising:
processor and
- storage device, coupled to the processor, and a storage device includes a logic circuit bus words connected with many tyres words and configured to selectively apply a positive voltage to a selected bus of words connected with the selected memory cell containing a device for magnetic tunnel junctions (MTJ), and applying a negative voltage to unselected buses words, and the negative voltage is applied to each set of tyres words during the waiting state.

25. A wireless device according to paragraph 24, in which the storage device contains the device memory transfer time back (STT-RAM).



 

Same patents:

FIELD: electricity.

SUBSTANCE: electromechanical device comprises coaxially arranged inductor and movable electroconducting anchor disc, impact disc and striker, the inductor and the electroconducting anchor disc are installed inside a coaxial ferromagnetic core made in the form of a sleeve closed with a cover, in which there is a row of axial guide holes, inside which there are guide rods placed, connected by one end with the impact disc, and with the other end with flat ledges, which interact with the electroconducting anchor disc, a sharpened part of the striker is directed towards the digital media of information.

EFFECT: increased efficiency of a device for protection of information placed on digital media in case there is a chance of its leakage, reduced fields of leakage into environment, reduced dimensions and increased reliability of the device.

9 cl, 12 dwg

FIELD: information technology.

SUBSTANCE: method of determining values of current and spin rotary moment in magnetic multilayer structures consisting of alternating ferromagnetic and nonmagnetic layers, at different applied voltages and while varying mutual orientation of magnetisation of the layers, wherein the disclosed method involves the following steps: determining parameters of the multilayer system which is to be used as a magnetic memory cell, particularly, the number of layers in the multilayer system is calculated, characteristics of the layers are determined, as well as lattice parameters, the number of layers in the multilayers, angles of magnetisation on the OX and OY axes; boundary s-s and d-d transfer integrals are calculated for each layer; based on the obtained values, boundary transfer integrals and the position of centres s and d of electrons of different spins of conducting zones of all layers are calculated; the rotary moment is calculated as a function of the applied voltage.

EFFECT: method enables to design non-volatile magnetic memory cells with predetermined parameters.

2 cl, 3 dwg, 3 tbl

FIELD: information technology.

SUBSTANCE: method of refreshing a dynamic random-access memory (DRAM) array in form of independently refreshable memory units, comprising: associating an indicator with each independently refreshable memory unit; upon writing data to an independently refreshable memory unit, setting the associated indicator to reflect valid data; increasing delay between refreshing operations in proportion to the zero number of suppressed refreshing cycles, wherein a refreshing cycle is suppressed if the associated indicator reflects invalid data, so that only all independently refreshable memory units, which contain valid data, can be refreshed with maximum period of refreshing; and refreshing with said maximum period of refreshing only the independently refreshable memory units whose associated indicator reflects valid data stored therein.

EFFECT: reducing DRAM power consumption.

26 cl, 6 dwg

FIELD: information technology.

SUBSTANCE: method of refreshing a dynamic random-access memory (DRAM) array in form of independently refreshable memory units, comprising: associating an indicator with each independently refreshable memory unit; upon writing data to an independently refreshable memory unit, setting the associated indicator to reflect valid data; increasing delay between refreshing operations in proportion to the zero number of suppressed refreshing cycles, wherein a refreshing cycle is suppressed if the associated indicator reflects invalid data, so that only all independently refreshable memory units, which contain valid data, can be refreshed with maximum period of refreshing; and refreshing with said maximum period of refreshing only the independently refreshable memory units whose associated indicator reflects valid data stored therein.

EFFECT: reducing DRAM power consumption.

26 cl, 6 dwg

FIELD: information technology.

SUBSTANCE: systems, circuits and methods for determining read and write voltages for a given word line transistor in spin transfer torque magnetoresistive random access memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that read operations occur in the linear region of the word line transistor.

EFFECT: short response time.

20 cl, 15 dwg

FIELD: physics.

SUBSTANCE: invention discloses systems, circuits and methods for a programme-controlled circuit which employs spin-torque transfer magnetic RAM (STT-MRAM) technology. Memory elements on a magnetic tunnel junction can be formed into input matrices and output matrices. The input matrices and output matrices can be merged to form composite matrices which enable to realise logic functions.

EFFECT: broader functionalities.

20 cl, 10 dwg, 3 tbl

FIELD: information technologies.

SUBSTANCE: systems, circuits and methods are disclosed to control word line voltage in a word line transistor in a magnetoresistive RAM with transfer of spin torque (STT-MRAM). The first voltage may be sent to a word line transistor for recording operations. The second voltage, which is less than the first voltage, may be sent to a word line transistor during reading operations.

EFFECT: control of WL transistor signal level for reading and recording operations.

20 cl, 12 dwg

FIELD: electricity.

SUBSTANCE: external portable single-type memory units in quantity of more than one are systematically arranged in container or cassette or drum and provide reading and/or record of multimedia information content with reading or reading-recording or recording device of electronic device to the chosen number of external portable single-type memory units with possibility of movement to the place of external portable single-type memory unit removed from container or cassette or drum of external portable single-type memory unit following it.

EFFECT: copying and printing of multimedia information content by electronic device.

8 cl

FIELD: physics.

SUBSTANCE: multilayer magnetoresistive composite nanostructure has several sets of alternating layers of magnetically soft and magnetically hard nanoclusters insulated at the top and bottom by a continuous dielectric layer of antiferromagnetic material. One set has an antiferromagnetic layer, a layer of magnetically soft nanoclusters, an antiferromagnetic layer, a layer of magnetically hard nanoclusters, and a antiferromagnetic layer, where thickness of the nanocluster film is equal to 0.8-2.5 nm. The number of said sets of layers is between 2 and 5.

EFFECT: design of a magnetoresistive nanostructure whose production technology guarantees required parametres, giant magnetoresistive effect in the material with working capacity under high temperature conditions, and high reproducibility of parametres under batch production conditions.

5 cl, 2 dwg

FIELD: information technologies.

SUBSTANCE: pseudo-dual-port memory contains the first port, the second port and array of memory cells with six transistors. The first call to memory is initiated by means of anterior front of the first synchronising signal (ACLK) received along the first port. The second call to memory is initiated in response to anterior front of the second synchronising signal (BCLK) received along the second port. If anterior front of the second synchronising signal occurs in the first period of time, than the second call to memory is initiated immediately after completion of the first call to memory by pseudo-dual-port method. If anterior front of the second synchronising signal occurs later in the second period of time, than the second call to memory is delayed till the time after the second anterior front of the first synchronising signal. Duration of the first and second calls to memory does not depend on beats of synchronising signals.

EFFECT: possibility to control ordering of two operations with memory having two separate ports, every of which has its own input synchronising pulse.

37 cl, 16 dwg

Magnetic materials // 2244971

FIELD: magnetic materials whose axial symmetry is used for imparting magnetic properties to materials.

SUBSTANCE: memory element has nanomagnetic materials whose axial symmetry is chosen to obtain high residual magnetic induction and respective coercive force. This enlarges body of information stored on information media.

EFFECT: enhanced speed of nonvolatile memory integrated circuits for computers of low power requirement.

4 cl, 8 dwg

FIELD: recording devices.

SUBSTANCE: device has electrically polarized dielectric material, being in layer placed between first and second addressing sets with parallel placement of electrodes within limits of each set, controlling buses and data buses, reading means and means for connecting each data bus to associated reading means. Method describes operation of said device. Device for three-dimensional data storage has multiple stacking layers, each of which has one of said energy-independent recording devices.

EFFECT: possible localization of errors, prevention of interferences in non-addressed cells.

3 cl, 11 dwg

FIELD: electronics.

SUBSTANCE: device for providing possible addressing in device, containing one or more volumetric element, in form of memory cells, display cells, diodes, transistors and/or switching/modulating elements and forming together with said device a portion of two-dimensional or three-dimensional matrix being a component of said device, contains three sets of electric-conductive lines or ribbon electrodes, forming an additional portion of said matrix. Device for storing and/or processing data or receipt and/or processing, and/or displaying of signals contains said means and more than one matrix, while said matrices are made in form of stack, accurately placed on substrate, and device forms a volumetric structure dependently on functional properties of each matrix in a stack.

EFFECT: broader functional capabilities.

2 cl, 23 dwg

FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

EFFECT: higher reliability of operation.

5 cl, 71 dwg

FIELD: memory devices.

SUBSTANCE: first device for comparing phases has signal generator for feeding two or more reading signals with given phases to memory cell, phase-sensitive detector, support signal source, discrimination/logic contour. Second device for comparing phases has signal generator for feeding first periodical signal, applied to second periodically reading signal of lesser frequency, phase-sensitive detector/discriminator. Method describes operation of said devices.

EFFECT: higher reliability.

3 cl, 15 dwg

Memory cell // 2256957

FIELD: computer science.

SUBSTANCE: memory cell, containing three-layer structure, including two electrodes, between which a functional zone is located, as electrodes metal and/or semiconductor and/or conducting polymer and/or conducting and optically transparent oxide or sulfide are used, and functional zone is made of organic, metal-organic and non-organic materials with different types of active elements built in molecular and/or crystalline structure, and also their combinations with each other and/or clusters on their basis, which change their condition or position under effect from outside electrical field and/or light radiation.

EFFECT: higher efficiency, broader functional capabilities, higher manufacturability.

25 cl, 24 dwg

FIELD: electric engineering.

SUBSTANCE: device has ferroelectric memory cell in form of thin ferroelectric polymer film, two electrodes, while at least one of said electrodes has at least one contact layer, which has conductive polymer in contact with memory cell, and if necessary has second layer in from of metallic film in contact with conductive polymer. Method for manufacturing ferroelectric memory contour includes operations for applying on substrate of first contact layer in from of thin film of conductive polymer and applying thin ferroelectric polymer film on first contact layer and second contact layer on thin ferroelectric polymer film.

EFFECT: increased polarization level of ferro-electric memory cell and decreased field strength.

2 cl, 12 dwg, 3 ex

FIELD: data carriers.

SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

FIELD: digital data processing.

SUBSTANCE: device in form of semiconductor memory device has control block with control elements and memory cells, each of which is made with possible connection to system of buses for connection to central processor and has an in-built microprocessor, including registers, made with possible storage of signs of start of data flow name and its end, information about state and mode of in-built microprocessor. Method describes process of data processing in aforementioned recording device.

EFFECT: higher speed of operation.

6 cl, 7 dwg

FIELD: technology for recording data, linked with other data.

SUBSTANCE: data production device has module for assigning numeric value, meant for assigning from number of multiple numeric values, stored on data carrier, of numeric value, appropriate for data file, subject for extraction, while numeric value is additional basic n value, where n - integer value higher than one. Device also has module for forming path name, meant for forming name by insertion of symbol, appropriate for numeric value, into each preset position in given formed symbols string, and receiving module, meant for extraction of data file, if in data carrier additional file is present with path name, formed by path name forming module.

EFFECT: decreased data-occupied space in memory.

4 cl, 12 dwg

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