Semiconductor instrument

FIELD: electricity.

SUBSTANCE: in semiconductor instrument containing sink, source consisting of transistor cells and peripheral p-n junction, which are located under gate electrode, as well as of metal electrode of source, which is located above gate electrode, polysilicon gate electrode insulated from source areas with dielectric, which contains in middle part the matrix of transistor cells and peripheral end part overlapping above the dielectric the source peripheral p-n junction; end part of polysilicon gate electrode, which overlaps above the dielectric the source peripheral p-n junction, is topologically separated from end cell of matrix of transistor cells and not covered with source metal coating.

EFFECT: reducing the resistance of power double-diffused MOS transistors in open state, without increase in the size of crystal and deterioration of other parameters.

2 cl, 3 dwg

 

The invention relates to microelectronics, and in particular to the field of power semiconductor devices, in particular power drop-transistors.

There are many structures of power, DMAP transistors that differ from the bipolar transistor high speed switching, high working voltages and currents, linear characteristics and high temperatures (Log Components and technology, No. 4, 2007, p.100-104).

One of the main problems to be solved when designing competitive power DMAP transistors is the task of reducing the resistance in the open status - RCwithout increasing the dimensions of the crystal and the deterioration of other parameters.

The main structure, widely used before the invention shown in figure 1 - the design of the power P (or N) channel drop transistor containing local oxide 1, the gate insulator 2, a polysilicon electrode, the shutter 3, the interlayer dielectric 4, stokowy metal electrode 5, the P+ (N+) region source 6, N+/N- (or P+/P-) region of the source/channel 7/8, P- (N-) region of the drain 9, R+ (N+) drain region 10, region metallization flow 11, Land- length stokovoj region from the metallization of the source to the channel.

Since RCdirectly proportional to the length stokovoj region-With, to reduce the latter was chosen to t geologicheskiy process with lateral isolation valves - figure 2, which depicts the design of the power drop transistor with a lateral insulated gate containing local oxide 1, the gate insulator 2, a polysilicon electrode-gate 3, stokowy metal electrode 5, the P+ (N+) region source 6, N+/N- (or P+/P-) region of the source/channel 7/8, P- (N-) region of the drain 9, R+ (N+) drain region 10, the area of the drain metallization 11, Land- length stokovoj region from the metallization of the source to the channel interlayer insulation shutter 12, the side insulation 13 and the polysilicon electrode, the shutter 3, the region 14 protravlivanija interlayer dielectric on the peripheral edges of polysilicon, including extreme cell, the reasons which are explained later.

For the process after gate oxidation, deposition, polysilicon, doped polysilicon, deposition of interlayer dielectric - ST - SiO2was done photoetching is "Gates" from chemical parkovanim anisotropic etching CT-SiO2and polysilicon (with the ratio of the velocities of the vertical and horizontal components as ~4/1) to the gate dielectric, resulting in the created gate electrode from the upper interlayer insulation, but the side surfaces of the polysilicon gates remained bare.

The next step was the creation of lateral isolation, which legs after the Finance relevant impurities monogrammatic areas of cells, formed by holes in the polysilicon gate on the entire surface of the plates was applied ARTICLE-FSS, and immediately travelpulse chemical brightly pronounced anisotropic way (with the ratio of the velocities of the vertical and horizontal components as ~4/1) to the gate dielectric in the cell. In this ARTICLE-FSS on the sidewalls of polysilicon remained stravenym, forming a lateral insulation 13, paddles. But the results of such method of creating a lateral insulation 13 gates were reproducible from batch to batch. In the analysis of marriage was established that the reason for marriage is the opening of the interlayer dielectric on the side closest to the periphery, faces extreme cells (figure 2), which led to a short circuit istokpoga electrode 5 (Al source) with the bolt polyctenium.

It was also found that if the gate polysilicon is both electrode overlapping the peripheral istokpoga P/N junction having a width of polysilicon, more than twice the distance on the polysilicon between cells, when plasma chemical faintly pronounced anisotropic etching of SiO2(when the speed ratio side protravlivanija relative to the vertical etching rates ~1/4). when creating a lateral insulation gate polysilicon, polikremnii overlapping lateral isolation n is travelways before opening the insulated polysilicon on the edges of the extended overlap area (figure 2). At this extreme edge of the shutter in the last cell was closed on stockbuy metallization, which led to marriage.

An assumption was made that such a feature boundary of polysilicon is connected with flow of ions in the plasma-chemical etching (PCT) of interlayer dielectric. The fact that topologically-value polysilicon forming the overlapping peripheral P/N junction and the outermost part of the last cell that has a much greater width of the peripheral polysilicon than polysilicon between the cells inside the matrix and this boundary the large surface of the polysilicon, charging by plasma of the same charge repel the plasma to the edge under a greater angle to the vertical than between cells, which leads to lateral leakage side interlayer dielectric - phosphorothiolate glass (ST-FSS) only at the regional wide-polikremnii and closing of the sealing edge of polysilicon with stokovoj metallization in the last cell of the matrix.

Due to the high percentage of defects on the above technology, DMAP transistors in the claimed invention was given the task to increase the yield of finished products - dmop transistors with reduced resistance drop transistors in an open state while minimizing the containers and without compromising other parameters.

The technical result to thetsa fact, that is a semiconductor device containing a drain, the source, consisting of transhistorical and the peripheral p-n junction beneath the electrode-gate, and from the metal of the source electrode located above the electrode-gate, the polysilicon electrode-gate, insulated from stokovyh areas dielectric containing in the middle part of the matrix of transistor cells and a peripheral edge portion that overlaps over the dielectric stokowy peripheral p-n junction, characterized in that the edge portion of the polysilicon electrode-gate overlap over the dielectric stokowy peripheral p-n junction, topologically separated from the last cell of the matrix of transistor cells and not overlap stokovoj metallization, and the edge portion of the polysilicon electrode-gate overlap over the dielectric stokowy peripheral p-n junction, topologically separated from the last cell of the matrix of transistor cells at a distance equal to 0.6 to 1.4 distances on the polysilicon between the transistor cells. This edge effect of protravlivanija side insulation, which is separated on the peripheral part becomes safe, as above it is not istokpoga electrode 3, which depicts the design of the power drop transistor with a lateral isolation valves, rupture prefering the polysilicon and safe potroom interlayer dielectric, containing local oxide 1, the gate insulator 2, a polysilicon electrode-gate 3, stokowy metal electrode 5, the P+ (N+) region source 6, N+/N-(or P+/P-) region of the source/channel 7/8, P- (N-) region of the drain 9, R+ (N+) drain region 10, the area of the drain metallization 11, Land- length stokovoj region from the metallization of the source to the channel interlayer insulation shutter 12, the side insulation 13 and the polysilicon electrode, the shutter 3, the region 14 protravlivanija interlayer dielectric on the peripheral edges of polysilicon region 15 break peripheral polysilicon.

Figure 3 shows the region 15 break peripheral polysilicon, resulting in region 14 protravlivanija interlayer dielectric on the peripheral edges of the polysilicon becomes safe and does not affect the repeatability of the manufacturing DMAP transistors from batch to batch.

In accordance with the claimed invention were developed 4 types of the p-channel transistor in die form:

- CPA-5 U=-100 B, R TCI=0,055 Ohm;

- KPB-5 U=-100 B, R TCI=to 0.060 Ohms;

- KPV-5 U=-80 B, R TCI=0,050 Ohm;

- CPG-5 U=-80 B, R TCI=0,055 Ohm

and 4 of the type p-channel transistors, designed to be placed in plastic enclosures CT-28-2 (220):

- CPA with U=-100 B, R TCI=0,0550 m, Ic=-40;

- CPB with U=-100 B, R TCI=0,0600 m, Ic=-40;

- CPU with U=-80 B, R TCI=0,0500 m, Ic=-40 And

- CPG with U=-80 B, R TCI=0,0550 m, Ic=-40 A.

By its parameters developed p-channel power DMAP transistors are at par with the best foreign analogues and exceed all domestic.

Were made three experimental batches of DMAP transistors, in which the marriage caused by the closure of the origins with the periphery of the gates, was absent. Thus, the task of the invention was achieved.

1. Semiconductor device containing a drain, the source consisting of transistor cells and the peripheral p-n junction beneath the electrode-gate, and from the metal of the source electrode located above the electrode-gate, the polysilicon electrode-gate, insulated from stokovyh areas dielectric containing in the middle part of the matrix of transistor cells and a peripheral edge portion that overlaps over the dielectric stokowy peripheral p-n junction, wherein the edge portion of the polysilicon electrode-gate overlap over the dielectric stokowy peripheral p-n junction, topologically separated from the last cell of the matrix of transistor cells and not overlap stokovoj plating.

2. A semiconductor device according to claim 1, characterized in that the edge portion of the polysilicon electrode-gate overlap over the dielectric stokowy peripheral p-n go to the d, topologically separated from the last cell of the matrix of transistor cells at a distance equal to 0.6 to 1.4 distances on the polysilicon between the transistor cells.



 

Same patents:

Multichannel reader // 2282269

FIELD: optical data processing systems.

SUBSTANCE: proposed multichannel reader built on semiconductor substrate has N input units, multiple-output switching unit, common read-out bus, write bus, pre-processor signal processing unit incorporating comparator, arithmetic-logic device, and memory unit; one of two comparator inputs is designed to apply digital-code signal thereto and is connected to common read-out bus; other comparator input is designed to feed reference signal; comparator output is connected to input of arithmetic-logic device whose output is connected to input of memory unit whose output is coupled with write bus; each input unit is made in the form of amplifier that has input, output, and control input, as well as two MIS transistors; first MIS transistor gate is connected to output of respective cell of multiple-output switching unit and gate, to common read-out bus; second MIS transistor gate is connected to output of next cell of multiple-output switching unit and gate, to write bus; each input unit is provided in addition with K-capacity analog-to-digital converter and L-capacity digital-to-analog converter; first MIS transistor source is connected to output of analog-to-digital converter whose input is connected to amplifier output; second MIS transistor source is connected to input of digital-to-analog converter whose output is connected to amplifier control input; common read-out bus is assembled of K buses, K being equal to capacity of analog-to-digital converter and to number of first MIS transistors connected through their gates to respective outputs of multiple-output switching unit, through drains, to respective buses of common read-out buses, and through sources, to respective inputs of analog-to-digital converters; write bus is assembled of L buses, L being equal to digital-to-analog converter capacity and to number of second MIS transistors connected through drains to respective buses forming write bus, through gates, to output of next cell of multiple-output switching unity, and through sources, to respective inputs of digital-to-analog converter.

EFFECT: extended dynamic range, enhanced speed, enlarged functional capabilities.

1 cl, 1 dwg

The invention relates to a structure oriented on the radio, in particular, to the structure of the CMOS circuits for digital radio transceiver

Multichannel reader // 2282269

FIELD: optical data processing systems.

SUBSTANCE: proposed multichannel reader built on semiconductor substrate has N input units, multiple-output switching unit, common read-out bus, write bus, pre-processor signal processing unit incorporating comparator, arithmetic-logic device, and memory unit; one of two comparator inputs is designed to apply digital-code signal thereto and is connected to common read-out bus; other comparator input is designed to feed reference signal; comparator output is connected to input of arithmetic-logic device whose output is connected to input of memory unit whose output is coupled with write bus; each input unit is made in the form of amplifier that has input, output, and control input, as well as two MIS transistors; first MIS transistor gate is connected to output of respective cell of multiple-output switching unit and gate, to common read-out bus; second MIS transistor gate is connected to output of next cell of multiple-output switching unit and gate, to write bus; each input unit is provided in addition with K-capacity analog-to-digital converter and L-capacity digital-to-analog converter; first MIS transistor source is connected to output of analog-to-digital converter whose input is connected to amplifier output; second MIS transistor source is connected to input of digital-to-analog converter whose output is connected to amplifier control input; common read-out bus is assembled of K buses, K being equal to capacity of analog-to-digital converter and to number of first MIS transistors connected through their gates to respective outputs of multiple-output switching unit, through drains, to respective buses of common read-out buses, and through sources, to respective inputs of analog-to-digital converters; write bus is assembled of L buses, L being equal to digital-to-analog converter capacity and to number of second MIS transistors connected through drains to respective buses forming write bus, through gates, to output of next cell of multiple-output switching unity, and through sources, to respective inputs of digital-to-analog converter.

EFFECT: extended dynamic range, enhanced speed, enlarged functional capabilities.

1 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: in semiconductor instrument containing sink, source consisting of transistor cells and peripheral p-n junction, which are located under gate electrode, as well as of metal electrode of source, which is located above gate electrode, polysilicon gate electrode insulated from source areas with dielectric, which contains in middle part the matrix of transistor cells and peripheral end part overlapping above the dielectric the source peripheral p-n junction; end part of polysilicon gate electrode, which overlaps above the dielectric the source peripheral p-n junction, is topologically separated from end cell of matrix of transistor cells and not covered with source metal coating.

EFFECT: reducing the resistance of power double-diffused MOS transistors in open state, without increase in the size of crystal and deterioration of other parameters.

2 cl, 3 dwg

FIELD: electricity.

SUBSTANCE: thin-film transistor TFT includes a gate, a first insulating layer located above the gate, a second insulating layer located above the first insulating layer, a semiconductor layer, a source and a drain, located between the first insulating layer and the second insulating layer, an ohmic contact layer located between the semiconductor layer, the source and the drain, the ohmic contact layer including an opening passing through the ohmic contact layer by means of a gap between the source and the drain in order to open the semiconductor layer, and the second insulating layer is connected to the semiconductor layer through this opening, and a conductive layer located above the second insulating layer. The conductive layer and the gate are electrically connected to each other, so that when the TFT is in the on-state, the switching current generated in the conductive channels of the semiconductor layer is increased. When the TFT is in the off-state, the tripping current generated in the conductive channels is reduced.

EFFECT: the ratio of the making current to the tripping current is increased.

15 cl, 6 dwg

Up!