Method of manufacturing of inverter and inverter

FIELD: electricity.

SUBSTANCE: method of manufacturing of an enhancement/depletion (E/D) inverter having a number of thin-film transistors on the same substrate with channel layers consisting of an oxide semiconductor containing at least one element selected from In, Ga and Zn, involves the stages to form a first transistor and a second transistor; a channel layer thickness of the first and second transistors is mutually different; at least one of the channel layers of the first and second transistors are thermally treated.

EFFECT: expansion of the facilities allowing to manufacturer an inverter with oxide semiconductor thin-film transistors of various threshold voltages, simplified method of manufacturing of the inverter with such characteristics, cost reduction.

13 cl, 18 dwg

 

The technical FIELD

The present invention relates to an inverter, which consists of a thin film transistor containing an oxide semiconductor layer as a channel layer. In addition, the present invention relates to integrated circuit that contains the corresponding inverter.

The LEVEL of TECHNOLOGY

Connection Board, thin-film transistor (TFT), in which transistors TFT are placed in an array on the substrate, constitute part of the basis for various kinds of liquid crystal displays, active matrix, such as a liquid crystal display, the display on the organic light emitting diode (OLED) and the like In the liquid crystal display with active matrix transistor TFT controls the electro-optical device corresponding to each pixel to display the desired information. As transistor TFT for this purpose is considered the transistor TFT on the basis of low-temperature polycrystalline silicon (LTPS), the transistor TFT based on hydrogenated amorphous silicon (a-Si:H), etc.

In addition, the technology for the simultaneous production of transistors TFT, respectively having different functions on the same substrate as the wiring Board. More specifically, in this technology, the transistor TFT (pixel circuit) to control the effect electro-optical device of each pixel and the peripheral circuit, such as the driver gate driver source, etc. consisting of transistors TFT are fabricated simultaneously on the same substrate. In this case, since the function of transistor TFT is different depending on each block schemes, such as the pixel circuit, the peripheral circuit and the like, it is desirable to adjust the threshold voltage of the transistor TFT for each block in the diagram. For example, it should be noted that a large threshold voltage, suitable for a threshold inverting the electro-optical device, preferably in the pixel circuit, and a low threshold voltage, it is desirable to curb energy consumption in the peripheral circuit. At this level of technology published patent application of Japan No. 2005-072461 discloses a method for adjusting the threshold voltages of transistors TFT in accordance with blocks of pixels in the circuits of transistors TFT based on LTPS, manufactured using annealing using an excimer laser (ELA).

The peripheral circuits include digital circuits, such as shift register, etc. it should be noted that in the case of manufacturing digital circuits with transistors TFT, the following four patterns (1)to(4) can be used as a logic element "NOT" (inverter). Structure (1) is an active load structure (2) is an enrichment/enrichment (E/), structure (3) is the enrichment/depletion (E/D), and structure (4) is a complementary metal-oxide semiconductor (CMOS). In the General case, the structure of the E/D or a CMOS structure is often used to reduce layout area and achieve operation at high speed. Incidentally, for the efficient operation of the inverter with the structure of enrichment/depletion is necessary to control the threshold voltage of the transistor TFT in such a way as to make the difference between the threshold voltages of the two transistors TFT constituting the inverter is large enough. On the other hand, as for the inverter with the structure of a CMOS necessary and transistor TFT with a channel of n-type, and the transistor TFT with a channel of p-type, require appropriate processes alloying for each transistor TFT, which leads to a greater number of photolithography processes compared with other structures.

As the potential options effective transistor TFT to be used in place of transistors TFT based on LTPS and a-Si:H have been actively researched and developed transistors TFT (oxide transistors TFT), in which the channel layer are layers of oxide semiconductors. The method of manufacturing an oxide of transistor TFT with the use of thin film received radio frequency magnetron raspy is the group of made of amorphous indium oxide-gallium-zinc (In-Ga-Zn-O; IGZO) as a channel layer is disclosed in the document "Appl. Phys. Lett. 89, 112123 (2006)". Many kinds of oxide semiconductors with high mobility of carriers, such as amorphous IGZO, etc. have a conductivity of n-type (e)but does not acquire the conductivity of p-type (hole) even when the doping, so the CMOS structure can not be used. However, oxide transistor TFT has the following two advantages. So, (1) the mobility of carriers oxide transistor TFT is much higher than the mobility of carriers of the transistor TFT on the basis of a-Si:H. Therefore, the document "IEEE Elec. Dev. Lett., 28, p.273 (2007)" reveals that even if you use the inverter with saturated load mode enrichment/enrichment, which is inconvenient from the point of view of speed, can be achieved working with great speed that exceeds the speed of the inverter transistor TFT on the basis of a-Si:H. moreover, (2) for the channel layer available for deposition by sputtering technique. Thus, because the original glass substrate can be increased, it is possible to expect decrease in the cost of manufacture in accordance with increase in the substrate.

In addition, the following documents are disclosed various methods to control the threshold voltage for oxide transistor TFT. First, the public is of application for U.S. patent number US-2006-0113565 reveals transistor TFT, which includes In, Ga, Zn and O as constituent elements, and uses as a channel layer of a transparent amorphous oxide thin film, the concentration of electronic carriers which is less than 1018cm-3and an integrated circuit that uses the corresponding transistors TFT. In addition, this document mentions the use of transistor TFT operating in the depletion mode (D), but does not mention a specific method of controlling the voltage Vthin the transistor TFT.

Publication of an application for US patent # US-2006-0244107 discloses a method of controlling the voltage Vthin the transistor TFT, which uses zinc oxide (ZnO) as a channel layer, through the introduction of alloying substances in the atmosphere of the deposition of the channel layer.

In addition, the document "BARQUINHA ET AL: "Influence of the semiconductor thickness on the electrical properties of transparent TFTs based on indium zinc oxide" JOURNAL OF NONCRYSTALLINE SOLIDS, NORTH-HOLLAND PHYSICS PUBLISHING. AMSTERDAM, NL, vol. 352, no. 9-20, 15 June 2006 (2006-06-15), pages 1749-1752, XP005482522 ISSN: 0022-3093 figure 3 reveals that the transistor TFT, which uses ZnO as a material of the channel layer, the voltage Vthis regulated by the thickness of the deposited channel layer.

In addition, the document "Journal of Applied physics, 97, p.064505 (2005)" reveals that the transistor TFT, which uses zinc oxide-India (Zn-In-O) as the material of the channel layer, atragene V this regulated by the temperature of thermal treatment.

In any case, all the documents of the set consisting of the publication of the patent by U.S. patent # US-2006-0244107, document, "Solid State Electronics, 352(9-20), p.1749 (2006)" and the document "Journal of Applied physics, 97, p.064505 (2005)", reveal that the characteristics of transistors TFT, respectively fabricated on different substrates under different conditions, differ from each other. However, none of these documents discloses a specific method of manufacturing the same substrate transistors TFT, each of which would have its voltage Vth.

In the method described in published patent application of Japan No. 2005-072461, inexpensive manufacture of digital circuits with transistors TFT is difficult for two reasons.

First, the transistor TFT, disclosed in this document, is the transistor TFT on the basis of LTPS. In other words, as the cost increases due to the increase of the annealing device using excimer laser (ELA), even if it increases the original glass substrate, the advantage of cost of production in accordance with increase of the substrate is small. Secondly, it is impossible to get the inverter is operating in the mode of enrichment/depletion, who works effectively, since the difference between the threshold voltages of transistors TFT obtained in the way described in this document too small. Therefore, the inverter disclosed in this document, has the structure of a CMOS and a photolithography process is complicated in comparison with other structures, whereby the cost is increased.

DISCLOSURE of INVENTIONS

The present invention aims to solve the problems described above. The present invention is characterized by a method of manufacturing the inverter is operating in the mode of enrichment/depletion (E/D), with many thin-film transistors on the same substrate, the channel layers of the above-mentioned transistors are composed of an oxide semiconductor containing at least one element selected from In, Ga and Zn, and the method comprises the steps: forming the first transistor and the second transistor, the thickness of the channel layers of the first and second transistors are different; and applying a heat treatment to at least one of the channel layers of the first and second transistors.

In addition, the present invention is characterized by a method of manufacturing the inverter is operating in the mode of enrichment/depletion (E/D), with many thin-film transistors on the same substrate, the channel layers of the above-mentioned transistors are composed of an oxide semiconductor containing at least one element selected from In, Ga and Zn, and the method comprises the steps: forming the total deposited film, de is appropriate as a channel layer of the first transistor and the channel layer of the second transistor; and performing heat treatment by application of a larger amount of heat to any one of the channel layers of the first transistor and the second transistor.

In addition, the present invention is characterized by the fact that among various oxide semiconductor thin film transistors, which are formed on the same substrate and each of which contains at least one element selected from In, Ga and Zn, the thickness of the channel layers of at least two transistors is mutually different, and the threshold voltage of the two transistors are mutually different.

In accordance with the present invention may be relatively easy to manufacture the oxide semiconductor thin film transistors respectively having different threshold voltages on the same substrate using the characteristics of the oxide semiconductor thin film transistor. For example, the relevant characteristics include such a characteristic that the difference in threshold voltage occurs due to the difference of thickness of the channel layers, and such a characteristic that the difference in threshold voltage caused by a difference of thermal treatment conditions of the channel layers. Even if you are using any one of these two characteristics, it is possible to increase considerably different the th threshold voltage, whereby the inverter is operating in the mode of enrichment/depletion functioning effectively.

Additional distinguishing features of the present invention will become clear on the basis of the following description of illustrative options embodiments with reference to the attached drawings.

BRIEF DESCRIPTION of DRAWINGS

The accompanying drawings, which are included in the description and be part of it, illustrate variations of the embodiment of the invention and together with the description serve to explain the principles of the invention.

Figure 1 - schematic diagram of the inverter is operating in the mode of enrichment/depletion.

Figure 2 - schematic diagram of the inverter with saturated load mode enrichment/enrichment.

Figure 3 - image of a cross-sectional view of the first variant embodiment.

Figure 4 - image of a cross-sectional view of the second variant embodiment.

5 is an image showing the result of evaluation (simulation) effective conditions of manufacture of the inverter is operating in the mode of enrichment/depletion.

6 is an image of the cross-section of the manufactured transistor TFT.

Figa, 7B, 7C, 7D, 7E, 7F, 7G and 7H - image showing the characteristic dependence of Ids-Vgsmanufactured transistor TFT.

Fig - image cross-sections showing the manufacturing process is of invertor, working in the mode of enrichment/depletion in the variant of embodiment 1, variant of embodiment 4 and comparative example 4-1.

Figure 9 is an image showing the output waveform model of a ring oscillator composed of inverters operating in the mode of enrichment/depletion in the variant of embodiment 1.

Figure 10 - image cross-sections showing the manufacturing process of the inverter with saturated load mode enrichment/enrichment, in comparative example 1-1 and comparative example 4-2.

11 is an image showing the output waveform model of a ring oscillator composed of inverter with saturated load mode enrichment/enrichment, in comparative example 1-1.

Fig - image cross-sections showing the manufacturing process of the inverter with saturated load mode enrichment/enrichment, in comparative example 1-2.

Fig - image cross-sections showing the manufacturing process of the inverter is operating in the mode of enrichment/depletion in the variant of embodiment 3.

Fig image showing the output waveform model of a ring oscillator composed of inverters operating in the mode of enrichment/depletion in the variant of embodiment 3.

Fig image showing the output of the second waveform model of the ring oscillator, composed of inverter with saturated load mode enrichment/enrichment, in comparative example 3-1.

Fig image showing the output waveform model of a ring oscillator composed of inverters operating in the mode of enrichment/depletion in the variant of embodiment 4.

Fig image showing the output waveform model of a ring oscillator composed of inverter with saturated load mode enrichment/enrichment, in comparative example 4-1.

Fig image showing the output waveform model of a ring oscillator composed of inverter with saturated load mode enrichment/enrichment, in comparative example 4-2.

The PREFERRED EMBODIMENT of the INVENTION

Now will be described in detail illustrative variants of the embodiment of the present invention with reference to the accompanying drawings.

Figure 1 is a schematic diagram of the inverter is operating in the mode of enrichment/depletion (E/D), which can be manufactured in accordance with the present invention. In the inverter mode of enrichment/depletion is one part of the thin-film transistor (TFT), working in the enrichment mode (mode E), and one part of the transistor TFT operating mode in the e depletion (D). The power source voltage is supplied from the outside as the potential difference between the voltage Vddand ground GND. The source electrode of transistor TFT operating in the depletion mode, and the drain electrode of transistor TFT mode of enrichment, are connected to each other, and the electrode of the transistor TFT operating in the depletion mode, is connected to the source electrode of transistor TFT operating in the depletion mode. The drain electrode of transistor TFT operating in the depletion mode, connected to a point of Vddvoltage power source, and the source electrode of transistor TFT, mode of dressing, connected to ground. The electrode of the transistor TFT, mode of dressing, serves as the entry point, and the drain electrode of transistor TFT, mode of dressing, serves as the exit point.

In principle, the output voltage of the inverter is operating in the mode of enrichment/depletion during the high level of the output signal rises to a voltage equivalent to the voltage of the power source. Therefore, the inverter is operating in the mode of enrichment/depletion has such a distinctive feature that the amplitude of the output voltage is wide and the rise time of the output voltage is fast.

On the other hand, figure 2 shows a schematic diagram of the inverter with saturated load is Oh, working in the mode of enrichment/enrichment, in which the load transistor TFT, and a control transistor TFT is operating in the mode of enrichment. Similarly, the inverter is operating in the mode of enrichment/depletion of the power source voltage is supplied from the outside as the potential difference between the voltage Vdda protective grounding connection.

When comparing these two types of inverters to each other inverter is operating in the mode of enrichment/depletion can manage the load capacity at a higher speed with greater amplitude.

In the transistor TFT, when the voltage Vdsbetween drain and source is much larger than the voltage Vgsbetween the gate and source of transistor TFT operates in a saturation region and the current Idsbetween the drain and source are represented by the following expression:

Ids=(W·Ci·µ/2L)·(Vgs-Vth)2(1)

Here, L denotes the channel length (μm), W denotes the channel width (μm), Cidenotes the capacitance of the gate dielectric (f/cm2), μ denotes the mobility of carriers field-effect (cm2/·(C), and Vthdenotes the threshold voltage ().

Although there are several ways to obtain experimental values of µ and Vthbelow is described one way. In the transistor TFT is the square root of the current Idsduring the periods of the a, while changing the voltage Vgsand direct voltage Vdssubstantially greater than the voltage Vgs, is plotted on the graph as a function of voltage Vgs. The values of µ and Vthcan be obtained from the gradient and the length of the tangential line drawn at the point arbitrary voltage Vgsin this graph. The tangent line can also be conducted at the point of voltage Vgswhere the derivative of the previous graph becomes maximum, or at the point of voltage Vgsthat should actually be applied to the transistor TFT. It is believed that in the latter case can be obtained actual values of µ and Vthnear the voltage Vgs.

One definition of transistors TFT operating in modes of enrichment and impoverishment, to simplify will be described by way of illustration transistor TFT with the n-type channel. Transistor TFT may be referred to as operating in the mode of enrichment (E)if the current Idssmall enough when the voltage Vgs=0, and therefore it may be regarded as being in the closed state. On the contrary, the transistor TFT, which has a finite current Idswhen the voltage Vgs=0 in the transistor TFT with a channel of n-type and which must be applied negative voltage Vgsas a reverse bias to cause the transistor FT in the closed state, referred to as operating in the depletion mode (D). Equivalent transistors TFT operating in modes of enrichment and depletion can be determined using the voltage Vonenable, which is the voltage Vgsat which the current Idsstarts to increase until the voltage Vgschange from the value at which the transistor TFT is in the closed state. Transistor TFT having a positive voltage Voncan be defined as a mode of dressing, and the transistor TFT having the negative voltage Voncan be identified as operating in the depletion mode. Instead of the above definition you can also define that the transistor TFT having a largely positive voltage Vthis operating in the mode of dressing, and the transistor TFT having a substantially negative voltage Vthaccordingly is operating in the depletion mode.

Although the above description was given using transistor TFT with a channel of n-type, the above description can also be considered various definitions related to modes of enrichment and depletion in the transistor TFT with a channel of p-type.

Next, it is determined that the transistor TFT with a channel of n-type, usually with a positive voltage Vsub> this operating in the mode of dressing, and the transistor TFT with a channel of n-type, substantially having the negative voltage Vthis operating in the depletion mode. However, in the case of using two transistors TFT with a channel of n-type with a positive voltage, the inverter can also be set through consideration of transistor TFT on the same side as operating in depletion mode, not enrichment, when there is a big difference between the two voltages Vth.

(The first variant embodiment)

Figure 3 shows a part cross-sectional view of the inverter in accordance with the first variant embodiment of the present invention.

The first transistor TFT 901 and the second transistor TFT 902 is fabricated on the substrate 100.

The first transistor TFT 901 contains the first electrode 201 of the gate insulating layer 300, the first channel layer 401, the first electrode 501 and the first drain electrode 601 of the source.

The second transistor TFT 902 contains the second electrode 202 of the gate insulating layer 300, the second channel layer 402, the second electrode 502 drain and the second electrode 602 of the source.

When this insulating layer 300 is entirely embedded in the first transistor TFT 901 and the second transistor TFT 902. However, it can be built separately in each transistor TFT.

The first electrode 601 source and the second electrode 502 drain are connected to each other. Partybacked 201 shutter is connected to the first electrode 601 source via a wired connection (not shown).

When the first electrode 501 drain connected to a point of Vddthe voltage of the power source and the second electrode 602 source connected to ground, so the inverter is operating in the mode of enrichment/depletion, in which the second electrode 202 shutter serves as the entry point, and the second electrode 502 drain serves as the exit point.

Thus, the first transistor, one transistor becomes operating in the depletion mode, and the second transistor, which is another transistor operates in the mode of enrichment.

The first channel layer 401 is thicker than the second channel layer 402. Thus, after fabrication of the channel layers with different thickness relative to each other, the whole appliance is heated at an arbitrary stage of manufacture. The result of this process, the first transistor TFT 901 and the second transistor TFT 902 have different values of the voltage Vthrelative to each other.

To adjust the thickness of the channel layers 401 and 402, after the formation of the total deposited film composed of an oxide semiconductor, which becomes the channel layer 401 and 402 may be performed by dry etching or the process liquid etching. Thus, when using etching, as is achieved by the formation of the channel layer only one is AZ, the manufacturing cost can be reduced.

In addition, can also be used inverse lithography. Thus, the film thickness can also be adjusted by re-forming the channel layer after applying the photoresist on the upper section of the channel layer mode of enrichment after fabrication of the channel layer, whose thickness corresponds to the thickness of the channel layer mode of dressing, which is the second channel layer 402 on the entire surface. When washing the entire structure on the substrate can be obtained channel layers with two kinds of thickness. This case is preferred because of the ability to control the film thickness is high for each channel of the layer.

(The second variant embodiment)

Figure 4 shows a part cross-sectional view of the inverter in accordance with a second alternative embodiment of the present invention.

The first transistor TFT 901 and the second transistor TFT 902 is fabricated on the substrate 100.

The first transistor TFT 901 contains the first electrode 201 of the gate insulating layer 300, the first channel layer 401, the first electrode 501 and the first drain electrode 601 of the source.

The second transistor TFT 902 contains the second electrode 202 of the gate insulating layer 300, the second channel layer 402, the second electrode 502 drain and the second electrode 602 of the source.

The first ele is trod 601 source and the second electrode 502 drain are connected to each other. The first electrode 201 shutter is connected to the first electrode 601 source via a wired connection (not shown).

When the first electrode 501 drain connected to a point of Vddthe voltage of the power source and the second electrode 602 source connected to ground, so the inverter is operating in the mode of enrichment/depletion, in which the second electrode 202 shutter serves as the entry point, and the second electrode 502 drain serves as the exit point.

Thus, the first transistor, one transistor becomes operating in the depletion mode, and the second transistor, which is another transistor operates in the mode of enrichment.

The thickness of the first channel layer 401 is approximately equal to the thickness of the second channel layer 402. The first transistor TFT 901 and the second transistor TFT 902 must have different values of Vththrough the electoral process calefaction for the channel layer 401 of the first transistor TFT compared to the process that must be performed for the channel layer 402 of the second transistor TFT.

In the present invention, the fact of the electoral process heating means control over what heat locally (selective/intensive) applies only to the specified area (also called a region), pre-fixed on the substrate. For example, Eesa way local heating of only the specified area. However, there is a case where part of the heat is transferred to the area that is different from the predetermined area, when the heating process is performed over a given area, but in the present invention, if the effect (on the film) of the transferred heat is at low levels, this effect is valid. If necessary, it is effective to provide a cooling unit in order to suppress the influence of the transfer of heat to the area that is different from the predetermined area, when the heating process is performed on the specified plot. The optimum temperature value and the exposure time of each transistor TFT is changed depending on the composition or thickness of each of the oxide semiconductor layer of the first transistor TFT and the second transistor TFT.

As is known to the authors of the present invention, subject to the conditions of heat treatment and effect in the case of manufacturing an oxide semiconductor thin film having a composition of In (indium):Ga (gallium):Zn (zinc)=1:0,9:0,6"condition, which will be described later, shows the following dependence. Thus can be obtained a permanent effect, for example, by exposure of the first transistor TFT for ten minutes or more at a temperature of 200°C and exposure of the second transistor TFT at a temperature of 120°C or less.

To selectively heat only lane the first transistor TFT, can be used various ways that local heating using a contact heating and heating by irradiation with electromagnetic waves (radiation high frequency waves, irradiation with ultraviolet rays, irradiation with the laser beam and the like).

In the present invention the above-mentioned electromagnetic waves include radio waves, high frequency waves such as microwaves, ultraviolet rays, visible rays, infrared rays, x-rays and gamma-rays.

In the present invention, the selective heating may be achieved by performing induction heating using resistivity or specific heat of various materials and the difference of the coefficients of absorption at a given wavelength.

Performing induction heating, since the difference between the amount of heat becomes larger depending on the method of selection of materials, is preferred, since the voltage Vthcan effectively be adjusted for each transistor TFT.

In addition, when using the difference of absorption coefficients depending on the materials specified transistor TFT can be selectively heated by a common heating, such as heating with pulsed lamp. And they are the NGOs, for structural materials (electrode gate electrode and source/drain) electrode of a given transistor TFT are substances that differ from the structural materials of the electrode corresponding to another transistor TFT. By providing such a structure specified transistor TFT can be selectively heated by a General optical irradiation by the pulsed lamps, etc. the process is implemented, since only the area of the electrode is formed from a material having a high absorption coefficient, selectively absorbs optical energy to heat that area. In particular, preferably the optical irradiation of the flash lamp as the heating device is simple.

However, in order to control the temperature of a given transistor TFT, for materials that differ from the structural materials of the transistor TFT may be assigned light-absorbing material or a reflective material. In addition, if necessary, can be used in the optical system, such as focus, projecting or scanning light. In addition, in the case where there is a risk that changes in the quality of the film due to the fact that heat is selectively heated is passed adjacent parts, if necessary, can be provided to block ohlord the deposits.

In other words, in variants of the embodiment of the present invention is preferred that the above-mentioned inverter has at least any patterns among the following items A to C.

A: the Structure in which the structural material of the source electrode of the above-mentioned first transistor is different from a structural element of the source electrode above the second transistor.

B: the Structure in which the structural material of the drain electrode above the first transistor is different from a structural element of the drain electrode above the second transistor.

C: the Structure in which the structural material of the gate electrode above the first transistor is different from a structural element of the gate electrode above the second transistor.

In addition, it is preferable that the step of heat treatment includes a heating process by irradiating electromagnetic waves. In addition, variants of the embodiment of the present invention is preferred that the above-mentioned inverter has at least any patterns among the following items from D to F.

D: the Structure in which the physical parameter of the structural material of the source electrode of the above-mentioned first transistor is different from the physical parameter e is ectrode source of the above-mentioned second transistor.

E: the Structure in which the physical parameter of the structural material of the drain electrode above the first transistor is different from the physical parameter drain electrode above the second transistor.

F: the Structure in which the physical parameter of the structural material of the gate electrode above the first transistor is different from a physical parameter of the gate electrode above the second microtransmitter.

Further, it is preferable that the above-mentioned physical parameter is at least one of the properties selected from the resistivity, specific heat and absorption coefficients.

(The third variant embodiment)

As shown in the first variant embodiment, after fabrication of the channel layers with different thickness, the conditions of the heating process of the first channel layer is made different from the conditions for the second channel layer, as in the method described in the second variant embodiment, when thermal process is performed in any manufacturing process.

In this way the first transistor TFT 901 and the second transistor TFT 902 have different values of the voltage Vth.

In order to efficiently operate the inverter is operating in the mode of enrichment/depletion in accordance with the present invention, bodø is described suitable range as the difference between the threshold voltages of the two transistors. Figure 5 is an image showing the result of comparison of vibration characteristics of the 31-stage ring oscillator-based inverter with saturated load mode enrichment/enrichment, with oscillatory characteristics of a 31-stage ring oscillator-based inverters operating in the mode of enrichment/depletion obtained by way of simulation using SPICE (simulation program with emphasis on an integrated circuit). In the right part of figure 5 shows the estimation, which is obtained by changing the voltage Vtha load transistor TFT in each conditions, the geometric ratio β, the relationship of the mobility of carriers of current, voltage Vddpower supply and voltage Vththe control transistor TFT mode of enrichment specified in the left side of figure 5. Here the geometric ratio β represents the ratio ratio (width W/L) of the control transistor TFT and relations (width W/L) of the load transistor TFT. The ratio of the mobility is the ratio of the mobility of the control transistor TFT and the mobility of the load transistor TFT. It should be noted that the channel length was set to L=10 μm for all transistors TFT. As for bandwidth, it was set to a =40 μm in the load transistors TFT and W=40×β µm in the control transistors TFT. Overlap length of the gate of each transistor TFT was set to 5 μm, and should only be considered parasitic capacitance caused by this overlap.

According to figure 5, when the voltage Vtha load transistor TFT satisfies the relationship shown by expression (2), for a voltage Vddthe power source is applied to the inverter, the inverter is operating in the mode of enrichment/depletion has the advantage of at least either the amplitude or oscillation frequency of the ring oscillator. Thus, each inverter is operating in the mode of enrichment/depletion, better than inverter with saturated load mode enrichment/enrichment, from the point of view of at least either speed switching, or stock immunity

0,7<|(Vth(Ld)-Vth(Dr))/Vdd|<2(2)

Thus, the expression (2) indicates that the inverter is operating in the mode of enrichment/depletion works with the same supply voltage, which satisfies the fact that the difference between the threshold voltages of the first and second transistors is in the range of less than 70% and greater than 200% of the voltage of the power source.

In the above-mentioned condition assessment in the range outside the above inequality, there is some m is of great advantage in forming the inverter, working in the mode of enrichment/depletion. Namely, in the case when |(Vth(Ld)-Vth(Dr))/Vdd|<0,7, the inverter does not have enough current to charge the load capacitance or observed unstable oscillation of the ring oscillator. On the other hand, in the case when |(Vth(Ld)-Vth(Dr))/Vdd|>2, the inversion voltage is too high compared to the supply voltage and the range of input/output voltage becomes narrow.

In addition, there will be described materials for forming transistor TFT to be used in the inverters in accordance with the present invention.

• Channel layer

For the channel layer are oxide semiconductor materials. Namely, can be used ZnO, In2O3, Ga2O3and the mixture of their crystals or amorphous solid solution (In-Zn-O, In-Ga-Zn-O and the like). Thus, can be used an oxide semiconductor which includes at least one element selected from In, Ga and Zn.

In particular, if the film of the In-Ga-Zn-O is formed as a channel layer of the transistor TFT spray application method, can be manufactured transistor having a sufficiently high mobility of carriers of field effect. In this case, since the temperature of the deposition material for the channel layer is low is th, the light emitting device can be formed on a flexible substrate, such as plastic.

In addition, the film of the In-Ga-Zn-O it is preferable that at least part of this film consisted of an amorphous substance. In accordance with this preferred structure improves the efficiency of the etching process.

• The electrodes of the drain-source

Require such materials to be used for the electrodes of the drain-source, barrier to injection of electrons to the channel layer was quite small in the case where the channel layer is an n-type semiconductor. In the case of a semiconductor p-type you want the barrier to injection of holes was quite small. For example, there may be used such a metal as Al, Cr, W, Ti and Au, aluminum alloy, and a silicide, such as WSi. In addition, can also be used transparent conductive oxide or a transparent oxide semiconductor, having a greater concentration of current. The tin oxide-indium (ITO), zinc oxide-India (IZO) and the film of the In-Ga-Zn-O correspond to the above-mentioned materials.

The electrodes of the drain-source can be formed by connecting more than one material or may be a multilayer film made of several materials.

• Electrode of the gate

Materials that should be used for the gate electrode, selected from the group of the mother of the crystals, similar to those described above for the electrodes of the drain-source. Can be used various metal thin film GIS, the conductive oxide thin film and the conductive organic thin film. The materials can be used for selective heating through the use of differences in physical properties, such as resistivity, specific heat of these different materials or the absorption coefficient at a given wavelength. It should be noted that preferential heating channel unit can be achieved also by the material of the electrodes of the drain-source.

The gate electrode may be formed by connecting more than one material or may be a multilayer film made of several materials.

Flat film is formed on the insulating layer of the shutter, and requires that the materials were of low conductivity. Namely, the current Igsleakage between the gate and source should be in practice quite small compared to the current Idsleakage between drain and source.

The film material is selected from SiOxSiNxand SiOxNyformed by the method of chemical vapour deposition (CVD), material SiO2SiNx, SiOxNy, Al2O3, Y2O3, HfO2and Ta2O5/sub> formed by the method of radio-frequency magnetron sputtering, and a multilayer film composed of these materials. As illustrated in figure 3, the film may be shared by two or more transistors TFT, or may be individual film for each transistor TFT.

When the inverter is operating in the mode of enrichment/depletion is produced by two types of transistors TFT, two threshold voltage Vthdoesn't always have to be in such a ratio that one voltage is maintained negative and the other positive, when they are embedded in the scheme. The present invention can be applied even if the two types of transistors TFT are working in the mode of enrichment or operating in the depletion mode, in the case where two threshold voltage Vthsignificantly different, and these two transistors TFT can be used separately from the point of view of a design schema.

In addition, the present invention can be similarly applied also in the case of manufacturing three or more types of transistors TFT in which the threshold voltage Vthyou can distinguish each other.

Estimated physical property of an amorphous film of an In-Ga-Zn-O, which will be used as the channel layer of the transistor TFT.

As the substrate on which the Fort is associated film, was prepared defatted cleaned glass substrate (product 1737 Corporation Corning Corporation). As the target material was used polycrystalline sintered product (dimensions: diameter of 98 mm, thickness 5 mm)having the composition InGaO3(ZnO).

This sintered product was manufactured using the wet process mixing materials In2O3:Ga2O3:ZnO (4N each reagent, solvent: ethanol), pre-sintering (at 1000°C for two hours), the process of dry grinding process and the main sintering (at 1500°C for two hours) as the starting material.

Conductivity of the target material is 0.25 (Siemens/cm), which indicates predilections property.

The residual pressure in the vacuum chamber for deposition is 3×10-4PA, and the total pressure during deposition (namely the formation of a film) was set equal to 0.53 PA using a mixture of oxygen and argon, which contains 3,3 volume percent of oxygen.

The temperature of the substrate is not specifically regulated, and the distance between the target material and a substrate on which is formed the film was 80 mm, an Applied electric power was 300 W, and a film was formed with a deposition rate of 2 Å/s

On the surface asadena the film thickness of 60 nm was directed x-ray beam with an incidence angle of 0.5 degrees, and it made the measurement of the diffraction x-ray beam using the method of a thin film. As a result, has not been confirmed explicitly diffraction maximum, it was resolved that made the film of the In-Ga-Zn-O amorphous.

In the x-ray fluorescence (XRF) analysis of the ratio of metals in the composition of the thin films was expressed as In:Ga:Zn=1:0,9:0,6.

After performing measurements in two points I-V through electrode pattern coplanar type using the deposited multilayer film of Ti and Au, when was the measured conductivity of a thin film, it was approximately 7×10-5Siemens/see If it is assumed that the electron mobility is approximately 5 cm2/·Estimated that the concentration of electrons is approximately 1014cm-3.

In accordance with the above test, it was confirmed that the as-built system thin film of the In-Ga-Zn-O contains In, Ga and Zn, and at least part of the thin film is an amorphous oxide.

In the future, the substance for forming the channel layer, which must be manufactured, contains In, Ga and Zn, and at least part of the substance is an amorphous oxide.

Allow the correlation of the composition of the metals was not the above-mentioned ratio of In:Ga:Zn=1:0,9:0,6.

Then several is like transistors TFT are respectively made on four different substrates in accordance with the following procedure, and prepared samples 1-4. The cross-section of the transistor TFT manufactured in each of samples 1-4, shown in Fig.6.

The cleaned glass substrate (product 1737 Corporation Corning Corporation) is used as the substrate 100, and Ti and Au napylyaetsya on the substrate with a total thickness of 50 nm by electron beam deposition and then forming a pattern by the method of inverse lithography, and by this means the electrode 200 shutter. Then a layer of SiO2that will become the insulating layer 300 shutter is formed (gas deposition: Ar, deposition pressures: 0.1 PA, the applied electric power: 400 W, film thickness: 100 nm) on the entire surface by the method of radio-frequency magnetron sputtering. A hole is formed in a part (not shown), the insulating layer 300 shutter located on the upper electrode 200 shutter, by etching, and the result is a contact hole used for contact with the electrode 200 shutter. Then a layer of amorphous IGZO (In-Ga-Zn-O) is formed (gas deposition: O2(3,3 volume%) + Ar, pressure deposition: 0,53 PA, applied electric power: 300 W) using RF magnetron sputtering as a channel layer 400. The film thickness was made equal to 30 nm in samples 1 and 2 and is equal to 60 nm in samples 3 and 4. During deposition by sputtering technique so the temperature value of the substrate is not specifically regulated.

Then at the data link layer 400 was drawing in the predefined size of the channel by etching.

Then the samples 2 and 4 were completely and uniformly heated on a hot plate whose temperature was set to 300°C for twenty minutes in an air atmosphere. This thermal process is not applied to samples 1 and 3.

Finally, Ti and Au were again napisany for the formation of a film, the thickness of which generally amounted to 100 nm by electron beam deposition, and then the electrode 500 drain electrode 600 of the source formed by the method of inverse lithography. Transistors TFT, the width W of the channel which is 40 μm and 200 μm or 800 μm, were produced in the respective samples. The length L of the channel was set to L=10 μm for the respective samples.

Characteristics depending on the Ids-Vgsmeasured at voltage Vds=+10 V in these samples, shown in figa-7H. All these characteristics clearly show the characteristics of the transistor TFT with a channel of n-type.

When you have calculated the mobility µ of the media field-effect and threshold voltage Vth, the following results were obtained.

Sample 1 (the thickness of the channel layer d=30 nm, thermal process is not running)

W=40 µm, µ=6,5, Vth=+3,5

W=800 µm, µ=2,0, Vth=+3,4;

Sample 2 (the thickness of the channel layer d=30 nm, heat about the ECC is)

W=40 µm, µ=9,3, Vth=-0,23

W=800 µm, µ=7,8, Vth=+1,4;

Sample 3 (the thickness of the channel layer d=60 nm, thermal process is not running)

W=40 µm, µ=6,0, Vth=+2,1

W=200 µm, µ=4.2V, Vth=+1,5;

Sample 4 (the thickness of the channel layer d=60 nm, a thermal process is performed)

W=40 µm, µ=9,7, Vth=-10,1

W=200 μm: µ=15, Vth=-3,0.

Both transistors TFT in samples 1 and 3 are working in the mode of dressing, and the transistor TFT in the sample 4 is operating in the depletion mode.

On the other hand, in the transistor TFT having the channel width W=40 μm in sample 2, while the voltage Vthis negative in the strict sense, it is expected that the transistor TFT operates in the mode of enrichment depending on the combination with other transistor TFT, as will be shown later.

Although not specifically described, since in the course of the manufacturing process, all samples are dried (at 120°C for ten minutes) several times in the air, it is assumed that the change in electrical properties due to the application of heat under conditions corresponding to the above-mentioned conditions can be neglected after the samples are made.

Based on the above experiment made inverters, are described in the following respective embodiments of the incarnation.

<embodiment 1>

This option is proxenia 1 is an example of a first variant embodiment. The manufacturing process of the inverter is operating in the mode of enrichment/depletion using an oxide semiconductor thin film transistor in a variant of embodiment 1 shown in Fig.

The cleaned glass substrate (product 1737 Corporation Corning Corporation) was used as the substrate 100.

After forming the photoresist (not shown) on the substrate using a first photolithography process Ti and Au napylyaetsya with a total thickness of 50 nm by electron beam deposition, and then patterning method, inverse lithography, and through this to get the first electrode 201 shutter and the second electrode 202 of the gate.

Then a layer of SiO2that will become the insulating layer 300 shutter, which is common to the first transistor TFT and the second transistor TFT is formed (gas deposition: Ar, deposition pressures: 0.1 PA, the applied electric power: 400 W, film thickness: 100 nm) on the entire surface by the method of radio-frequency magnetron sputtering. After forming the photoresist (not shown) formed on this film by a second photolithography process on the part of the insulating layer 300 shutter button located on the upper parts of the electrodes 201 and 202 of the shutter, a drawing by etching and obtained a contact hole (not shown).

Then, the film 400 of amorf the CSOs IGZO (total deposited film), which will become a channel layer composed of an oxide semiconductor is formed (gas deposition (i.e. gas formation film): O2(3,3 volume%) + Ar, deposition pressures (i.e. the pressure of formation of the film): 0,53 PA, applied electric power: 300 watts) method of the radio-frequency magnetron sputtering. The film thickness is 60 nm, is formed on both sites, the respective channel layers of the first and second transistors TFT. During deposition by sputtering technique, the temperature of the substrate is not specifically regulated.

Then, a photoresist (not shown) is formed on the upper plot of the film 400 made of amorphous IGZO in the area 801, where he formed the first transistor TFT, using a third photolithography process, and then the film 400 made of amorphous IGZO is subjected to dry etching. The etching is performed with the adjustment of time and intensity to the film thickness 400 of amorphous IGZO in the field 802, where he formed a second transistor TFT, became equal to 30 nm.

After forming the photoresist (not shown) through a fourth photolithography process film 400 made of amorphous IGZO is subjected to etching to separate the film from the amorphous IGZO, so that the channel layer became an independent layer for each transistor. Thus obtained, the first channel layer 401 and the second channel slay.

Then the whole structure is uniformly heated on a hot plate whose temperature is set to 300°C for twenty minutes in an air atmosphere.

Finally, after forming the photoresist (not shown) through a fifth photolithography process Ti and Au again napylyaetsya for the formation of a film, the thickness of which a total of 100 nm by electron beam deposition. Then the first electrode 501 of the flow, the first electrode 601 source, the second electrode 502 drain and the second electrode 602 source formed by the method of inverse lithography. At this time, the first electrode 601 source and the second electrode 502 drain are formed together, as shown in Fig, and electrically connected with each other. In addition, the first electrode 601 source connected with the first electrode 201 shutter through the simultaneous formation of interlayer wired connection (not shown) through the above-mentioned contact hole together with the electrodes of the drain-source.

In accordance with the above description turns the inverter is operating in the mode of enrichment/depletion, in which the first electrode 501 of the flow is considered as the point of supply voltage and the second electrode 602 source is considered as a grounding point.

It should be noted that the processes of photolithography is performed five times.

To assess dinamicas the e characteristics of the inverter, working in the mode of enrichment/depletion is made in accordance with the above procedure, was performed circuit simulation of the 5-stage ring oscillator, which consists of inverters operating in the mode of enrichment/depletion, characterized in that each transistor TFT that has a width of W=40 μm in sample 4, is set as the load transistor TFT, and each transistor TFT having a width W=200 μm in the sample 2, is set as the control transistor TFT. For the simulation model was used level 1 (the structure of metal-oxide-semiconductor (MOS) with the n-type channel), which is the simplest model MOS. In the 5-stage ring oscillator was implemented oscillations with a frequency of 470 kHz at a voltage of external power supply +10 C. the delay Time was equal to 0.21 ISS. The amplitude of 8.0 and a maximum value of +9.7 In the output voltage in the approximation is equal to the supply voltage +10 C. the output waveform shown in Fig.9.

In this variant of embodiment 1, the inverter is operating in the mode of enrichment/depletion may simply be formed only by adding one photolithography process compared to the process of manufacturing the inverter with saturated load mode enrichment/enrichment shown in comparative example 1-1.

Comparative example 1-1)

Although this method of manufacture is similar to the variant of embodiment 1, two types of transistors TFT are fabricated on the same substrate without performing a process of regulating the layer thickness of both the channel layer to have different thicknesses. Thus, two types of transistors TFT are fabricated on the same substrate under the conditions that the channels of both transistors TFT have the same film thickness of 30 nm, and using a manufacturing method having the same conditions of the heating process. Then can be made inverter with saturated load mode enrichment/enrichment. The process flow related to the above, shown in figure 10.

The cleaned glass substrate (product 1737 Corporation Corning Corporation) was used as the substrate 100.

After forming the photoresist (not shown) on the substrate using a first photolithography process Ti and Au napylyaetsya with a total thickness of 50 nm by electron beam deposition, and then patterning method, inverse lithography, and through this to get the first electrode 201 shutter and the second electrode 202 of the gate.

Then a layer of SiO2that will become the insulating layer 300 shutter, which is common to the first transistor TFT and the second transistor TFT is formed (gas deposition: Ar, pressure besieged the I: 0.1 PA, applied electric power: 400 W, film thickness: 100 nm) on the entire surface by the method of radio-frequency magnetron sputtering. After forming the photoresist (not shown) formed on this film by a second photolithography process on the insulating layer 300 shutter is applied to the image by etching, and the upper parts of the electrodes 201 and 202 of the gate is obtained a contact hole (not shown).

Then, the film of the amorphous IGZO is formed (gas deposition: O2(3,3 volume%) + Ar, pressure deposition: 0,53 PA, applied electric power: 300 W) using RF magnetron sputtering as a channel layer 400. The film, whose thickness is 30 nm, is formed on both sites, the respective channel layers of the first and second transistors TFT. During deposition by sputtering technique, the temperature of the substrate is not specifically regulated.

After forming the photoresist (not shown) through a third photolithography process channel layer 400 is subjected to etching and get the first channel layer 401 and the second channel layer 402.

Then the whole structure is uniformly heated on a hot plate whose temperature is set to 300°C for twenty minutes in an air atmosphere.

Finally, after forming the photoresist (not showing the n) using a fourth photolithography process Ti and Au again napylyaetsya for the formation of a film, the thickness of which a total of 100 nm by electron beam deposition. Then the first electrode 501 of the flow, the first electrode 601 source, the second electrode 502 drain and the second electrode 602 source formed by the method of inverse lithography. At the same time, the first electrode 501 drain connected with the first electrode 201 of the gate by forming an interlayer wired connection (not shown) through the above-mentioned contact hole.

The first electrode 601 source integrated with the second electrode 502 of the flow.

In accordance with the above description turns the inverter with saturated load mode enrichment/enrichment, in which the first electrode 501 of the flow is considered as the point of supply voltage and the second electrode 602 source is considered as a grounding point. The photolithography processes are performed four times.

In order to evaluate the dynamic characteristics of the inverter with saturated load mode enrichment/enrichment, made in accordance with the above procedure, was performed following circuit simulation. Thus, it was made of circuit modeling of the 5-stage ring oscillator, which consists of an inverter with saturated load mode enrichment/enrichment, characterized in that each of the of ransistors TFT, with a width of W=40 μm in the sample 2, is configured as a load transistor TFT, and each transistor TFT having a width W=200 μm in the sample 2, is set as the control transistor TFT. The output waveform is shown at 11. 5-stage ring oscillator was implemented oscillations with a frequency of 350 kHz at a voltage of external power supply +10 C. the delay Time of one cascade amounted to 0.29 μs, which is forty percent more compared with the variant of embodiment 1. The amplitude amounted to 5.5 V, and the maximum value of the output voltage was +7.1 In that approximately 3 In less than supply voltage +10 C.

Thus, the inverter is operating in the mode of enrichment/depletion in the variant of embodiment 1 operates at a higher speed with a higher amplitude than the inverter with saturated load mode enrichment/enrichment, in the present comparative example. And in accordance with the manufacturing method in the variant of embodiment 1 can be expected can be obtained inverter, higher quality, than in comparative example 1-1.

It should be noted that the voltage Vthtransistor TFT that has a width of W=40 μm in the sample 2, is slightly less than 0 In the strict sense. However, it is important that it is approximately equal to the value of voltage Vthtransistor TFT, and housego width W=200 μm in sample 2, and the load transistor TFT that has a width of W=40 μm in sample 2, can largely be seen as a mode of enrichment in this combination.

It was also performed circuit simulation of the 5-stage ring oscillator, in which each transistor TFT that has a width of W=40 μm in sample 4, is considered as a load transistor TFT, and each transistor TFT having a width W=200 μm in sample 4, is considered as the control transistor TFT. Fluctuations could not be found in any case, when the inverter is the inverter mode of enrichment/depletion or inverter with saturated load mode enrichment/enrichment.

(Comparative example 1-2)

Considered a method of manufacturing the inverter is operating in the mode of enrichment/depletion, similar to the method in the above-described variant of the embodiment 1, on the basis of the method of forming the channel layer, disclosed in published patent application of Japan No. 2006-165532. In the method described in published patent application of Japan No. 2006-165532, the voltage Vthis regulated by the concentration of nitric oxide fed into the atmosphere of the deposition of ZnO. In the case of manufacturing transistor TFT having two kinds of voltages Vthon the same substrate, requires the process of formation of the channel layer, with different doping concentration of the semiconductor in order to obtain the first channel layer and the second channel layer, respectively.

The inverter is operating in the mode of enrichment/depletion can be manufactured using the following process is similar to the process in the comparative example 1-1. The manufacturing process will be described using Fig.

The cleaned glass substrate (product 1737 Corporation Corning Corporation) was used as the substrate 100.

After forming the photoresist (not shown) on the substrate using a first photolithography process Ti and Au napylyaetsya with a total thickness of 50 nm by electron beam deposition, and then patterning method, inverse lithography, and through this to get the first electrode 201 shutter and the second electrode 202 of the gate.

Then a layer of SiO2that will become the insulating layer 300 shutter, which is common to the first transistor TFT and the second transistor TFT is formed (gas deposition: Ar, deposition pressures: 0.1 PA, the applied electric power: 400 W, film thickness: 100 nm) on the entire surface by the method of radio-frequency magnetron sputtering. After forming the photoresist (not shown) formed on this film by a second photolithography process on the insulating layer 300 shutter is applied to the image group is a rotary etching and on the upper parts of the regions (not shown) of the electrodes 201 and 202 of the gate is obtained a contact hole (not shown).

Then a layer of ZnO, which will be the first channel layer 401 is formed by pulsed laser deposition. Intentional doping of the first channel layer 401 is not used. A photoresist (not shown) is formed through a third photolithography process is performed patterning by etching, and get the first channel layer 401. Additionally, a layer of ZnO, which will become the second channel layer 402 is formed by pulsed laser deposition using a similar procedure. At this time, the second channel layer 402 legarrette nitrogen through a set of atmospheric deposition from the gas mixture of oxygen and nitrous oxide. A photoresist (not shown) is formed through a fourth photolithography process is performed patterning by etching, and it turns out the second channel layer 402.

Finally, after forming the photoresist (not shown) through a fifth photolithography process Ti and Au again napylyaetsya for the formation of a film, the thickness of which a total of 100 nm by electron beam deposition. Then the first electrode 501 of the flow, the first electrode 601 source, the second electrode 502 drain and the second electrode 602 source formed by the method of inverse lithography. At the same time, the first electrode 601 source connected with the first electrode 201 shutter through the formation of the deposits via a wired connection (not shown) through the above-mentioned contact hole.

The first electrode 601 source and the second electrode 502 drain are formed as a single unit.

In accordance with the above description turns the inverter is operating in the mode of enrichment/depletion, in which the first electrode 501 of the flow is considered as the point of supply voltage and the second electrode 602 source is considered as a grounding point. It should be noted that the resulting inverter can be appropriately continuously formed protective layer, and the difference between the voltage Vththe first transistor 901 and the voltage Vththe second transistor 902 can be adjusted more preferable.

The processes of photolithography in the above-described procedure is performed five times, which is equal to the number of times of processing in the variant of embodiment 1.

However, the manufacturer of the inverter using the procedure described above is actually complex, and the processes of photolithography requires at least six times, one more compared to the variant of embodiment 1.

The reason for the above-mentioned lists the following two problems.

Below is mentioned the first problem. When forming the second channel layer 402, the first channel layer 401 is also introduced into the chamber for deposition. In the above-described method cannot be avoided that the first channel layer 401 is placed is moved in an atmosphere of deposition during the formation of the second channel layer 402. As a result, it is not preferred because there is a risk that the electrical properties of the first channel layer 401 will change before or after forming the second channel layer 402. In order to prevent this situation, in the case of providing a sealing layer (photoresist or films obtained by spray SiNxon the first channel layer 401 for the protection of the first channel layer 401 from atmospheric deposition of the second channel layer 402, an additional photolithography process.

Following is the second problem. In the case of drawing on the second channel layer 402 by etching after application of the pattern on the first channel layer 401, the ratio of the etching selectivity of the last layer to the first layer becomes important that the first layer was not affected by the etching of the last layer. However, the distinction between structural components of the first channel layer 401 and the second channel layer 402 is only contained in the amount of dopant, and it is assumed that the ratio of the etching selectivity is approximately equal to unity. Therefore, in order to perform the guaranteed etching, must be provided with the protection layer etching in the area 801, where he formed the first transistor TFT. In this case also requires an additional process totalitar the AI.

Therefore, by using the manufacturing method of the present invention it is possible to make the inverter is operating in the mode of enrichment/depletion simple way with fewer treatments than in the method of manufacturing the inverter is operating in the mode of enrichment/depletion used in traditional technology.

<embodiment 2>

In a variant of embodiment 2 shows a case of using the method of inverse lithography of forming the channel layer in the variant of embodiment 1. The process will be described again using Fig.

After receiving the contact holes in a manner analogous to the method in the variant of embodiment 1, the film 400 made of amorphous IGZO, which will become part of the channel layer continuously formed (gas deposition: O2(3,3 volume%) + Ar, pressure deposition: 0,53 PA, applied electric power: 300 watts) method of the radio-frequency magnetron sputtering. The film, whose thickness is 30 nm, is formed with the same thickness on both sites, the respective channel layers of the first and second transistors TFT. During deposition by sputtering technique, the temperature of the substrate is not specifically regulated.

Then, a photoresist (not shown) is formed on the upper part of the film 400 made of amorphous IGZO in the field 802, where he formed the second Tran the STO TFT, using a third photolithography process. The photoresist appropriately thermally processed, and it is preferable to increase the resistance to damage from spraying in the subsequent process. Film of amorphous IGZO, whose thickness is 30 nm, again formed as the remainder of the film 400 made of amorphous IGZO on the photoresist and in the field 801, where he formed the first transistor TFT, a method of radio-frequency magnetron sputtering under similar conditions. Additionally, the entire structure is rinsed with a solution to remove the photoresist to remove the photoresist and the film of amorphous IGZO formed on the upper section of the photoresist, and the channel layer napalan only on the first transistor TFT for forming the channel layer of the first transistor TFT. At this time, the obtained channel layers having a different thickness for each transistor TFT of the two transistors TFT, as shown in Fig.

After this is obtained by the inverter is operating in the mode of enrichment/depletion, through a procedure similar to the procedure used in the variant of embodiment 1. It should be noted that the processes of photolithography is performed five times.

Thus, in the case of using the method of inverse lithography when forming the channel layer can be obtained an effect similar to the variant of embodiment 1. In addition, the possibility to regulate the Finance thickness of the channel layer is much better compared with the variant of embodiment 1.

<embodiment 3>

This variant of embodiment 3 is an example of a second variant embodiment. The manufacturing process of the inverter is operating in the mode of enrichment/depletion, using the oxide thin film transistor in a variant of embodiment 3 will be shown on Fig.

Film of tin oxide-indium (ITO, conductivity: 1×104Siemens/cm), whose thickness is 200 nm, is formed on the cleaned glass substrate (product 1737 Corporation Corning Corporation) using RF magnetron sputtering, and a photoresist (not shown) is formed on this film formed using the first photolithography process. After this is done the patterning by etching and get the first electrode 201 of the gate.

Then, after forming a photoresist (not shown) on the glass substrate using a second photolithography process Ti and Au napylyaetsya with a total thickness of 50 nm by electron beam deposition, is drawing figure method of inverse lithography and get the second electrode 202 of the gate.

Then a layer of SiO2that will become the insulating layer 300 shutter, which is common to the first transistor TFT and the second transistor TFT is formed (gas deposition: Ar, deposition pressures: 0.1 PA, the applied electric power: 400 W, the woman film: 100 nm) on the entire surface by the method of radio-frequency magnetron sputtering. After forming the photoresist (not shown) formed on this film by a third photolithography process is performed patterning by etching and obtained a contact hole (not shown).

Then, the film 400 made of amorphous IGZO, which will become a channel layer is formed (gas deposition: O2(3,3 volume%) + Ar, pressure deposition: 0,53 PA, applied electric power: 300 watts) method of the radio-frequency magnetron sputtering. The film thickness is 60 nm, is formed on both sites, the respective channel layers of the first and second transistors TFT. During deposition by sputtering technique, the temperature of the substrate is not specifically regulated. The film 400 made of amorphous IGZO is subjected to etching for dividing the order of the channel layer became an independent layer for each transistor. Thus obtained, the first channel layer 401 and the second channel layer 402.

Then the entire structure of the inductively heated. Since the resistivity of the electrode of ITO is approximately fifty times greater than the electrode of Au, the first electrode 201 shutter selectively heated in comparison with the second electrode 202 of the shutter. Use the power of the applied alternating magnetic field, frequency and time of application, which have been optimized. The deterioration of the wearing selectivity of the heat conduction substrate is prevented by intermittent application of an alternating magnetic field, used for induction heating, as needed. Is also effective to heat applied to the electrode 202 of the gate, was assigned using a cooling unit, such as a heat sink.

Finally, after forming the photoresist (not shown) through a fifth photolithography process Ti and Au again napylyaetsya for the formation of a film, the thickness of which a total of 100 nm by electron beam deposition. Then the first electrode 501 of the flow, the first electrode 601 source, the second electrode 502 drain and the second electrode 602 source formed by the method of inverse lithography. At the same time, the first electrode 601 source connected with the first electrode 201 of the gate by forming an interlayer wired connection (not shown) through the above-mentioned contact hole.

The first electrode 601 source and the second electrode 502 drain are formed as a single unit.

In accordance with the above description turns the inverter is operating in the mode of enrichment/depletion, in which the first electrode 501 of the flow is considered as the point of supply voltage and the second electrode 602 source is considered as a grounding point. It should be noted that the processes of photolithography is performed five times.

In order to evaluate the dynamic characteristics of the inverter operating mode abogada the Oia/depletion performed circuit simulation of the 5-stage ring oscillator, which consists of inverters operating in the mode of enrichment/depletion, characterized in that the transistor TFT that has a width of W=40 μm in sample 4, is set as the load transistor TFT, and the transistor TFT having a width W=200 μm in sample 3, is set as the control transistor TFT.

In the 5-stage ring oscillator was implemented oscillations with a frequency of 390 kHz at a voltage of external power supply +10 C. the Time delay 0.26 μs. The amplitude amounted to 5.5 V, and the maximum value of the output voltage for a single cascade was +9.0 In that 1.0 In less than the source voltage +10 C. the output waveform shown in Fig.

In this variant embodiment, the inverter is operating in the mode of enrichment/depletion may simply be formed only by adding one photolithography process compared to the process of manufacturing the inverter with saturated load mode enrichment/enrichment (comparative example 3-1).

Alternatively, the same material can be used as materials for forming the electrodes of the source, drain and gate in these two types of transistors TFT. Even if you use this structure and was formed by the channel layer, is within the same thickness, can be obtained an effect similar to the effect in a variant of embodiment 3, during the process of heating channel layer is heated only close neighbor of the first channel layer 401 through contact heating or laser annealing.

In this case, can be eliminated one photolithography process.

However, in a variant of embodiment 3, the device can be simplified, and the possibility of regulation refined, if induction heating is performed by making transistor TFT, which includes a variety of materials for forming the electrodes of the source, drain and gate, or by heating a flash lamp using the difference between the absorption coefficients depending on the materials.

In this variant of embodiment 3 of the induction heating is performed by using different materials for the electrodes of the shutter in two types of transistors. However, the effect similar to the effect in a variant of embodiment 3 can be obtained also by performing induction heating using different materials for the other electrodes, except for the gate electrode, such as a source electrode or a drain of the first transistor, or the corresponding electrode of the second transistor.

(Comparative example 3-1)

Although this method is izgotovlenie the same way in a variant of embodiment 3, two types of transistors TFT are fabricated on the same substrate by setting the thickness of both of the channel layer 60 nm so that there is no preferential heating for the first channel layer 401 and does not execute the processes of heating for both channels of transistors TFT. Then can be made inverter with saturated load mode enrichment/enrichment, through the use of four photolithography processes similarly to comparative example 1-1 in a variant of embodiment 1.

In order to evaluate the dynamic characteristics of the inverter with saturated load mode enrichment/enrichment was performed circuit simulation of the 5-stage ring oscillator, which consists of an inverter with saturated load mode enrichment/enrichment, characterized in that the transistor TFT that has a width of W=40 μm in sample 3, is set as the load transistor TFT, and the transistor TFT having a width W=200 μm in sample 3, is set as the control transistor TFT. In the 5-stage ring oscillator was implemented oscillations with a frequency of 150 kHz at a voltage of external power supply +10 V and the amplitude was 4.4 Century, the Time delay for a single cascade amounted to 0.66 μs, which is approximately two and a half times greater than for option voploscheni is 3. The maximum value of the output voltage is approximately +6 V, which is significantly smaller in comparison with a variant of embodiment 3. Thus, the inverter is operating in the mode of enrichment/depletion in the variant of embodiment 3 operates at a higher speed with a higher amplitude than the inverter with saturated load mode enrichment/enrichment, in this comparative example. Therefore, in accordance with the method of manufacture in a variant of embodiment 3 can be expected can be obtained inverter, much better than in comparative example. The output waveform shown in Fig.

<a Variant of embodiment 4>

This variant of embodiment 4 is an example of a third variant embodiment. The manufacturing process of the inverter is operating in the mode of enrichment/depletion using an oxide semiconductor thin film transistor in a variant of embodiment 4 will be shown on Fig.

The cleaned glass substrate (product 1737 Corporation Corning Corporation) was used as the substrate 100.

After forming the photoresist (not shown) on the glass substrate using the first photolithography process Ti and Au napylyaetsya with a total thickness of 50 nm by electron beam deposition, and then patterning method, inverse lithography, and what redstem this is obtained by the first electrode 201 shutter and the second electrode 202 of the gate.

Then a layer of SiO2that will become the insulating layer 300 shutter, which is common to the first transistor TFT and the second transistor TFT is formed (gas deposition: Ar, deposition pressures: 0.1 PA, the applied electric power: 400 W, film thickness: 100 nm) on the entire surface by the method of radio-frequency magnetron sputtering. After forming the photoresist (not shown) formed on this film by a second photolithography process on the part of the insulating layer 300 shutter button located on the upper parts of the first electrode 201 shutter and the second electrode 202 shutter, a drawing by etching and obtained a contact hole (not shown).

Then, the film 400 made of amorphous IGZO, which will become a channel layer is formed (gas deposition: O2(3,3 volume%) + Ar, pressure deposition: 0,53 PA, applied electric power: 300 watts) method of the radio-frequency magnetron sputtering. The film thickness is 60 nm, is formed on both sites, the respective channel layers of the first and second transistors TFT. During deposition by sputtering technique, the temperature of the substrate is not specifically regulated.

Then, a photoresist (not shown) is formed on the upper plot of the film 400 made of amorphous IGZO in the area 801, where he formed the first transistor TFT, using retigo process of photolithography, and then the film 400 made of amorphous IGZO is subjected to dry etching. The etching is performed with the adjustment of time and intensity to the film thickness 400 of amorphous IGZO in the field 802, where he formed a second transistor TFT, became equal to 30 nm.

After forming the photoresist (not shown) through a fourth photolithography process film 400 made of amorphous IGZO is subjected to etching for dividing the order of the channel layer became an independent layer for each transistor. Thus obtained, the first channel layer 401 and the second channel layer 402.

Then only close neighbor of the first channel layer 401 is heated focused laser beam. At this time, the second channel layer 402 is slightly heated due to thermal conductivity of the substrate, although it was not heated as well as the first channel layer 401.

However, as confirmed by the testimony of graphs on figa-7H, because changes in voltage Vthtransistor TFT that uses the second channel layer are small before and after heating in comparison with transistor TFT, using the first channel layer, it is believed that the heating process is not applied to the channel layer 402.

Finally, after forming the photoresist (not shown) through a fifth photolithography process Ti and Au again napylyaetsya for the formation of a film thickness to the Torah as a whole is 100 nm, by electron beam deposition. Then the first electrode 501 of the flow, the first electrode 601 source, the second electrode 502 drain and the second electrode 602 source formed by the method of inverse lithography. At this time, the first electrode 601 source and the second electrode 502 drain are formed together, as shown in Fig, and electrically connected with each other. In addition, the first electrode 601 source connected with the first electrode 201 shutter through the simultaneous formation of interlayer wired connection (not shown) through the above-mentioned contact hole together with the electrodes of the drain-source.

In accordance with the above description perform the inverter is operating in the mode of enrichment/depletion, in which the first electrode 501 of the flow is considered as the point of supply voltage and the second electrode 602 source is considered as a grounding point. It should be noted that the processes of photolithography is performed five times.

To assess the dynamic characteristics of the inverter is operating in the mode of enrichment/depletion manufactured through the above procedure, was performed circuit simulation of the 5-stage ring oscillator, which consists of inverters operating in the mode of enrichment/depletion, characterized in that the transistor TFT that has a width of W=40 μm in sample 4, the backside of the n as a load transistor TFT, and the transistor TFT that has a width of W=800 μm in the sample 1, is set as the control transistor TFT.

In the 5-stage ring oscillator was implemented oscillations with a frequency of 114 kHz at a voltage of external power supply +10 C. the delay Time was 0.88 ISS. The amplitude was 7.8, and the maximum value of the output voltage was +10 V, which is equal to the voltage of the power source. The output waveform shown in Fig.

In this variant of embodiment 4, the inverter is operating in the mode of enrichment/depletion can be simply formed by using the same number of photolithography processes or by adding only one photolithography process in comparison with the manufacturing processes of inverter with saturated load mode enrichment/enrichment, as shown in the following comparative examples.

When providing the difference of the film thickness adjustment film thickness can be performed by the method of inverse lithography, as shown in the variant of embodiment 2, without performing etching. In this case, the ability to control the film thickness is improved.

When differences in the conditions of heating are two types of transistors TFT can be manufactured from different materials for forming the electrodes of the source, drain and gate, as shown in the variant embodied the I 3, and the heat can be selectively performed by induction heating or optical radiation.

(Comparative example 4-1)

Although this method of manufacture is similar to the variant of embodiment 4, two types of transistors TFT are fabricated on the same substrate so that there is no preferential heating for the first channel layer 401 and does not execute the processes of heating for grooves of both transistors TFT. Then can be made inverter with saturated load mode enrichment/enrichment.

Similarly to the variant of embodiment 4, as shown in Fig, obtained the first channel layer 401 and the second channel layer 402, which was provided by the difference of the film thickness by etching or by the method of inverse lithography. Then, a photoresist (not shown) is formed by a fifth photolithography process. Thereafter, Ti and Au again napylyaetsya for the formation of a film, the thickness of which generally is 100 nm, the method of electron-beam deposition, and the first electrode 501 of the flow, the first electrode 601 source, the second electrode 502 drain and the second electrode 602 source formed by the method of inverse lithography.

As for the above-mentioned electrodes, the first electrode 201 shutter is connected with the first electrode 501 of the flow through the formation of external PR is water connections (not shown), but is not connected with the first electrode 601 of the source. Thus, it can be obtained inverter with saturated load mode enrichment/enrichment, in which the first electrode 501 of the flow is considered as the point of supply voltage, and the second electrode 602 source is considered as a grounding point. It should be noted that the processes of photolithography is performed five times.

In order to evaluate the dynamic characteristics of the inverter with saturated load mode enrichment/enrichment manufactured through the above-described procedure was performed following circuit simulation. Thus, it was made of circuit modeling of the 5-stage ring oscillator, which consists of an inverter with saturated load mode enrichment/enrichment, characterized in that the transistor TFT that has a width of W=40 μm in sample 3, is set as the load transistor TFT, and the transistor TFT that has a width of W=800 μm in the sample 1, is set as the control transistor TFT. The output waveform shown in Fig. 5-stage ring oscillator was implemented oscillations with a frequency of 30 kHz at a voltage of external power supply +10 C. the delay Time for each cascade was 3.4 μs, which is 3.8 times more in comparison with a variant of embodiment 4. The amplitude was 5,6B, and the maximum value of the output voltage was +6.8 V, which is approximately +3.2 V less than the supply voltage +10 C. Thus, compared to the inverter with saturated load mode enrichment/enrichment manufactured in this comparative example 4-1, the inverter is operating in the mode of enrichment/depletion in the variant of embodiment 4 operates at a higher speed with a higher amplitude than the inverter with saturated load mode enrichment/enrichment manufactured in this comparative example 4-1. Therefore, in accordance with the method of manufacture in a variant of embodiment 4 can be expected can be obtained inverter, much better than in comparative example 4-1.

(Comparative example 4-2)

Although this method of manufacture is similar to the variant of embodiment 4, two types of transistors TFT are fabricated on the same substrate so that there is no process to set both channels of different thickness, and only change the conditions of heating under a condition in which the channels of both transistors TFT have the same thickness of 30 nm. Then can be made inverter with saturated load mode enrichment/enrichment.

The corresponding manufacturing process is shown in figure 10.

The cleaned glass substrate (and is the product 1737 Corporation Corning Corporation) was used as the substrate 100.

After forming the photoresist (not shown) on the glass substrate using the first photolithography process Ti and Au napylyaetsya with a total thickness of 50 nm by electron beam deposition, and then patterning method, inverse lithography, and through this to get the first electrode 201 shutter and the second electrode 202 of the gate.

Then a layer of SiO2that will become the insulating layer 300 shutter, which is common to the first transistor TFT and the second transistor TFT is formed (gas deposition: Ar, deposition pressures: 0.1 PA, the applied electric power: 400 W, film thickness: 100 nm) on the entire surface by the method of radio-frequency magnetron sputtering. After forming the photoresist (not shown) formed on this film by a second photolithography process on the insulating layer 300 shutter is applied to the image by etching, and the upper parts of the areas of the electrodes 201 and 202 of the gate is obtained a contact hole (not shown).

Then, the film 400 made of amorphous IGZO is formed (gas deposition: O2(3,3 volume%) + Ar, pressure deposition: 0,53 PA, applied electric power: 300 W) as the channel layer 400 by the method of radio-frequency magnetron sputtering. The film, whose thickness is 30 nm, is formed on both plots correspond to their channel layers of the first and second transistors TFT. During deposition by sputtering technique, the temperature of the substrate is not specifically regulated.

After forming the photoresist (not shown) through a third photolithography process channel layer 400 is subjected to etching and get the first channel layer 401 and the second channel layer 402.

Then only the near vicinity of the second channel layer 402 locally (selective/intensive) heated by a focused laser beam.

Finally, after forming the photoresist (not shown) through a fourth photolithography process Ti and Au again napylyaetsya for the formation of a film, the thickness of which a total of 100 nm by electron beam deposition. Then the first electrode 501 of the flow, the first electrode 601 source, the second electrode 502 drain and the second electrode 602 source formed by the method of inverse lithography. At the same time, the first electrode 501 drain connected with the first electrode 201 of the gate by forming an interlayer wired connection (not shown) through the above-mentioned contact hole.

It should be noted that the first electrode 601 source and the second electrode 502 drain are formed as a single unit.

In accordance with the above description turns the inverter with saturated load mode enrichment/enrichment, in which the first electrode 501 of the flow rassm trivets as a point of supply voltage and the second electrode 602 source is considered as a grounding point. The photolithography processes are performed five times.

In order to evaluate the dynamic characteristics of the inverter with saturated load mode enrichment/enrichment manufactured through the above-described procedure was performed following circuit simulation. Thus, it was made of circuit modeling of the 5-stage ring oscillator, which consists of an inverter with saturated load mode enrichment/enrichment, characterized in that the transistor TFT that has a width of W=40 μm in the sample 2, is configured as a load transistor TFT, and the transistor TFT that has a width of W=800 μm in the sample 1, is set as the control transistor TFT. The output waveform shown in Fig. 5-stage ring oscillator was implemented oscillations with a frequency of 68 kHz at a voltage of external power supply +10 C. the delay Time for each cascade amounted to 1.48 ISS, which is 70 percent more in comparison with a variant of embodiment 4. The amplitude was 6.3, and the maximum value of the output voltage was +8.3 V, which is approximately 1.7 To less than the source voltage +10 C. Thus, compared to the inverter with saturated load mode enrichment/enrichment manufactured in this comparative example 4-2, the inverter is operating in the mode of enrichment/is badania in a variant of embodiment 4, operates at higher speeds with greater amplitude than the inverter with saturated load mode enrichment/enrichment manufactured in this comparative example 4-2. Therefore, in accordance with the method of manufacture in a variant of embodiment 4 can be expected can be obtained inverter, much better than in comparative example 4-2.

<a Variant of embodiment 5>

The inverter consisting of an oxide of transistors TFT manufactured in variants of the embodiment 1-4, can be applied to any device in a digital circuit. For example, it can be used in the schema "NO," scheme "NOT-OR", the ring oscillator, the clock inverter, trigger circuit, shift register, static random access memory (SRAM), ROM (ROM; ROM type "NOT-OR" and a permanent storage device (ROM; ROM) type "NO".

The present invention can also be applied to the production of not only digital circuits, but also analog circuits, deliberately using transistors TFT having a different threshold voltage. For example, the present invention can be applied to the input stage of the differential amplifier.

In addition, the present invention can be applied to any scheme that uses the above-mentioned circuit device, including the surrounding in the inverter. For example, the present invention can be applied to the liquid crystal display with active matrix and tag radio frequency identification (RFID).

Although the present invention has been described with reference to illustrative options embodiments, it should be understood that the invention is not limited to the disclosed illustrative variant embodiment. The volume of the following claims should receive the broadest interpretation to encompass all such modifications and equivalent structures and functions.

This application claims the priority of patent application of Japan No. 2007-133039, filed may 18, 2007, which is hereby incorporated by reference herein in its entirety.

1. A method of manufacturing the inverter is operating in the mode of enrichment/depletion (E/D), with many thin-film transistors on the same substrate, the channel layers of the above-mentioned transistors are composed of an oxide semiconductor containing at least one element selected from In, Ga and Zn, the method comprises the steps are:
forming the first transistor and the second transistor, the thickness of the channel layers of the first and second transistors is mutually different; and applying heat treatment to at least one of the channel layers of the first and second transistors.

2. The method according to claim 1, in which at the stage of application of the term is processing heat treatment is performed through the application of a larger amount of heat to any one of the channel layers of the first transistor and the second transistor.

3. The method according to claim 1, wherein the step of applying heat treatment includes a step in which locally heats a partial region of the channel layer through the contact heating or irradiation with electromagnetic waves.

4. The method according to claim 1, wherein the inverter has at least one kind of structure:
structure in which a constituent material of the source electrode of the first transistor and a constituent material of the source electrode of the second transistor are mutually different,
structure in which a constituent material of the drain electrode of the first transistor and a constituent material of the drain electrode of the second transistor are mutually different, and
structure in which a constituent material of the gate electrode of the first transistor and a constituent material of the gate electrode of the second transistor are mutually different, and
the step of applying heat treatment includes a step in which heat channel layer by irradiating electromagnetic waves.

5. The method according to claim 4, in which the inverter has at least one kind of structure:
structure in which a property of the constituent material of the source electrode of the first transistor and the property of the constituent material of the source electrode of the second transistor are mutually different, the structure in which property constituting material e is ectrode drain of the first transistor and the property of the constituent material of the drain electrode of the second transistor are mutually different, and the patterns in which the property of the constituent material of the gate electrode of the first transistor and the property of the constituent material of the gate electrode of the second transistor are mutually different, and the property is at least one property selected from the resistivity, specific heat and coefficient of absorption.

6. The method according to claim 1, additionally containing a stage on which to apply etching to the channel layer to make the thickness of the channel layers of the first and second transistors are different.

7. The method according to claim 1, in which, in order to make the thickness of the channel layers of the first and second transistors are different, the number of times or run-time stage of deposition of the channel layer of the first transistor is different from the number of times of execution time or stage of deposition of the channel layer of the second transistor.

8. A method of manufacturing the inverter is operating in the mode of enrichment/depletion (E/D), with many thin-film transistors on the same substrate, the channel layers of the above-mentioned transistors are composed of an oxide semiconductor containing at least one element selected from In, Ga and Zn, the method comprises the steps are:
form the total deposited film, acting as a channel layer of the first transistor and the channel layer of the second transit the RA; and
performing heat treatment by application of a larger amount of heat to any one of the channel layers of the first transistor and the second transistor.

9. The method of claim 8 in which the step of performing the heat treatment includes a step in which locally heats a partial region of the channel layer through the contact heating or irradiation with electromagnetic waves.

10. The method according to claim 8, in which the inverter has at least one kind of structure:
structure in which a constituent material of the source electrode of the first transistor and a constituent material of the source electrode of the second transistor are mutually different,
structure in which a constituent material of the drain electrode of the first transistor and a constituent material of the drain electrode of the second transistor are mutually different, and
structure in which a constituent material of the gate electrode of the first transistor and a constituent material of the gate electrode of the second transistor are mutually different, and
the step of the heat treatment includes a step in which the heated channel layer by irradiating electromagnetic waves.

11. The method according to claim 10, in which the inverter has at least one kind of structure:
structure in which a property of the constituent material of the source electrode of the first Tr is sistor and the property of the constituent material of the source electrode of the second transistor are mutually different, structure in which a property of the constituent material of the drain electrode of the first transistor and the property of the constituent material of the drain electrode of the second transistor are mutually different, and a structure in which a property of the constituent material of the gate electrode of the first transistor and the property of the constituent material of the gate electrode of the second transistor are mutually different, and the property is at least one property selected from the resistivity, specific heat and coefficient of absorption.

12. The inverter, in which among the many oxide semiconductor thin film transistors, which are formed on the same substrate and each of which contains at least one element selected from In, Ga and Zn, the thickness of the channel layers of at least two transistors is mutually different, and the threshold voltage of the two transistors are mutually different.

13. The inverter indicated in paragraph 12, in which the inverter is operating, if the voltage of the power source, which satisfies such a condition that the difference between the threshold voltages of the two transistors is 70% or more and 200% or less of the voltage of the power source.



 

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