Hybrid integrated microwave circuit

FIELD: electricity.

SUBSTANCE: hybrid integrated microwave circuit includes dielectric substrate on the front side of which there located is topological metallisation pattern, and on rear side - screen earthing metallisation, at least one metallised mounting platform connected to screen earthing metallisation, at least one transistor, at least two capacitors on both sides of transistor. At that, at least one of the transistor outputs is electrically connected to upper coatings of capacitors, at least two other outputs are electrically connected to topological metallisation pattern, lower coatings of capacitors are electrically connected to metallised mounting platform and through it to screen earthing metallisation. Transistor with outputs, two capacitors and electric connections of one of transistor outputs to upper coatings of capacitors are made in the form of at least one crystal of monolithic integrated circuit, which is located on one metallised mounting platform. At that, both capacitors are film-type, upper coatings of capacitors, outputs of transistor and electric connections of one of transistor outputs with upper coatings of capacitors are provided in one metallisation layer of crystal of monolithic integrated circuit. At that, in crystal of monolithic integrated circuit immediately under lower coatings of capacitors there made are through metallised holes for electric connection of lower coatings of capacitors with metallised mounting platform.

EFFECT: improving electrical and mass and dimensions characteristics, improving reliability, reducing labour input of manufacturing process.

6 cl, 3 dwg, 3 ex

 

The invention relates to electronic engineering microwave, namely, hybrid integrated circuits, microwave range, and can be used in solid-state microwave modules for various purposes.

Known hybrid integrated circuit VHF range containing dielectric charge with the topological pattern of metallization on the front side and the display ground metallization on the back and vertical metallized holes, semiconductor crystals, while the dielectric substrate is upside down on a metal heat sink base and connected with it [1].

In this scheme, with the aim of improving the electrical and mass-dimensional characteristics in the Board performed a stepped recess with a metallic bottom, in which the above metallized holes are semiconductor crystals, the distance between the semiconductor crystals is not more than 0.1 mm, and the distance between the planes of the front surface of semiconductor crystals and slice stepped recess is not more than 0.02 mm

Location semiconductor crystals in a stepped recess and the electrical connection pads (pins) of a semiconductor crystals by means of metallized holes have been made to improve heat dissipation and reduce the length of electrical connections is thereby reduce the parasitic inductance and capacitance of these compounds and as a consequence, to increase the electrical and physical specifications.

However, this hybrid integrated circuit VHF range is:

- low reliability due to the presence of a large number of welded and soldered electrical connections,

- high complexity of manufacturing, is primarily due to the complexity of making the step notch.

Known hybrid integrated circuit VHF range containing dielectric substrate on the front side of which is a topological pattern of metallization and on the back - screen grounding metallization, condensers, which are plated holes, while the bottom plates of the capacitors are connected through plated holes with screen grounding metallization. On the front side of the dielectric substrate is made recess (metallized landing pad), which is a crystal of a semiconductor device in one plane with the face of the dielectric substrate and connected with him binder, pads (pins) of a crystal of a semiconductor device is attached to the upper plates of the capacitors and the topological metallization pattern. When the dielectric substrate is upside down on a metal t is pelotudeses the base and connected by a connecting electrical and heat-conductive substance.

In this scheme with the aim of improving heat dissipation from the chip of the semiconductor device and improve the reliability of the hybrid integrated circuit plated holes made deaf from the front side of the dielectric substrate thickness of the bottom is not more than 0.5 mm When the metallization of the bottom of the mentioned holes serves as the bottom plates of the capacitors, and the top plates of capacitors made in the composition of the topological pattern of metallization, the thickness of the substrate between the holes and the sides of the recesses is not more than 1 mm [2 - prototype].

This design is a hybrid integrated circuit allowed:

to use the metallization of the bottom metallized blind holes as the bottom plates of capacitors

residual thickness of the dielectric substrate in metallized blind holes as a dielectric layer of the capacitors

- to form the top plates of capacitors in the structure of the topological pattern of metallization.

This allowed for comparison with the first analogue to exclude the portion of the soldered electrical connections from the design of hybrid integrated circuits and, consequently, to increase its reliability.

However, on the other hand the execution of the upper plates of the capacitors in the structure of the topological pattern of metallization makes it difficult to obtain a thin SL is I dielectric capacitors, thickness less than 0.05 mm, which determines its large geometrical dimensions and thus low specific capacity and, consequently, low weight and size characteristics.

In addition, this design is a hybrid integrated circuit has a high complexity of manufacturing, due to the necessary and complicated and time-consuming process operations when performing recesses on both sides of the dielectric substrate.

The technical result of the invention is to improve electric and mass-dimensional characteristics, improving reliability, reducing the complexity of manufacture.

The specified technical result is achieved by the claimed hybrid integrated circuit VHF range, containing

- dielectric substrate on the front side of which is a topological pattern of metallization, and on the reverse side is a display of the grounding metallization, while the dielectric substrate is upside down on a metal heat sink base and connected by electrical and heat-conductive substance,

at least one metallized landing, electrically connected with the display of the grounding metallization,

at least one transistor with the conclusions

at least two capacitor located krasnyh sides of the transistor

- in this case, at least one of the terminals of the transistor is electrically connected to the top plates of the capacitors, at least two other conclusions are electrically connected to the topological metallization pattern,

- the bottom plates of capacitors electrically connected to metallized landing and through it with the screen grounding metallization.

In the proposed integrated circuit

the transistor with the conclusions, two of the capacitor and electrically connect one of the terminals of the transistor with the top plates of capacitors made in the form of at least one crystal monolithic integrated circuits, each of which is metallized on one landing, while

capacitors made film,

the upper plates of capacitors, terminals of the transistor and electrically connect one of the terminals of the transistor with the top plates of the capacitors are made in one layer of metallization crystal monolithic integrated circuits,

in the crystal monolithic integrated circuit, directly under the bottom plates of the capacitors are through plated holes for electrical connection of the bottom plates of capacitors with metallized landing.

The transistor crystal monolithic integrated Hemi can be performed, for example, in the form of a field-effect transistor with a barrier of a Schottky, with at least one source field-effect transistor with a barrier of a Schottky electrically connected to the top plates of capacitors, and at least one gate and one stock with the topological metallization pattern.

Metallized landing pad can be performed on the front side of the dielectric substrate in the composition of the topological pattern of metallization or recess made on its front side, and its depth provides the location of the front sides of the crystal monolithic integrated circuit and the substrate in the same plane, and the distance from the chip monolithic integrated circuit to the edges of the cavity in the direction of connection of the other terminals of the transistor crystal monolithic integrated circuit with a topological metallization pattern is equal to or less than 0.15 mm

In the metallized landing and the dielectric substrate under the transistor crystal monolithic integrated circuit may be performed, at least one through-plated hole filled with a metal or metals.

Metal heat sink base can be made with the tab, and in the dielectric substrate coaxially with the guide is a through hole for its location. the ri on the above ledge is metallized landing pad, the height of the protrusion provides the location of the front sides of the crystal monolithic integrated circuit and the substrate in the same plane. The distance from the chip monolithic integrated circuit in a direction of connection of the other terminals of the transistor crystal monolithic integrated circuit with a topological metallization pattern is equal to or less than 0.2 mm

The stated set of essential features of a hybrid integrated circuit VHF range, namely:

execution of the transistor with the conclusions of the capacitors and the electrical connections of one of the terminals of the transistor with the top plates of the capacitors in the form of a crystal monolithic integrated circuit, and the upper plates of the capacitors, transistor pin and the electrical connections of one of the terminals of the transistor with the top plates of the capacitors in a single layer metallization crystal monolithic integrated circuits, as well as - through-plated holes in the crystal monolithic integrated circuit directly under the bottom plates of capacitors for electrical connection of the bottom plates of capacitors with metallized landing will provide a reduction in the lengths of the respective electrical connections and, as a consequence, the improvement of electrical characteristics;

run capacitors plait the full-time will provide the dielectric layer capacitors of a thickness of less than 0.001 mm, and thus provides increased capacity and size reduction and, as a consequence, increase of electric and mass-dimensional characteristics.

It should be emphasized that the dimensions of the crystal monolithic integrated circuit is almost equal to the dimensions of the transistor.

Moreover, thanks to the performance of transistors and capacitors in a single technological cycle in the composition of the crystal monolithic integrated circuit provides a significant reduction in the complexity of the manufacturing process.

Moreover, due to the further reduction in comparison with the prototype of the number of welded electrical connections provides increased reliability.

Proposed special cases of the execution of metallized landing, provide the following:

a) on the front side of the dielectric substrate in the composition of the topological pattern of metallization - reducing the complexity of manufacturing,

b) in the recess made on its front side with the specified process parameters - improved electrical characteristics thanks,

first, to reduce the thickness of the dielectric substrate under the crystal monolithic integrated circuit and thereby improve heat dissipation from the chip monolithic integrated circuit,

secondly, to reduce the length of the electrical connections of the other terminals of the transistor crystal monolithic integrated circuit with topological rice is com metallization.

The distance from the chip monolithic integrated circuit to the edges of the cavity in the direction of connection of the other terminals of the transistor crystal monolithic integrated circuit with a topological metallization pattern more than 0.15 mm is undesirable, as it leads to an increase in the length of the above compounds, and thus to the increase of the parasitic inductances and capacitances and, as a consequence, the decrease of the electric characteristics.

Performing in the metallized landing and the dielectric substrate under the transistor crystal monolithic integrated circuit, at least one metallized through holes filled with the metal or metals, due to the improved heat dissipation from the chip monolithic integrated circuit provides improved electrical characteristics.

Location metallized landing on the ledge metal heat sink base, located in a through hole of the dielectric substrate, provides improved heat dissipation from the chip monolithic integrated circuit and, consequently, improving the electrical characteristics.

The distance from the chip monolithic integrated circuit in a direction of connection of the other terminals of the transistor crystal monolithic integrated circuit with the topological pattern of the met is lisali more than 0.2 mm is undesirable, as it leads to an increase in the length of the indicated compounds, and thus to the increase of the parasitic inductances and capacitances and, as a consequence, the decrease of the electric characteristics.

So, the proposed set of essential features of the claimed hybrid integrated circuit VHF range will allow the full implementation of the technical result, namely improving the electrical and mass-dimensional characteristics, improving reliability, reducing the complexity of manufacture.

The invention is illustrated by drawings.

On 1 shows a section view and a top view of a fragment of the requested hybrid integrated circuit VHF range, containing one crystal monolithic integrated circuit (metallized landing pad is made on the front side of the dielectric substrate in the composition of the topological pattern of metallization), where:

dielectric substrate - 1,

topological figure metallization - 2 on its front side,

- the display of the grounding metallization 3 on the reverse side,

metal heat sink base - 4,

- electricity and heat-conductive substance 5,

- metallized landing pad - 6,

-electric connection - 7 metallized landing screen with a grounding metallization,

- transistor - 8,

two condense the ora - 9 and 10, respectively,

one of the conclusions of the transistor 11,

- the electrical connection of one of the terminals of the transistor 12 with the upper plates of the capacitors

the upper plates of capacitors - 13,

two other output transistor 14 and 15, respectively,

- the electrical connections of the other two terminals of the transistor 16 and 17 respectively with the topological metallization pattern,

- the bottom plates of capacitors - 18,

- the electrical connection of the bottom plates of capacitors - 19 with metallized landing

- crystal monolithic integrated circuits 20,

- layer metallization crystal monolithic integrated circuits 21,

- through-plated holes 22 into the crystal monolithic integrated circuits.

Figure 2 is given a special case execution, when metallized landing pad is made in the recess on the front side of the dielectric substrate, where:

the recess 23 on the front side of the dielectric substrate,

- at least one through-plated hole - 24 under the transistor crystal monolithic integrated circuits,

- metal or metal - 25 through metallized holes.

Figure 3 is a special case of the execution, when metallized landing pad is made on the metal ledge teplota asego Foundation, where:

the ledge 26 of the metal heat sink base.

- through hole - 27 in the dielectric substrate,

Examples of specific performance of the claimed hybrid integrated circuit VHF range.

Example 1 - including the special case, when the transistor crystal monolithic integrated circuit made in the form of field-effect transistor with a barrier of a Schottky, and metallized landing pad is made on the front side of the dielectric substrate in the composition of the topological pattern of metallization.

Before implementing the crystal monolithic integrated circuit 20 in a single technological cycle through thin-film technologies (crystal size of 0.5×0.5 to×0.1 mm) on politology substrate of gallium arsenide active layers of n-type conductivity, thickness of 0.15 μm and a concentration of 5×1017-5×1018cm-3respectively, containing:

field effect transistor with a barrier of a Schottky, CCGT 8, pins 11, 14 and 15, respectively, the source-gate-drain metallization structure its findings titanium-gold thickness 0,0007 0,0001 and mm, respectively,

two capacitor 9 and 10, with a capacity of, for example, from 2-5 pF, are, for example, from opposite sides of a field-effect transistor with a barrier of a Schottky 8,

- electrical connection - 12 source 11 field-effect transistor with a barrier of a Schottky top what vkladkami 13 capacitors

thus

capacitors made film, the lower and upper plates made by metallization structure titanium-gold 0,0007 0,0001 and mm, respectively, the dielectric layer of the capacitor of silicon dioxide with a thickness of 0.005 mm

the upper plates of capacitors 13, the conclusions of the source-gate-drain 11, 14 and 15, respectively, the field-effect transistor with a barrier of a Schottky 8, the electrical connections 12 source 11 with the upper plates 13 of the capacitors 9 and 10 are made in one metallization layer 21 of the monolithic integrated circuit 20.

On the dielectric substrate 1, for example paligorova by thin-film technology has been the face side is a topological pattern of metallization 2, on the reverse side is a display of the grounding metallization 3 same structure of chromium-copper-Nickel-gold (Cr-Cu-Ni-Au), with the dielectric substrate is a flip side together with the display of the grounding metallization 3 on a metal heat sink base 4 made of pseudoplane MD-50 (50% copper (Cu) and 50% molybdenum (Mo)and connected with it, for example, solder gold silicon eutectic composition 5.

On the front side of the dielectric substrate 1 is made in the composition of the topological pattern of metallization 2 metallized landing pad 6, for example, the structure of chrome-copper-Nickel-gold (Cr-Cu-Ni-Au), a similar article is ucture topological pattern of metallization 2.

While it is electrically connected 7, for example, through metallic hole 24 is filled, for example, solder gold-silicon eutectic composition with 25 screen grounding metallization 3.

On metallized landing 6 is located above the crystal monolithic integrated circuit 20 and is connected to it by solder tin-gold eutectic composition.

While the bottom plates 18 of the capacitors 9 and 10 19 electrically connected through the plated through holes 22 in the crystal monolithic integrated circuit 20 with metallized landing 6 and through her on-screen grounding metallization 3.

Example 2

Hybrid integrated circuit VHF range is accomplished similarly to that described in example 1 is a special case, when metallized landing pad is made in the recess 23 on the front side of the dielectric substrate 1 and in the metallized landing 6 and the dielectric substrate 1 under the transistor 8 crystal monolithic integrated circuit 20 is a through metallic hole 24 is filled with solder, gold-silicon eutectic composition of 25.

Example 3

Hybrid integrated circuit VHF range is accomplished similarly to that described in example 1 is a special case, when metallized landing pad races is alogena on the ledge 26 of the metallic heat sink base, located in a through hole 27 made in the dielectric substrate.

On prepared samples of the hybrid integrated circuit of the microwave range have been measured electrical characteristics, namely the gain in power.

As shown by measurements, the gain in power is increased by about 7-8 percent at a frequency of 10 GHz.

Thus, the claimed hybrid integrated circuit VHF range will allow for a comparison with the prototype

first, to improve the electrical and physical specifications, with dimensions reduced by 60-65%,

secondly, to reduce the complexity of manufacturing approximately 1.2 times.

This hybrid integrated circuit can be widely used, including in balanced amplifiers microwave.

Sources of information

1. RF patent №2025822, IPC H01L 21/00, priority 19.03.91, publ. 30.12.94, bull. No. 24.

2. RF patent №2227345, IPC H01L 27/13, H05K 1/16, priority 26.02.02, publ. 20.04.04, bull. No. 11 - the prototype.

1. Hybrid integrated circuit VHF range containing dielectric substrate on the front side of which is a topological pattern of metallization, and on the reverse side is a display of the grounding metallization, while the dielectric substrate is upside down on a metal heat sink base and become United with him in power and those who boprovodam substance, at least one metallized landing, electrically connected with the display of the grounding metallization, at least one transistor with the conclusions of the at least two capacitor from different sides of the transistor, in this case, at least one of the terminals of the transistor is electrically connected to the top plates of the capacitors, at least two other of its output electrically connected to the topological metallization pattern, the bottom plates of capacitors electrically connected to metallized landing and through it with the screen grounding metallization, wherein the transistor with the conclusions, two of the capacitor and the electrical connection of one from the findings of the transistor with the top plates of capacitors made in the form of at least one crystal monolithic integrated circuits, each of which is metallized on one landing, both of the capacitor is made of a film, the upper plates of capacitors, terminals of the transistor and electrically connect one of the terminals of the transistor with the top plates of the capacitors are made in one layer of metallization crystal monolithic integrated circuit in a chip of a monolithic integrated circuit directly under the bottom plates of the capacitors are made is through-plated holes for electrical connection of the bottom plates of capacitors with metallized landing.

2. Hybrid integrated circuit of the microwave range according to claim 1, characterized in that the transistor crystal monolithic integrated circuit made in the form of field-effect transistor with a barrier of a Schottky, with at least one source field-effect transistor with a barrier of a Schottky is electrically connected to the top plates of the capacitors, at least one bolt and one stock with the topological metallization pattern.

3. Hybrid integrated circuit of the microwave range according to any one of claims 1 and 2, characterized in that the metallized landing pad is made on the front side of the dielectric substrate in the composition of the topological pattern of metallization.

4. Hybrid integrated circuit of the microwave range according to any one of claims 1 and 2, characterized in that the metallized landing pad is made in the recess on the front side of the dielectric substrate, and its depth provides the location of the front sides of the crystal monolithic integrated circuit and the substrate in the same plane, and the distance from the chip monolithic integrated circuit to the edges of the cavity in the direction of connection of the other terminals of the transistor crystal monolithic integrated circuit with a topological metallization pattern is equal to or less than 0.15 mm

5. Hybrid integrated circuit of the microwave range according to any one of claims 1 and 2, characterized those who, in metallized landing and the dielectric substrate under the transistor crystal monolithic integrated circuits made at least one pass-through metallic hole filled with a metal or metals.

6. Hybrid integrated circuit of the microwave range according to any one of claims 1 and 2, characterized in that the metal heat sink base is made with the tab, and in the dielectric substrate coaxially with the guide is a through hole for its location, on the above ledge is metallized landing pad, and the height of the protrusion provides the location of the front sides of the crystal monolithic integrated circuit and the substrate in the same plane, the distance from the chip monolithic integrated circuit in a direction of connection of the other terminals of the transistor crystal monolithic integrated circuit with a topological metallization pattern to the edges of the said openings is equal to or less than 0.2 mm



 

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