Method for blur compensation of moving object image and device for implementation of method

FIELD: physics, computation equipment.

SUBSTANCE: the invention claims method of image blur compensation involving: calculation of difference between measured image pixel brightness and brightness assessment obtained earlier on the basis of previous frame sequence; movement detection by comparison of obtained difference to threshold value; defining of movement direction for each pixel; combination of adjoining pixels with the same movement direction in a single object; outlining contours of moving objects by adding their initial B(k) and gradient ▿(B(k)) of images; and generation of output image where k1, k2 are weight factors. Device of image blur compensation includes: image sensor, controller, mode movement detection module, object detection module, correction module, first RAM device, second RAM device, third RAM device, counter, first comparator, second comparator, first multiplexor, second multiplexor, third multiplexor, fourth multiplexor, fifth multiplexor, sixth multiplexor, seventh multiplexor, first demultiplexor, second demultiplexor.

EFFECT: blur compensation for moving object image in real-time mode.

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The invention relates to computer technology and can be used to improve the clarity of the image coming from the image sensor, the motion of the image sensor or in the body frame of the moving objects.

The known method of eliminating image blur due to the motion of the objects in the digital image (Tull D.L. Preventing blur caused by motion of the subject in a digital image, 2002, U.S. patent No. 6441848). The method includes obtaining image matrix of photosensitive light receiver (MPPI) for a given accumulation time; calculating the value of a variable, proportional to the intensity of the radiation flux for each pixel; calculating a second derivative of a specified variable for each pixel; comparing the value of the second derivative of the specified variable with a threshold value, which corresponds to the detected movement; the calculation of the accumulation time for each pixel as a percentage of the current accumulation time; changing the accumulation time for each pixel according to the calculated percentage value.

The disadvantages of this method are:

- the presence of distortions in the image caused by variations of the brightness at the boundaries of regions with different dwell time;

its inapplicability to the receivers of the image on the again of charge-coupled devices (CCD), for which it is impossible to change the accumulation time of each pixel separately.

A device that implements the function of eliminating image blur due to the motion of the objects in the digital image (Tull D.L. Preventing blur caused by motion of the subject in a digital image, 2002, U.S. patent No. 6441848)containing a matrix of photosensitive detectors, each elementary image sensor (EFS) which includes a diagram of the detection; a focusing lens; a diagram of the memory connected to the matrix photosensitive light receiver, which stores the value of the accumulation time for each elementary image sensor.

The disadvantages of this device are:

- high complexity of its technological performance, due to the need of embedding in each pixel circuit of the detection;

- reduced fill factor of the pixel (the ratio of the photosensitive pixel to its total area) due to the embedding in each pixel circuit of the detection, which reduces the sensitivity of the device and increasing the level of geometric noise and noise fixed wiring.

Closest to the invention is a method of compensating image blur caused by the movement or feeding of the elementary image sensor, with a simultaneous expansion is the group dynamic range by synthesizing the image frames (Liu et. all Motion/saturation detection system and method for synthesizing high dynamic range motion blur free images from multiple captures, 2006, U.S. patent No. 7061524). According to the method, calculating the difference between the measured brightness of the pixels of the image and a previously obtained its assessment based on the sequence of previous frames, detect motion by comparing the difference with a threshold value, in the absence of motion take the measurements of the brightness of the true image, if the movement of the measured intensity values are adjusted on the basis of the estimates.

The main disadvantage of this method is to process at least four shots to produce images with a sufficient degree of compensation of the blur, which imposes significant limitations on the speed of the device that implements the method, and in some cases due to the formation of modern video sensor image with large resolution leads to the impossibility of functioning of the device in real time.

Closest to the present invention is a device to compensate for image blur caused by the movement or saturation EF (Liu et. all Motion/saturation detection system and method for synthesizing high dynamic range motion blur free images from multiple captures, 2006, U.S. patent No. 7061524). The device comprises: an image sensor, each EF which contains media is TBA motion detection/saturation between the previous frame and the current frame; processing unit, determining whether to accept for each EF the sample image recorded in the current frame; block assessment brightness within the global exposure time, and the unit for determining the difference between the measured brightness received during the current frame, and evaluation of brightness is generated for the previous frame, for each EF; unit comparing the calculated difference with a threshold value for each EF; block modification assessment brightness for each EF; forming unit of the image output on the basis of the final evaluation of brightness for each EF.

The disadvantage of this device is the low fill factor of the pixel (not more than 10%), which significantly impairs the sensitivity of the image sensor, the high complexity of its technological performance and high structural complexity associated with the need to be embedded in each pixel circuit of the motion detection.

An object of the invention is to compensate the blurring of moving objects in real-time for MPPI of any type (CCD, based on semiconductor complementary pairs of metal-oxide-semiconductor (CMOS)) with simultaneous reduction of the technological performance of the device and reducing its structural complexity.

The task is solved in that in the known method the comp is ncacii blur caused by the movement, including the definition of the interframe difference luminance of an image motion detection for each pixel in the image, brightness adjustment only moving pixels, according to the invention inserted a definition of the direction of motion for each pixel by processing adjacent frames sliding window 3×3 items and analysis of the total values of the elements of the frame-to-frame differences, the Association of moving in one direction adjacent pixels in the object based on the analysis of the distance between two pixels with the same direction of movement, underline the contours of moving objects by adding the original image of a moving object with its gradient image.

The technical problem is solved in that the device containing the image sensor, put the controller module motion detection mode, the determining module of interest, the correction module, the first RAM, the second RAM, the third RAM, counter, element, OR, the first comparator, second comparator, the first constant, the second constant, the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer, a sixth multiplexer, the seventh multiplexer, the first demultiplexer, the second demultiplexer, the third constant.

The invention can be used to compensate for the size of the employment of the image of moving objects in real time in different video sensor and vision systems, made on the basis of the solid-state MPPI different types.

The invention is illustrated by drawings, where figure 1 shows the algorithm of the method of compensation of the image blur, figure 2 codes the direction of movement of a pixel in vosmiletnej surroundings, figure 3 is a structural diagram of a device for the compensation of the image blur moving objects figure 4 - block diagram of the controller figure 5 - block diagram of the module motion detection, 6 is a structural diagram of a register block figure 7 - structural diagram of the summing block, Fig - structural diagram of the module object definitions, figure 9 - block diagram of the correction module, figure 10 - block diagram of the module emphasize the contours, figure 11 - value constants register block.

The process of compensating the image blur (figure 1) consists of several stages: read image, the selection in the image of the moving pixels based on the analysis of interframe difference, the determination of the direction of movement of each pixel, the Association of moving in one direction adjacent pixels in the object, underline the contours of moving objects to compensate for blurring of the image by adding their source and gradient images, the output image.

The motion of each pixel relative to the current k-th ka the RA is determined by the principle of frame-to-frame subtraction: the difference between the brightness of static pixels in adjacent frames is 0 (at constant illumination). The calculation is performed for vosmiletnej neighborhood of each pixel, each of the eight possible directions of movement is assigned a particular code.

To determine the number, direction of motion r (figure 2) of each pixel (x,y) frame is processed sliding window of size 3×3 in the following way: for each pixel (x,y) of the current frame is composed of the brightness matrix B(k) adjacent pixels by 8 lines:

The matrix elements In(k)whose indices are equal to 0, (X+1) or (Y+1), is taken equal to 0, where X, Y are the dimensions of the frame horizontally and vertically, respectively.

Next, the matrix B(k) is converted to a matrix In*(k) by subtracting from the brightness of adjacent pixels brightness of the Central pixel:

This transformation allows to take into account possible changes in the ambient light of the scene with the same arrangement of objects in the current frame relative to the previous frame.

Similarly to the processing of the previous (k-1)-th frame is composed matrix In*(k-1):

The result of the subtraction matrix B*(k-1) from the matrix In*(k) allows to judge about whether the Central pixel is fixed on the adjacent frames, if equal to zero, the Central pixel of the output matrix In** (k/k-1), i.e. satisfies the following condition:

If the Central pixel of the output matrix In**(k/k-1) is not equal to 0, we conclude that the motion of the pixel.

Next is the determination of the direction of movement of each pixel. To do this, the matrix B*(k-1) form 8 matrix shifted by 1 pixel on each of the 8 directions (missing rows and/or columns filled with zeros). Matrix determine the movement of the Central pixel in the current frame relative to the previous set in the General form as follows:

For the formation of 8 the resulting matrix of displacements for each of the 8 directions you must subtract each matrix determine the direction of the matrix In*(k). The resulting matrix of brightness of the image, calculates the displacement of the pixel in the current frame are in the General form as follows:

For the direction of the pixel is assumed that the direction for which the sum of the changes in brightness (sum of all elements of the resulting matrices) module is minimal.

where sup_ind(*) is a function value which is the value of the upper index of the matrix Inr(k/k-1).

Then determine what their moving objects. For this purpose it is necessary to find the neighboring pixels with the same direction of movement, the search which is carried out in accordance with formulas (8)-(13)

Neighboring pixels with the same direction are grouped into objects in accordance with the formula:

where ξ,ς - coordinates of the pixel; Np+1 is the minimum number of points in the object.

Under that object, EDis a set of non-background pixels in the image with the direction D, such that for each point there will be at least one neighboring point located at a distance of 1 pixel, and the number of such points in the object to exceed the threshold value Np.

After this is implemented correction of the brightness of moving objects by underlining their contours (combining the original image with gradient image). The output values of the pixel intensity is calculated as follows:

where ▿(bx,y(k)) is the gradient image, such that

The brightness values of the static areas of the image remain the tsya unchanged.

Device for compensation of the image blur (figure 3) contains the image sensor DI 10, the controller 1, the detection module movement MOD 2, the definition of the objects of MOO 3, the correction module MK 4, the first RAM 5, the second RAM 6, the third RAM 7, the counter 100, item, OR 101, the first comparator 102, the first multiplexer 51, the second multiplexer 52, the third multiplexer 53, the fourth multiplexer 54, the fifth multiplexer 55, the sixth multiplexer 57, the seventh multiplexer 59, the first demultiplexer 56, the second demultiplexer 58, and input CLK/3 is designed to supply pulsing signal in DI 10 and connected to the first input of the controller 1, group output DI 10 is connected to the first group the input of the controller 1, the second group output controller 1 is connected to the first group the inputs of the first multiplexer 51 and the third multiplexer 53, group output of the first multiplexer 51 is connected to the input of the first group RAM 5, the group of input-output of the first RAM 5 is connected to the input of the first group demultiplexer 56 and to group the output of the fifth multiplexer 55, the first group of the output of the demultiplexer 56 is connected to the fourth group to the input of the controller 1, the group of input-output of the second RAM 6 is connected to group the input of the second demultiplexer 58 and to group the output of the sixth multiplexer 57, and the third group the output of the controller is 1 connected to the system bus, the fourth group controller output 1 is connected to the first group to the entrance of the sixth multiplexer 57, the first group output controller 1 is connected to the first group to the input of the fifth multiplexer 55, the first output of the controller 1 is connected to the first input of the second multiplexer 52, the output of the second multiplexer 52 is connected to the input of the first RAM 5, the second output controller 1 is connected to the first input of the fourth multiplexer 54, the output of which is connected to the input of the second RAM 6, the second and the third group the inputs of the controller 1 are designed to supply constant (H-1) and (Y-1), respectively (where X, Y - the dimension of the image horizontally and vertically), the second input of the controller 1 is designed to supply the clock signal CLK and is connected with the second input MOD 2, the third input of the controller 1 is connected to the output of the first comparator 102, the first group whose input is connected to group the output of the meter 100 and the fifth group input MOD 2, for the second group the input of the first comparator 102 filed with the constant 0, the third output of the controller 1 is connected to the first input element OR 101, the first input MOD 2 is designed to supply the clock signal CLK/25, the first and second group inputs MOD 2 are for feed constant (X-3) and (Y-3), respectively, the third group input MOD 2 is connected to group the output of the second demultiplexer 58, the fourth the fifth group input MOD 2 is connected to the second group to the output of the first demultiplexer 56, the first group output MOD 2 is connected to the second group to the inputs of the first multiplexer 51 and the third multiplexer 53, the second group output MOD 2 is connected to the second group to the entrance of the seventh multiplexer 59, the third group output MOD 2 is connected to group input-output RAM 7 and the first group to the entrance of MOO 3, the first release of the MOD 2 is connected to the second input of the OR element 101, the second output MOD 2 is connected to the input of the seventh multiplexer 59, the third output MOD 2 is connected to the input of the third RAM 7, the second and the third group the inputs of MOO 3 are designed to supply constant (X-2) and (Y-2), respectively, the fourth group entrance of MOO 3 is connected to the first group output MK 4, the fifth group entrance of MOO 3 is connected to the fourth group output MK 4, the sixth group entrance of MOO 3 connected to group the output of the counter 100, the first, second and third inputs of MOO 3 are designed to supply clock signals CLKX, CLKX6, CLKY, respectively, the first group out of MOO 3 is connected to the first group to the entrance of the seventh multiplexer 59, group output of which is connected with the group entrance to the third RAM 7, the second group output LEAs 3 is connected to the first group to sign MK 4, the third group out of MOO 3 is connected to the second group input MK 4, the fourth group output MOO 3 is connected to the third group input MK 4, the output of MOO 3 is connected to the Tr is Teemu input element of the LIP 101 and to the third input of the MK 4, the fourth input of the OR element 101 is connected to the output of the MK 4, the second group output MK 4 is connected to the third group input of the first multiplexer 51, the third group output MK 4 is connected to the second group to the input of the fifth multiplexer 55, the fourth group entrance MK 4 is intended for filing threshold R, which determines the minimum number of pixels in the object, the fifth group entrance MK 4 is connected to the third group the output of the first demultiplexer 56, the first and second inputs MK 4 are used to supply a clock signal CLKW and CLKZ, respectively, to the second input of the second multiplexer 52 filed with the constant 0, group the output of counter 100 is connected to the fourth group input of the first multiplexer 51, group the input of the second multiplexer 52, the third group to the input of the third multiplexer 53, the fifth group to the input of the fourth multiplexer 54, the third group to the input of the fifth multiplexer 55 to the second group to the entrance of the sixth multiplexer 57, and the second group the inputs of the first demultiplexer 56 and the second demultiplexer 58, second, third, fourth inputs of the fourth multiplexer 54 is constant 0, the first multiplexer 51 provides a signal with his first group entry to your group output at "0" at its Thursday the mouth group the entrance, with his second group of input - when set to "1", from their third group of entry - when set to "3", the second multiplexer 52 provides a signal with his first group entry to your group output at "0" at its third group the entrance, with his second group of input - when set to "3", the third multiplexer 53 provides a signal with his first group entry to your group output at "0" at its third group the entrance, with his second group of input - when set to "1", the fourth multiplexer 54 provides a signal with his first group entry to your group output at "0" at its fifth group the entrance, with his second group of input - when set to "1", from their third group of entry - when set to "2", from their fourth group of input - when set to "3", the fifth multiplexer 55 provides a signal with his first group entry to your group output at "0" at its third group the entrance, with his second group of input - when set to "3", the sixth multiplexer 57 provides a signal with his first group entry to your group output at "0" at its second group, first demultiplexer 56 provides prohozhdenie the signal from your group log on to the first group output at "0" at its second group the entrance, when set to "1" - on his second group output, when the value "3" is on its third group output, the second demultiplexer 58 provides a signal from your group log on to your group output when set to "1" at its second group the entrance, the seventh multiplexer 59 provides a signal with his first group entry to your group output at "0" at its input, and the second group of input - when set to "1".

Controller 1 (figure 4) contains the first element OR 11, the second element OR 12, the first counter 13, the second counter 14, the third counter 15, the first comparator 16, the second comparator 17, the shaper address 18, the And gate 19, the buffer 110 and the demultiplexer 111, and the first input of the first counter 13 is the first input of the controller 1 and is intended to supply the clock signal CLK/3, the first group of the output of the first counter 13 is connected to the first group the inputs of the first comparator 16 and shaper address 18, group output of the shaper 18 is the second group output controller 1, the second group the input of the first comparator 16 is the second group of the input of the controller 1, the output of the first comparator 16 is connected to the second input of the first element OR 11, to the first input of the second counter 14 and to the first input element And 19, group the output of the second counter 14 is connected to second the mu group the input of the shaper addresses 18 and to the first group the input of the second comparator 17, the second group input of the comparator 17 is the third group controller input 1, the output of comparator 17 is connected to the second input element And 19, to the second input of the second OR element 12 and the first input of the first element OR 11, the third input of the first element OR 11, the first input of the second OR element 12 and the second input of the third counter 15 is connected to the third input of the controller 1, the first input of the third counter 15 is the second input of the controller 1 and is intended to supply the clock signal CLK, group output of the third counter 15 is connected to the second group of the input buffer 110 and the second group the input of the demultiplexer 111 the first group input buffer 110 is the first group controller input, group output buffer 110 is the first group output of the controller 1, the first group of the input of the demultiplexer 111 is the fourth group the input of the controller 1, the first group of the output of the demultiplexer 111 is the third group controller output 1, the second group the output of the demultiplexer 111 is the fourth group output controller 1, the high-order group output of the third counter 15 is the first output of controller 1, the output element, And 19 is the third output of the controller 1, the low-order group output of the third counter 15 is the second output of the controller 1.

Modulating the motion detection MOD 2 (figure 5) includes the first counter 21, the second counter 22, the third counter 23, the fourth counters 24, the first comparator 25, the second comparator 26, the first adder 27, the second adder 28, the first shaper address 29, item, OR 210, the And gate 211, the first register block 212, the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221, the first summing block 222, the second summing block 223 the third summing unit 223, a fourth summing block 225, the fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summation block 230, the schema defining at least 231, the third comparator 233, the fourth comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, eighth comparator 238, the ninth comparator 239, tenth comparator 240, the eleventh comparator 241, the encoder 242, the third adder 244, a fourth adder 245, the second shaper address 246, twelfth comparator 247, and the first input the first counter 21 is the first entry MODES 2 and is designed to provide pulsing signal with a frequency of CLK/25, the second input of the first counter 21, which is a reset input connected to the output element OR 210, the output of the first to the of narator 25 is connected to the second input of the OR element 210 and the first input of the second counter 22, group the output of the first counter 21 is connected to the first group input of the first comparator 25, the first group to the input of the first adder 27 and the first group to the input of the fourth adder 245, group the output of the second counter 22 is connected to the first group the input of the second comparator 26, the first group to the second input of the adder 28 and the first group to the third input of the adder 244, the second group the input of the first comparator 25 is the first group entry MODES 2 and is designed to supply a constant value (X-3), the second group the input of the second comparator 26 is the second group input MODES 2 and is designed to supply a constant value (Y-3) the output of the second comparator 26 is connected to the second input of the second counter 22, which is the reset input, and to the first input element OR 210, the input of the third counter 23, which is the second input MOD 2, is designed to supply the clock signal CLK, group output of the third counter 23 is connected to the second group to the first input of the adder 27, the output of the third counter 23 is connected to the fourth input of the counter 24, the group output of which is connected to the second group to the input of the second adder 28, the group output of the first adder 27 is connected to the first input of the first group of driver address 29, and group output the second adder 28 is connected to the second group is the first input of the first driver address 29, the output of the first driver address 29 is the first group output MODES 2, the first group of the first input register block 212 is the fourth group input MOD 2, the third group input MOD 2 is connected to the first group the inputs of the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221, the second group the inputs of the first register block 212, the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register unit 221 is connected to group the output of the fourth counter 24, the third group the inputs of the first register block 212, the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register unit 221 is connected to group the output of the third counter 23 the group o the species of the first register unit 212 connected to the first group of inputs of the first summing block 222, the second summing block 223, the third summing unit 224, a fourth summing block 225, the fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summation block 230, the group of outputs of the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register unit 221 is connected to the second group to the inputs of the first summing block 222, the second summing block 223 the third summing unit 224, a fourth summing block 225, the fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summation block 230, the group outputs of the first adder block 222, the second summing block 223, the third summing unit 224, a fourth summing block 225, the fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summing unit 230 are connected respectively to the first, second, third, fourth, fifth, sixth, seventh, eighth, the ninth unit definition mini is mind 231, and the first group to the third inputs of the comparator 233, the fourth comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, eighth comparator 238, ninth comparator 239 tenth of the comparator 240, the second group the inputs of which are connected to group the input schema definition of the minimum 231, group output of the fifth adder unit 226 is connected to the first group input eleventh comparator 241, the second group the inlet of which a constant is 0, the outputs of the third comparator 233, the fourth comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, eighth comparator 238, the ninth comparator 239 tenth of the comparator 240 is connected to group the input of the encoder 242, group output of which is the third group output MODES 2, the output of the eleventh comparator 241 is the third output MODES 2, the second group the inputs of the third adder 244, a fourth adder 245 and twelfth comparator 247 is connected to the constant 2, group outputs of the third adder 244 and the fourth adder 245 is connected to group the inputs of the second shaper address 246, group output which is the second group output MODES 2, the first group entrance of the twelfth comparator 247 is the fifth group input MOD 2, the inputs of the element 211 And connected to quijada the first comparator 25 and the second comparator 26, respectively, the output element 211 And is the first release of the MOD 2.

Each register block 212÷221 (6) consists of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, the first register 810, a second register 811, the third register 812, the fourth register 813, the fifth register 814, the sixth register 815, the seventh register 816, the eighth register 817, ninth register 818, the first adder 819, the second adder 820, the third adder 821, the fourth adder 822, the fifth adder 823, the sixth adder 824, seventh adder 825 eighth adder 826, the first constant 851, the second constant 852, third constants 853, fourth constants 854, fifth constants 855 sixth constants 856, seventh constants 857, eighth constants 858, ninth constants 859, tenth constants 860, eleventh constants 861, twelfth constants 862, thirteenth constants 863, fourteenth constants 864, fifteenth constants 865, sixteenth constants 866, seventeenth constants 867, eighteenth constants 868, and the first group of the input register unit is connected to group inputs the first register 810, a second register 811, the third register 812, the fourth register 813, the fifth register 814, the sixth register 815, the seventh is on the register 816, the eighth register 817, ninth register 818, the second group of the input register unit is connected to the first group the inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, the third group input register unit is connected to the third group the inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, the outputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89 is connected to the inputs of the first register 810, a second register 811, the third register 812, the fourth register 813, the fifth register 814, the sixth register 815, the seventh register 816, the eighth register 817, ninth register 818, respectively, group outputs of the first register 810, a second register 811, the third register 812, the fourth register 813 sixth register 815, the seventh register 816, the eighth register 817, ninth register 818 is connected to the first group the inputs of the first summit the RA 819, the second adder 820, the third adder 821, the fourth adder 822, the fifth adder 823, the sixth adder 824, seventh adder 825 eighth adder 826, respectively, group output of the fifth register 814 is connected to the second group to the inputs of the first adder 819, the second adder 820, the third adder 821, the fourth adder 822, the fifth adder 823, the sixth adder 824, seventh adder 825 eighth adder 826, the outputs of the first adder 819, the second adder 820, the third adder 821, the fourth adder 822, the fifth adder 823, the sixth adder 824, seventh adder 825, eighth adder 826 are a group of outputs of the register unit, the output of the fifth adder 823 is the fifth output groups outputs of the register unit, the output of the seventh adder 825 is the seventh output groups outputs of the register unit, the first constant 851, the third constant 853, the fifth constant 855, seventh constant 857, ninth constant 859, eleventh constant 861, thirteenth constant 863, fifteenth constant 865, seventeenth constant 867 connected to the second group to the inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, respectively, the second is onstant 851, the fourth constant 854, the sixth constant 856, eighth constant 858, tenth constant 860, the twelfth constant 862, fourteenth constant 864, sixteenth constant 866, eighteenth constant 868 is connected to the fourth group the inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, respectively. The values of the first constant 851, the second constant 852, third constants 853, fourth constants 854, fifth constants 855 sixth constants 856, seventh constants 857, eighth constants 858, ninth constants 859, tenth constants 860, eleventh constants 861, twelfth constants 862, thirteenth constants 863, fourteenth constants 864, fifteenth constants 865, sixteenth constants 866, seventeenth constants 867, eighteenth constants 868 is determined according to the table shown at 11.

Each summing block 222-230 (7) consists of the first adder 91, the second adder 92, the third adder 93, the fourth adder 894, fifth adder 95, sixth adder 96, the seventh adder 97, eighth adder 98, ninth adder 99, and the outputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, sixth the second adder 96, the seventh adder 97, eighth adder 98 is connected to the first, second, third, fourth, fifth, sixth, seventh, eighth inputs of the ninth adder 99, respectively, the first inputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, sixth adder 96, the seventh adder 97, eighth adder 98 are the first group of inputs of the adder block, the second inputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, sixth adder 96, the seventh adder 97, eighth adder 98 is the second group of inputs of the summing block group output ninth adder 99 is a group output of summing block.

The definition of the objects of the IPO 3 (Fig) consists of the first counter 31, a second counter 32, the third counter 33, the fourth counter 34, the fifth counter 35, the sixth counter 36, the trigger 37, the first element And 38, the first element OR 39, the first adder 310, a second adder 311, the third adder 312, a fourth adder 313, the fifth adder 314, the first comparator 315, the second comparator 316, the second shaper address 318, the data Converter 319, the first shaper address 320, the second element And 321, the first multiplexer 322, the first element NOT 323, the first register 324, which is LEGO comparator 325, the third element, And 327, the fourth comparator 328, the fifth comparator 331, a sixth comparator 332, the seventh comparator 333, eighth comparator 334, the ninth comparator 335, tenth comparator 336, a second register 337, the third register 338, the fourth register 339, fifth register 340, the sixth register 341, the seventh register 342, the eleventh of the comparator 343, twelfth comparator 344, the thirteenth of the comparator 345, fourteenth comparator 346, fifteenth comparator 347, sixteenth comparator 348, fourth element And 361, the fifth element And 362, the sixth element And 363, the seventh element And 364, the eighth element And 365, the ninth element And 366, the eighth register 367, ninth register 368, tenth register 369, eleventh register 370, twelfth register 371, thirteenth register 372, the second element OR 373, third element OR 374, fourth element OR 375, the fifth element OR 376, seventh counter 377, eighth counter 378, ninth counter 379, fourteenth register 380, the tenth element And 381, the tenth counter 382, the buffer element 383, the second multiplexer 384, eleventh element And 385, the twelfth element And 386, the second buffer item 387, the third multiplexer 388, seventeenth comparator 389, the third buffer element 391, eighteenth comparator 392, the first RAM 71, the second RAM 72, the third RAM 73, the rich first input of the first element And 38 is the first sign of MOO 3 and is designed to supply the clock signal CLKX, the trigger output 37 is connected to the second input of the first element And 38, the output of the first element And 38 connected to the first input of the first counter 31, the group output of the first counter 31 is connected to the first input of the first group of driver address 320 and the first group to the input of the first comparator 315, the second group entrance of MOO 3 is connected to the second input of the first group of comparator 315, the output of the first comparator 315 is connected to the first input of the second element And 321 to the second input of the first element OR 39 and to the first input of the second counter 32, the output of the first element 39 is connected to the second input of the first the counter 31, the group output of the second counter 32 is connected to the first group the input of the second comparator 316 and the second input of the first group of driver address 320 whose output is connected to the first input of the first group of multiplexer 322, the third group entrance of MOO 3 is connected to the second group to the input of the second comparator 316, the output of the second comparator 316 is connected to the second input of the second element And 321 to the second input of the second counter 32 and to the first input of the first element OR 39, the output of the second element And 321 is the output of MOO 3, the output of the trigger 37 is connected to the input of the first element 323 and NOT to input of the first register 324, the output of the first element 323 is connected to the input of the first multiplexer 322, to the third input is the fifth counter 35, to the second input of the sixth counter 36 and to the first and second inputs of the third buffer element 391, whose output is connected to the input/output of the first RAM 71, the first group entrance of MOO 3 is connected to the input of the first group of register 324, the output of the first group of register 324 is connected to the first group to the input of the third comparator 325, at whose second group input is constant 0, the output of the third comparator 325 is connected to the first input of the third element And 327, the output of which is connected to the first input of the trigger 37, the input/output of the first RAM 71 is connected to the first input of the fourth comparator 328, to whose second input is the constant 1, the output of the fourth comparator 328 is connected to the second input of the third element And 327, the input of the third counter 33 is a second input of MOO 3 and is designed to supply the clock signal CLKX6, group output of the third counter 33 is connected to the fourth input of the counter 34, the group output of the third counter 33 is connected to the first group input of the first adder 310, whose second group input is the constant 1, the output of the first adder 310 is connected to the first group the input of the second adder 311, whose second group input connected to group the output of the fifth counter 35, the third group the input of the second adder 311 is connected to group the output of the first counter 31, the first group of the input trateg the adder 312 is connected to group the output of the fourth counter 34, the second group, the third input of the adder 312 is connected to group the output of the sixth counter 36, the third of group the third input of the adder 312 is connected to group the output of the second counter 32, the group outputs of the second adder 311 and the third adder 312 is connected respectively to the first and second group to the second inputs of the former (address 318, group output of which is connected to the second input of the first group of multiplexer 322 and to group the input of the first RAM 71, group output of the third counter 33 is connected to the first group to the input of the fifth comparator 331, a sixth comparator 332, the seventh comparator 333, eighth comparator 334, the ninth comparator 335, tenth comparator 336, group fourth output of the counter 34 is connected to the third group to the input of the fifth comparator 331, a sixth comparator 332, the seventh comparator 333, eighth comparator 334, the ninth comparator 335, tenth comparator 336, the second group input and the fourth group fifth input of the comparator 331 is constant 0, the second group input and the fourth group of the sixth input of the comparator 332 is served, respectively, the constant 1 and constant 0, the second group input and the fourth group the entrance of the seventh comparator 333 is served, respectively, the constant 2 and the constant 0, the second group input and the fourth group the new entrance of the eighth comparator 334 serves accordingly, the constant 0 and constant 1, in the second group the input and the fourth group entrance of the ninth comparator 335 is constant 1, the second group input and the fourth group sign-tenth of the comparator 336 is served, respectively, the constant 2 and the constant 1, the output of the fifth comparator 331 is connected to the input of the second register 337, the output of the sixth comparator 332 is connected to the input of the third register 338, the output of the seventh comparator 333 is connected to the input of the fourth register 339, the eighth output of the comparator 334 is connected to the input of the fifth register 340, the output of the ninth comparator 335 is connected to the input of the sixth register 341, the output of the tenth comparator 336 is connected to the input of the seventh register 342, first group the inputs of the second register 337, the third register 338, the fourth register 339, fifth register 340, the sixth register 341, the seventh register 342 is connected to the first group to the entrance of MOO 3, group outputs of the second register 337, the third register 338, the fourth register 339, fifth register 340, the sixth register 341, the seventh register 342 is connected respectively to the first group inputs eleventh comparator 343, twelfth comparator 344, the thirteenth of the comparator 345, fourteenth comparator 346, fifteenth comparator 347 and sixteenth comparator 348, whose second group inputs connected to the output group the first register 324, the output of the eleventh to the of narator 343 connected to the first input of the fourth element And 361 and to the third input of the ninth element And 366, the output of the twelfth comparator 344 is connected to the first input of the fifth element And 362 to the second input of the fourth element And 361, to the first input of the sixth element And 363 to the second input of the seventh element And 364, to the first input of the eighth element, And 365 and to the first input of the ninth element And 366, the output of the thirteenth comparator 345 is connected to the second input of the fifth element And 362 and the fifth input of the ninth element And 366, the output of the fourteenth comparator 346 is connected to the first input of the seventh element And 364 and the sixth input of the ninth element And 366, the output of the fifteenth comparator 347 is connected to the second the input of the eighth element, And 365 and the fourth input of the ninth element And 366, the output of the sixteenth comparator 348 is connected to the second input of the sixth element And 363 and the second input of the ninth element And 366, the output of the fifth element And 362 connected to the third input of the sixth element And 363, whose output is connected to the third input of the eighth element And 365, whose output is connected to the third input of the seventh element And 364, whose output is connected to the third input of the fourth element And 361, the outputs of the fourth element And 361, the fifth element And 362, the sixth element And 363, the seventh element And 364, the eighth element And 365, the ninth element And 366 are connected respectively to the first inputs of the eighth register 367, ninth register 368, tenth register 369, eleventh register 370, twelfth the CSO register 371, the thirteenth register 372, whose second input is connected to the output of the tenth comparator 336 and third inputs of the data registers connected to the output of the fifth comparator 331, the output of the eighth register 367 is connected to the second input of the fifth element OR 376 and to the first input of the second element OR 373, the output of the ninth register 368 is connected to the first input of the third element OR 374 and to the second input of the second element OR 373, the output of the tenth register 369 connected to the first input of the fourth element OR 375 and to the third input of the second element OR 373, the output of the eleventh register 370 is connected to the first input of the fifth element OR 376 and to the fourth input of the second element OR 373, the output of the twelfth register 371 is connected to the third input of the fourth element OR 375 and to the fifth input of the second element OR 373, whose output is connected to the first input of the seventh counter 377 and to the first input of the eighth counter 378, the output of the third element OR 374 connected to the first input of the fifth counter 35, the output of the fourth element OR 375 connected to the first input of the sixth counter 36, the output of the fifth element OR 376 is connected to the second input of the fifth counter 35, the output of the thirteenth register 372 is connected to the second input of the ninth counter 379, which negative input to the first input of the tenth element And 381 and to the first input of the tenth counter 382, the first input of the ninth counter 39, is the third sign of MOO 3 and is designed to supply the clock signal CLKY, the first output of the ninth counter 379 is connected to the second input of the tenth element And 381, the output of the tenth element And 381 are connected to the input of the fourteenth register 380, group output of the seventh counter 377 is connected to the group entrance fourteenth register 380, group output fourteenth register 380 is connected to group the input of the buffer element 383, whose output is connected to group input-output of the second RAM 72, group tenth output of the counter 382 is connected to the first group the input of the second multiplexer 384, whose second group entrance is the fourth group entrance LEAs 3, group the output of the second multiplexer 384 is connected to the input of the second group RAM 72, the first and second outputs of the ninth counter 379 connected respectively to first and second inputs of the eleventh element And 385, the first input of which is inverted and the output is connected to the second input of the twelfth element And 386, whose output is connected to the input of the second RAM 72, the first group of the input of the fourth adder 313 is connected to group the output of the fifth counter 35, the second group the input of the fourth adder 313 is connected to group the output of the first counter 31, the first group of the input of the fifth adder 314 is connected to group the output of the second counter 32, the second group is new to the input of the fifth adder 314 is connected to group the output of the sixth counter 36, group outputs of the fourth adder 313 and the fifth adder 314 is connected respectively to the first and second group of the input data Converter 319, whose output is connected to group the input of the second buffer element 387, group output of which is connected to group input-output of the third RAM 73, group output of the eighth counter 378 is connected to the first group to the third input of the multiplexer 388, the second group the input of the third multiplexer 388 is the fifth group entrance of MOO 3, group output of the third multiplexer 388 is connected to the group entrance to the third RAM 73, the first group entrance seventeenth comparator 389 connected to group the output of the first counter 31, the second group entrance seventeenth comparator 389 connected to group the output of the second counter 32, the third group entrance seventeenth comparator 389 is constant 0, the output of the seventeenth comparator 389 is connected to the second input of the eighth counter 378 and to the second input of the tenth counter 382, the sixth group entrance of MOO 3 is connected to the first group to the entrance of the eighteenth comparator 392, the second group the inlet of which a constant 2, the output of the eighteenth comparator 392 is connected to the first input of the twelfth element And 386, the input of the second multiplexer 384 and the input of the third multiplexer 388, group output Pervov the multiplexer 322 is the first group output LEAs 3, group tenth output of the counter 382 is the second group out of MOO 3, group input/output of the second RAM 72 is the third group out of MOO 3, group input/output of the third RAM 73 is the fourth group out of MOO 3, when the trigger 37 is a RS-flip-flop, the first input of which is the R-input of the second input - S input, the first output of the ninth counter 379 is the younger discharge its output value, the second output - senior category, the inputs of the second multiplexer 324 and the third multiplexer 388 are inverted inputs, the data of the first RAM 71 are single-bit.

The correction module MK 4 (figure 9) consists of the first register 453, the first comparator 454, the first counter 455, the second comparator 456, pulse generator 457, second element And 458, a second counter 459, the third comparator 460, the first flip-flop 461, the first element And 462, the fourth comparator 463, the fifth comparator 464, the third counter 465, the second trigger 466, a second register 467, the third register 468, the fourth register 469, multiplexer 470, the data Converter 471, the first adder 472, the second adder 473, the first constant 474 1, shaper address 475, the second constant 476 0, the third constant 477 equal to 1, the fourth constant 478 equal to 2, module emphasize the contours 479, fifth register 480, the seventh comparator is 481, fifth constants 482 equal to 3, the third element And 483, the sixth comparator 484, and the input of the first register 453 is the third entrance MK 4, the first group entrance MK 4 is connected to the input of the first group of register 453, group output of the first register 453 is connected to the first group input of the first comparator 454, the output of the first comparator 454 is connected to the second input of the first counter 455 and to the first output MK 4, the first group output MK 4 is connected to group the output of the first counter 455, the second group entrance MK 4 is connected to the first group the input of the second comparator 456, the first group to the input of the third comparator 460 and to the first group the input of the pulse generator 457, fourth group entrance MK 4 is connected to the second group to the input of the second comparator 456, the output of the second comparator 456 is connected to the input of the pulse generator 457 to the second input of the third counter 465 and to the first input of the first flip-flop 461, the output of pulse generator 457 is connected to the first input of the second element And 458, whose output is connected to the first input of the second counter 459, whose group output, which is the fourth group MK outlet 4 connected to the second group to the third input of the comparator 460, whose output is connected to the second input of the first flip-flop 461 and to the second input of the second counter 459, the output of the first flip-flop 461 is connected to second the d input of the first element And 462, the output of the first element And 462 connected to the first input of the first counter 455, the first input of the MK 4 is designed to supply the clock signal CLKW and connected to the first input of the first element And 462 and the first input of the third element And 483, the second input is connected to the output of the second trigger 466, and the output of the third element And 483 is connected to the second input of the second element And 458, a second input of the MK 4 is designed to supply the clock signal CLKZ and connected to the first input of the third counter 465, group output of the third counter 465 is connected to group the input of the fourth comparator 463, whose output is connected to the first input of the second trigger 466 and to the input of the second register 467, a group whose input is connected to the fifth group input module MK 4, group a inputs of the third register 468 and the fourth register 469 also connected to the fifth group input module MK 4, group output of the third counter 465 is connected to the ninth group input multiplexer 470, the third group entrance MK 4 is connected to group the input data Converter 471, whose first group output connected to the first, third and fourth group the inputs of multiplexer 470 and the first input of the first adder 472, the second group the output of the data Converter 471 is connected to the fifth, sixth and eighth group the inputs of multiplexer 470 and the second group the entrance of the second adder 473, in the second group the input of the first adder 472 and the first group the input of the second adder 473 served the third constant 474 1 group output of the first adder 472 is connected to the second group input multiplexer 470, group the output of the second adder 473 is connected to the seventh group input multiplexer 470, the first and second group outputs of multiplexer 470 is connected respectively to first and second inputs of the former (address 475, a group whose output is the second group output MK 4, the output of the fifth comparator 464 is connected to the input of the third register 468, the output of the sixth comparator 484 is connected to the input of the fourth register 469, the second group fourth inputs of the comparator 463, the fifth comparator 464, the sixth comparator 484 serves a constant value specified by the second constant 476, the third constant 477, fourth constant 478, 0, 1, and 2, respectively, group outputs of the second register 467, the third register 468 and the fourth register 469 are connected respectively to the first, second and third group the module inputs emphasize the contours 479, a group whose output is connected to group the input of the fifth register 480, the output of the third counter 465 is connected to the first group to the entrance of the seventh comparator 481, at whose second input is the fifth constant 482, equal to 3, the output of the seventh Communist the Torah 481 is connected to the second input of the second trigger 466 and to the input of the fifth register 480, whose group output is the third group output MK 4, the output of the second trigger 466 is the second release of MK 4.

Module emphasize the contours of the IPC 479 (figure 10) consists of a first multiplier 411, the second multiplier 412, the third multiplier 413, a fourth multiplier 414, the third adder 417, module selection square root 419, the first adder 420, a second adder 421, the fourth adder 422, and the first group entrance IPC 479 is connected to the first group input of the first adder 420, a second group entrance IPC 479 is connected to the second group input of the first adder 420 and the first group to the second input of the adder 421, the third group entrance IPC 479 is connected to the second group to the input of the second adder 421, group the output of the first adder 420 is connected to the first and second group to the inputs of the first multiplier 411, group the output of the second adder 421 is connected to the first and second group to the second inputs of the multiplier 412, group outputs of the first multiplier 411 and the second multiplier 412 is connected respectively to the first and second group to the third inputs of the adder 417, a group whose output is connected to group input module selection square root 419, group output module selection square root 419 is connected to the first group to the input of the third multiplier 413, the second group of the input which the CSO is the fourth group entrance IPC 479 and is designed to supply a constant value k1 (where k1 is the first integer weighting factor that determines the degree emphasize the contours), group output of the third multiplier 413 is connected to the first group to the input of the fourth adder 422, the second group entrance IPC 479 is connected to the first group to the fourth input of multiplier 414, the second group entrance which is the fifth group entrance IPC 479 and is designed to supply a constant value k2 (where k2 is the second integer weighting factor that determines the degree emphasize the contours), group output of the fourth multiplier 414 is connected to the second group to the input of the fourth adder 422, group output of the fourth adder 422 is a group output IPC 479, the first adder 420 and a second adder 421 performs a subtraction function.

Device for compensation of the image blur works in four modes, specified by the value in the group output of the meter 100. The operating modes of the device sequentially alternating with 0 to 3 for each coming from DI 10 frame. In the zero mode is the output of the processed frame to the system bus and the write data from DI 10. In the first mode, the detection and determination of the direction of motion for each pixel. In the second mode, the pixels with the same direction are grouped into objects. In the third mode for the found driving is, for example by transferring them of interest calculation and correction of pixel intensity to compensate for image blur.

In the zero mode input DI 10 receives an input signal CLK/3. Group output DI 10 in the first group the input of the controller 1 sequentially transmitted to the brightness of the pixels of the current frame image.

The controller 1 operates in three modes, which are interleaved sequentially from 2 to 0 for each pixel, and provides: in mode 2 - delivery of the data from the first RAM 5 on the system bus to school, mode 1 - overwrite frame from the first RAM 5 in the second RAM 6, mode 0 - write data received from the image sensor in the first RAM 5. In all modes of operation of the controller 1 data processing of the first RAM 5 and the second RAM 6 is made at the address formed on the second group output controller 1.

In mode 2, the controller 1 reads the intensity value of the pixel from the first RAM 5 and issue it to the system bus. For this purpose, the controller 1 in their second group generates output address value and transmits it to the first group the input of the first multiplexer 51, with the group out of which he comes to group the input of the first RAM 5. At this address the brightness value of the pixel of the current frame with the group of input-output of the first RAM 5 is read and supplied to the first group, the first input of the demultiplexer 56, with the first group out of which it is transmitted to the fourth group the input of the controller 1 and further along the SHS will with the third group of output controller 1 on the system bus.

Further, in mode 1, the controller 1 records read from the first RAM 5 brightness value of the pixel in the second RAM 6. The brightness value of the pixel is read on the previously generated address and transmitted from the group of input-output of the first RAM 5 in the first group the first input of the demultiplexer 56, from which it is fed to the fourth group the input of the controller 1. The fourth group of output controller 1, the brightness value of the pixel is supplied to the first group entry to the sixth multiplexer 57, with the group out of which it comes to group the input-output of the second RAM 6.

Later in mode 0, the controller 1 writes the brightness value of the current pixel received from DI 10 in the first RAM 5. For this purpose, the previously formed on the second group output controller 1 the value of the address of the pixel is supplied to the first group the input of the first multiplexer 51 and forth from a group of output of the first multiplexer 51 to group the input of the first RAM 5. With the first group of output controller 1 the value of the current pixel's brightness goes to group the input of the fifth multiplexer 55, with the group out of which the brightness value of the current pixel is transmitted to the input-output of the first RAM 5. Read/write data from the first RAM 5 and the second RAM 6 for all operating modes of the device is similar to that of the zero mode is.

On the second and third group the inputs of the controller 1 are constants (H-1) and (Y-1), respectively.

The first output of controller 1, a signal is generated that defines the operation mode of the first RAM 5: read or write data. For this purpose, the signal from the first output controller 1 is supplied to the first input of the second multiplexer 52, the output of which is transmitted to the input of the first RAM 5. On the second output controller 1, a signal is generated that defines the operation mode of the second RAM 6: read or write data. For this purpose, the signal from the second output controller 1 is supplied to the first input of the fourth multiplexer 54, the output of which is transmitted to the input of the second RAM 6.

The signal on the third output of the controller 1 is received at the first input of the OR element 101 and forth from its output to the input of counter 100 is the increment values to group the output of the counter 100 and the switching mode of the device from zero in the first. The group output of the counter 100, the signal is sent to the first group the input of the first comparator 102, the second group whose input is filed with the constant 0. The first comparator 102 performs the function of "not equal" and outputs the value 0 at its output when the inequality of mode zero. From the output of the first comparator 102, the signal at the third input of the controller 1. When a single value of this output signal is to reset and the prohibition of the operation of the controller 1, if set to zero, this signal is the resolution of the controller.

The mode of operation of the device group with the output of counter 100 is supplied to the fourth group the input of the first multiplexer 51, group input of the second multiplexer 52, the third of group the third input of the multiplexer 53, group input of the fourth multiplexer 54, the third group the input of the fifth multiplexer 55 and the second group the entrance of the sixth multiplexer 57, and the second group the inputs of the first demultiplexer 56 and the second demultiplexer 58.

In the first mode of the device MOD 2 produces the detection and determination of the direction of motion for each pixel.

The first and second group inputs MOD 2 are constants (X-3) and (Y-3), respectively. At first login MOD 2 receives a clock frequency CLK/25.

The first group output MOD 2 is gradually formed the address value of the currently processed pixel, which is supplied to the second group the inputs of the first multiplexer 51 and the third multiplexer 53, with a group of outputs which it is then delivered to group the inputs of the RAM 5 and the RAM 6, respectively. The fourth group input MOD 2 from the second group of output of the first demultiplexer 56 receives the brightness value of the pixel of the current frame, on which input the value entered with group input the output of the RAM 5. The third group input MOD 2 from the second group of the output of the second demultiplexer 58 receives the brightness value of the pixel of the previous frame, on which input this value came from the group of input-output RAM 6.

The fifth group input MOD 2 group output of counter 100 is number of modes of the device. During the first mode of the device on the second output MOD 2 is formed of a zero signal, and at other modes of operation of the device is a single signal that is input to the seventh multiplexer 59. From the second group of output MOD 2 for the second group the entrance of the seventh multiplexer 59 receives the address value of the current pixel, which is a group of the output of the seventh multiplexer 59 is transmitted to the group entrance to the third RAM 7. In the group of input-output of the third RAM 7 from the third group of output MODES 2 receives the value of the direction of the current pixel, which is when a single is on the third output MODES 2, applied to the input of the third RAM 7, is written in this RAM. Upon completion of the processing of the last pixel of the frame on the first release of the MOD 2 is formed of a single signal to the second input of the OR element 101 and the transferring device to the next (second) mode of operation.

In the third mode of the device of MOO 3 analyzes the direction of movement of each is about pixels and groups of pixels with the same direction of motion in objects.

On the second and third group the inputs of MOO 3 are constants (X-2) and (Y-2), respectively. At the first sign of MOO 3 comes clocked CLKX. To the second input of MOO 3 comes clocked CLKX6. At the third entrance of MOO 3 comes clocked CLKY.

The sixth group entrance of MOO 3 group output of counter 100 receives the mode of operation of the device. With the first group of output of MOO 3 address value of the current of the analyzed pixel is supplied to the first group entrance of the seventh multiplexer 59 and forth with his group the entrance to the third RAM 7. With the group of input-output of the third RAM 7 is the direction of the current pixel is supplied to the first group entrance of MOO 3. After processing the last pixel of the frame at the output of MOO 3 is formed of a single signal to the third input of the OR element 101 and the transferring device to the next (fourth) mode, and the third entrance MK 4 and provides values for the number of objects formed on the second group out of MOO 3 and supplied to the first group entrance MK 4.

In the fourth mode of the device MK 4 sequentially formed for all LEAs 3 objects makes the determination of the number of pixels constituting the object, the calculation of the adjusted brightness values of pixels of moving objects and record adjusted the level of the brightness values of pixels in the first RAM 5.

On the first entrance MK 4 comes clocked CLKW, the second input of the MK 4 is the clock CLKZ.

In its work, the MK 4 in the first group generates output value of the address at LEAs 3 recorded the number of pixels of the current of the analyzed object and delivers it to the fourth group entrance of MOO 3. In the fourth group the output of the MK 4 is formed, the value of the address of NGO 3 reads the coordinate values of the current processed pixel, and come to the fifth group entrance of MOO 3. The third group of output of MOO 3 the second group entrance MK 4 receives the number of points of the current of the analyzed object. The fourth group of output of MOO 3 the third group entrance MK 4 receives the coordinates of the current pixel of the current of the analyzed object.

The fifth group entrance MK 4 receive data (pixel intensity adjustment area) with the fourth group of output of the first demultiplexer 56 read with the group of input-output of the first RAM 5 according to the address generated by the second group output MK 4 and filed in the fourth group the input of the first multiplexer 51, the output of which is transmitted at the group entrance of the first RAM 5, and served on the first group, the first input of the demultiplexer 56.

In the process MK 4 in their second group generates output address value, determine playsega coordinates of the pixel with the adjusted brightness value, and submits it to the fourth group the input of the first multiplexer 51, with the group out of which this address value is supplied to group the input of the first RAM 5. In the third group the output of the MK 4 is formed adjusted the brightness value of the pixel, which is supplied to the fourth group the input of the fifth multiplexer 55, with group output of which is sent to group the input-output of the first RAM 5 and is written into it.

The fourth group entrance MK 4 served a threshold value that determines the minimum number of pixels in the object. Outlet MK 4 is formed of a single signal at the fourth input of the OR element 101 and the transferring device in the zero mode.

The controller 1 operates as follows. At the first input of the first counter 13, which defines the x coordinate of the current processed pixel receives the clock signal CLK/3, which is to group the output of the first counter 13 is incremented by one and fed to the first group the input of the first comparator 16. In the second group the input of the first comparator 16 is constant (H-1), where X is the size of the frame horizontally. From the output of the first comparator 16, the signal at the second input of the first element OR 11, the output of which is applied to the second input of the first counter 13. When a single value dannoharu is reset the first counter 13. Simultaneously, the output signal of the first comparator 16 is supplied to the first input of the second counter 14, which defines the y coordinate of the current processed pixel, of which output signal is fed to the first group the input of the second comparator 17, the second group whose input is filed with the constant (Y-1), where Y is the size of the frame vertically. From the output of the second comparator 17, the signal at the second input of the second element OR 12 and to the first input of the first element OR 11. With the release of the second element OR 12 signal is applied to a second input of the second counter 14. When a single value of this signal is provided to the reset of the second counter 14. Thus, a sequential scan of the coordinates (x,y) pixels, where x∈[0,X-1],∈[0,Y-1].

The group output of the first counter 13 and the group of the output of the second counter 14 coordinates (x,y) of the current pixel are received respectively in the first and second group the inputs of the former (address 18, whose group output, which is formed by the address value of the current pixel is the second group output controller 1.

The third counter 15, which is designed to set the current operating mode of the controller, ensures the formation at its Dubina group value of from 0 to 2. At the first input of the third counter 15 receives the clock signal CLK, which provide the rest of the increment values at the output of the counter. Group output of the third counter 15 signal is supplied to the second group input buffer 110, the first group whose input is the signal from the image sensor 10. When 0, the second group of the input buffer 110 is provided a transmission signal from DI 10 group output buffer 110, which is the first group output controller 1. For other values in the second group input buffer 110 his group the output is the third high-impedance state.

From the output of the first comparator 16, the output of the second comparator 17 and the high-order group output of the third counter 15, the signals on the first, second and third inputs of the element And 19, the output of which the signal at the third output of the controller 1 and 0 means the completion of the mode of compensation of the image blur.

Group output of the third counter 15 signal is supplied to the second group the input of the demultiplexer 111, the first group entry which is the fourth group the input of the controller 1. When 0, the second group the input of the demultiplexer 111 provided the transmission signal with the first group of input on his first group output, which is the third group output controller 1. A value of 1 in the second group the input of the demultiplexer 111 is provided podklyuchenie first group at its second input group output, the fourth group output controller 1.

The third input of the first element OR 11, the first input of the second OR element 12 and the second input of the third counter 15 receives the signal, a single value which blocks the operation of the controller 1.

The signal from the second output controller 1 is used to control read/write of the second RAM 6.

Module motion detection 2 works as follows. At the first input of the first counter 21 receives the clock signal CLK/25, on which the first counter 21 increments its value. The group output of the first counter 21 and the x-coordinate of the currently processed pixel is fed to the first group the input of the first adder 27 and the first group the input of the first comparator 25, the second group input of which receives the value of (X-3). If the values match on both their group the inputs of the first comparator 25 sends a signal to the second input of the OR element 210, the output of which the signal at the second input of the first counter 21 and resets the first counter 21 to zero state. Simultaneously with the output of the first comparator 25, the signal at the first input of the second counter 22 with the group of which output signal is supplied to the first group the input of the second comparator 26, the second group input of which receives the value of (Y-3). If the values match, n is both their group the inputs of the second comparator 26 generates a single signal, supplied to the second input of the second counter 22 and the first input of the OR element 210 and forth from its output to the second input of the first counter 21, thereby resetting the first counter 21 and the second counter 22 to zero state. Thus, in the group output of the first counter 21 is gradually formed the x coordinate of the current processed pixel values from 0 to (X-3); the output of the second counter 22 sequentially formed coordinate of the current processed pixel values from 0 value to (I-3).

To the input of the third counter 23 receives the clock signal CLK, to group the output of the third counter 23 are sequentially formed values of i from 0 to 4, inclusive, which are received in the second group the input of the first adder 27. When the overflow of the third counter 23 at its second output a signal is generated at the input of the fourth counter 24 and its output an incremental value. With a group of fourth output of the counter 24 values of j from 0 to 4 inclusive are received in the second group the input of the second adder 28. With a group of outputs of the first counter 21 and the second counter 22 values x and y are received on the first group the inputs of the first adder 27 and the second adder 28. Group outputs of the first adder 27 and the second adder 28 are formed values that define the coordinates (x+i, j) of the current pixel, received on the first and second group the inputs of the first shaper address 29. The first shaper address 29 produces at its group output forming the address And in accordance with the formula A=(x+i)+(I+j)*X and delivers the address And the first group output MOD 2.

The first group of the first input register block 212 with the fourth group of input MOD 2 receives the brightness value of the current pixel of the current frame. For the first group the inputs of the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221 with the third group of input MOD 2 receives the brightness value of the current pixel of the previous frame. In the second group the inputs of the first register block 212, the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register unit 221 receives the values of j with a group of fourth output of the counter 24. In the third group the inputs of the first register block 212, the second register unit 23, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register unit 221 receives the values of i group with an output of the third counter 23.

Group output of the first register block 212 are formed in the matrix elements In(k) in accordance with formula (1) and come to the first group the inputs of the first summing block 222, the second summing block 223, the third summing unit 224, a fourth summing block 225, the fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summation block 230.

Group outputs of the second register unit 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221 are formed in the matrix elements In the*(k) for each of the 8 directions of motion in accordance with formula (2) and fed to the second group the inputs of the first summing block 222, the second summing block 223, the third summing unit 224, the fourth sum is the dominant block 225, fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summation block 230.

Group outputs of the first adder block 222, the second summing block 223, the third summing unit 224, a fourth summing block 225, the fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summation block 230 are formed in the matrix elements In the*(k-1) in accordance with formula (3).

The value group of the output of the fifth adder block 226 is supplied to the first group entrance eleventh comparator 241, the second group the inlet of which a threshold value, when compared with which is determined by the actual movement of the current pixel of the current frame. Output eleventh comparator 241 signal at the third output MOD 2.

Values with the group of outputs of the first adder block 222, the second summing block 223, the third summing unit 224, a fourth summing block 225, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summation block 230 are received in the corresponding group unit determining minimum 231 and the first group to the third inputs of the comparator 233, otwartego comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, eighth comparator 238, ninth comparator 239 tenth of the comparator 240. In the second group the third inputs of the comparator 233, the fourth comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, eighth comparator 238, ninth comparator 239, tenth comparator 240 receives the size of the group output unit determining at least 231.

Thus, at the outputs of the third comparator 233, the fourth comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, eighth comparator 238, ninth comparator 239 tenth of the comparator 240. The second group of inputs of the third comparator 233, the fourth comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, eighth comparator 238, ninth comparator 239, tenth comparator 240 in the code "1 of N" are formed in the direction of the current pixel of the current frame, which serves to group the input of the encoder 242. At the output of the encoder 242, which is the third group output MODES 2, are formed, the bearing movements in binary code.

The group output of the first counter 21 and the x coordinate of the current pixel is supplied to the first group the input of the fourth adder 245. With the output of the second group with whom etchika 22 coordinate of the current pixel is supplied to the first group the input of the third adder 244. In the second group the inputs of the third adder 244 and the fourth adder 245, and the second group the entrance of the twelfth comparator 247 receives the constant 2. With a group of outputs of the third adder 244 and the fourth adder 245 coordinate values of the current pixel (x+2, y+2) are fed to the first and second group the second inputs of the former (address 246, group output which is the second group output MOD 2.

From the output of the first comparator 25 and the output of the second comparator 26, the signals are sent to first and second inputs of the element And 211, the output of which the signal at the first output MOD 2. This signal increments the value of the device mode of compensation of the image blur.

Each of the register blocks 212-221 works as follows. From the second group of input register block in the first group the inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89 is supplied value i, with the third group of input register block in the third group the inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, Wasim the second comparator 88, the ninth comparator 89, the third input register unit is connected to a third input of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89 receives the value of j. The values i, j define the coordinates of the current pixel of the current window handle 3×3. The coordinates of the current window handle, defined by the first constant 851, the second constant 852, the third constant 853, the fourth constant 854, the fifth constant 855, the sixth constant 856, seventh constant 857, eighth constant 858, ninth constant 859, tenth constant 860, the eleventh constant 861, twelfth constant 862, thirteenth constant 863, fourteenth constant 864, fifteenth constant 865, sixteenth constant 866, seventeenth constant 867, eighteenth constant 868, served on the second and fourth group the inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89. The outputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, with whom Dimage comparator 87, the eighth comparator 88, the ninth comparator 89 is formed logical unit if the values match on their first, second group and third inputs, the fourth group of inputs respectively and fed to the inputs of the first register 810, a second register 811, the third register 812, the fourth register 813, the fifth register 814, the sixth register 815, the seventh register 816, the eighth register 817, ninth register 818, the outputs of the first register 810, a second register 811, the third register 812, the fourth register 813 sixth register 815, the seventh register 816, the eighth register 817, ninth register 818. With the first group of input register unit to group the inputs of the first register 810, a second register 811, the third register 812, the fourth register 813, the fifth register 814, the sixth register 815, the seventh register 816, the eighth register 817, ninth register 818 is a brightness value of the current pixel. Registers are used to store the pixel intensity window treatments 3×3. The group output of the fifth register 814, the luminance value of the Central pixel is fed to the second group the inputs of the first adder 819, the second adder 820, the third adder 821, the fourth adder 822, the fifth adder 823, the sixth adder 824, seventh adder 825 eighth adder 826. With a group of outputs of the first register 810, a second register 811, retigo register 812, the fourth register 813 sixth register 815, the seventh register 816, the eighth register 817, ninth register 818 value of brightness of the peripheral pixels window treatments 3×3 arrive at the first group the inputs of the first adder 819, the second adder 820, the third adder 821, the fourth adder 822, the sixth adder 824, seventh adder 825 eighth adder 826, the outputs of which are group outputs of the register block. Adders provide subtracting a value received in the second group the entrance, from the values entered for the first group entrance. Thus, at the output of register block matrix is formed In the*(k)defined by formula (2).

Each of the summing blocks 222÷230 operates as follows. Values received in the first group the inputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, sixth adder 96, the seventh adder 97, eighth adder 98, are subtracted from the values received in the second group the inputs of these adders, respectively. The obtained difference with a group of outputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, sixth adder 96, the seventh adder 97, eighth adder 98 are received in the corresponding group inputs uwatoko adder 99, the output is the value that determines the amount of displacement in each of 8 directions in accordance with the formula (4).

The definition of the objects of MOO 3 is intended to define the objects described by a set of coordinates of its pixels in accordance with formula (14). For this NGO 3 provides a consistent analysis of the characteristics of the motion direction of each pixel, if the motion search is adjacent to the current pixel has the same direction and the determination of the number of pixels of each object.

LEAs 3 works as follows. At the first input of the first element And 38, which is the first input of MOOS, receives the clock signal CLKX. To the second input of the first element And 38 with the output of the first flip-flop 37 receives the signal, allowing the passage of the clock signal CLKX output of the first element And 38 to the first input of the first counter 31. Group output of the first counter 31 generates a value that specifies the x coordinate of the current processed pixel, which is supplied to the first group the input of the first driver addresses 320 and the first group the input of the first comparator 315. From the second group of input LEAs 3 in the second group the input of the first comparator 315 receives the value of (X-2). If the values match on both their group the inputs of the first comparator 315 sends a signal to the Torah input element OR 39, since the output of which the signal at the second input of the first counter 31 and resets the first counter 31 to zero state. Simultaneously with the output of the first comparator 315, the signal at the first input of the second counter 32 with the group of which output signal is supplied to the first group the input of the second comparator 316, the second group input of which receives the value of (Y-2). If the values match, the second comparator 316 generates a single signal to the second input of the second counter 32 and the first input of the OR element 39 and then its output to the second input of the first counter 31, thereby resetting the first counter 31 and the second counter 32 to zero state. Thus, in the group output of the first counter 31 is gradually formed the x coordinate of the current processed pixel values from 1 to (X-2); the output of the second counter 32 is gradually formed the y coordinate of the current processed pixel values from 1 values to (Y-2).

In the second group the input of the first driver address 320 receives the value of Y with the group of the output of the second counter 32. The output of the first driver address 320 is formed by the address of the current pixel and is supplied to the first group the input of the first multiplexer 322.

From the output of the first comparator 315 and the output of the second comparator 316 will signalinput on the first and second inputs of the element And 321, since the output of which the signal at the first output of MOO 3. This signal increments the value of the device mode of compensation of the image blur.

With the output of the first flip-flop 37 signal via the first inverter 323 is fed to the input of the first multiplexer 322 and to the input of the first register 324. To group the input of the first register 324 receives the value of the index movement direction of the current pixel and at unit level at its input is stored in this register and issued to group the output of the first register 324. Group the input of the first register 324 is the first group entrance of MOO 3. The group output of the first register 324 index value of the direction of the current pixel is supplied to the first group the input of the third comparator 325, the second group whose input is filed with the constant 0. With an output of the third comparator 325, which is the inverted output signal at the first input of the third element And 327. From the output of the fourth comparator 328, which is the inverted output to the second input of the third element And 327 receives a signal notifying that the current pixel has previously processed/not processed. At the first input of the fourth comparator 328 with input/output RAM 71 enters the sign of the processing pixel and at its second input is the constant 1. With an output of the third element And 327 signal, a single condition is which forbids moving on to the next pixel, arrives at the first input of the first flip-flop 37, dropping the trigger is in the zero state.

At zero output state of the third element And 327 of the first counter 31 and the second counter 32 is formed at its outputs control signals for processing of the next pixel, and when a single output state of the third element And 327 searched pixel whose properties satisfy the condition of formula (14). For this purpose, the input of the third counter 33 receives the signal CLKX6, an incremental counter value, the output of which is formed of the values of i from 0 to 2. With an output of the third counter 33, the signal received at the input of the fourth counter 34, an incremental counter value, the output of which is formed of the values of j from 0 to 1. With an output of the third counter 33, the signal arrives at the first group the input of the first adder 310, the second group whose input is filed with the constant 1. Group output of the first adder 310 are formed values (i-1). Value (i-1,j) determine the current coordinates of the analyzed points in a neighbourhood of a point (x,y) (figure 1).

The group output of the first adder 310, the information is transferred to the first group the input of the second adder 311, the second group entrance which is an auxiliary variable 1 group output of the fifth counter 35. In the third group the input of the second adder 311 post which becomes the value of x with group of output of the first counter 31. With a group of fourth output of the counter 34 j enter the values for the first group the input of the third adder 312, the second group entrance which is an auxiliary variable m with a group of sixth output of the counter 36. On the third of group the third input of the adder 312 receives a value from the group of the output of the second counter 32. Group outputs of the second adder 311 and the third adder 312 is formed of the values (x+i+1) and (I+j+m), respectively, defining the coordinates of a pixel used for reading data from RAM 70 and the recording characteristics of the processing pixel in the RAM 71. Group output of the third counter 33 for the first group the input of the fifth comparator 331, a sixth comparator 332, the seventh comparator 333, eighth comparator 334, the ninth comparator 335, tenth comparator 336 is supplied value i. In the third group the input of the fifth comparator 331, a sixth comparator 332, the seventh comparator 333, eighth comparator 334, the ninth comparator 335, tenth comparator 336 receives the value of j. In the second group the input and the fourth group fifth input of the comparator 331 is constant 0. In the second group the input and the fourth group of the sixth input of the comparator 332 is served, respectively, the constant 1 and constant 0. In the second group the input and the fourth group the entrance of the seventh comparator 333 is served according to the government, the constant 2 and the constant 0. In the second group the input and the fourth group of the eighth input of the comparator 334 serves accordingly, the constant 0 and constant 1. In the second group the input and the fourth group entrance of the ninth comparator 335 is constant 1. In the second group the input and the fourth group sign-tenth of the comparator 336 is served, respectively, the constant 2 and the constant 1. Thus, at the outputs of the fifth comparator 331, a sixth comparator 332, the seventh comparator 333, eighth comparator 334, the ninth comparator 335, tenth comparator 336 is formed of a single signal, permitting writing of data and is connected to the inputs of the second register 337, the third register 338, the fourth register 339, fifth register 340, the sixth register 341, the seventh register 342, respectively, to the first group inputs which served code the direction of motion of the pixel. Thus, after reading pane of 6 pixels, defined by coordinates (i,j) (relative to the coordinates of the current pixel (x,y)), group outputs of the second register 337, the third register 338, the fourth register 339, fifth register 340, the sixth register 341, the seventh register 342 written codes of directions of movement of the current pixel of the analyzed sub-regions served by the first group inputs eleventh comparator 343, twelfth comparator 344, trinadcatoj the comparator 345, fourteenth comparator 346, fifteenth comparator 347 and sixteenth comparator 348, the second group inputs are supplied code value movement direction of the current pixel (x,y). Output eleventh comparator 343 signal at the first input of the fourth element And 361 and the third input of the ninth element And 366. From the output of the twelfth comparator 344 signal at the first input of the fifth element And 362, to the second input of the fourth element And 361, to the first input of the sixth element And 363, the second input of the seventh element And 364, at the first input of the eighth element, And 365 and to the first input of the ninth element And 366. Output thirteenth comparator 345 signal to the second input of the fifth element And 362 and the fifth input of the ninth element And 366. Output fourteenth comparator 346 signal at the first input of the seventh element And 364 and the sixth input of the ninth element And 366. Output fifteenth comparator 347 signal to the second input of the eighth element, And 365 and the fourth input of the ninth element And 366. Output sixteenth comparator 348 signal to the second input of the sixth element And 363 and the second input of the ninth element And 366. With the release of the fifth element And 362 signal is supplied to the third input of the sixth element And 363. From the output of the sixth element And 363 of the signal at the third input of the eighth element And 365. From the output of the eighth ELEH the enta And 365 of the signal at the third input of the seventh element And 364. From the output of the seventh element And 362 signal is supplied to the third input of the fourth element And 361. The outputs of the fourth element And 361, the fifth element And 362, the sixth element And 363, the seventh element And 364, the eighth element And 365, the ninth element And 366 are connected respectively to the first inputs of the eighth register 367, ninth register 368, tenth register 369, eleventh register 370, twelfth register 371, thirteenth register 372, the second input of which receives the output signal of the tenth comparator 336, providing the write data to the registers, whose third input signal from the output of the fifth comparator 331, cleansing the contents of the data registers. Thus, at the output of the eighth register 367, ninth register 368, tenth register 369, eleventh register 370, twelfth register 371, thirteenth register 372 is formed in the result of checking the conditions (8)-(12), respectively.

Depending on the conditions (8)-(11) is the increment/decrementvalue fifth counter 35 or the sixth increment of the counter 36, and when the condition (12) is made the jump to check whether this group of pixels of the object. To do this, the output of the eighth register 367 the signal at the second input of the fifth element OR 376 and to the first input of the second element OR 373; output ninth register 368 signal is supplied to pen the first input of the third element OR 374 and to the second input of the second element OR 373; the tenth register 369 signal is supplied to the first input of the fourth element OR 375 and to the third input of the second element OR 373; exit eleventh register 370 signal is supplied to the first input of the fifth element OR 376 and to the fourth input of the second element OR 373; exit twelfth register 371 signal is supplied to the third input of the fourth element OR 375 and to the fifth input of the second element OR 373. As a result, the output of the second element OR 373 when the next pixel belonging to the object, is formed by a single value of the signal which is fed to the first input of the seventh counter 377 storing the number of pixels of the current object, and at the first input of the eighth counter 378, keeping the total number of points in all the found objects. With an output of the third element OR 374 signal, notifying you of the need to increase the abscissa of the pixel (x+i+1, I+j+m) 1, is fed to the first input of the fifth counter 35. From the output of the fourth element OR 375 signal, notifying you of the need to increase the ordinate of the pixel (x+i+1, I+j+m) 1, is fed to the first input of the sixth counter 36. With the release of the fifth element OR 376 signal, notifying you that you reduce the abscissa of the pixel (x+i+1, I+j+m) 1, is fed to the second input of the fifth counter 35. The fifth counter 35 and the sixth counter 36 is reset to the zero state by applying to them the third and second the strokes respectively the output element 323.

At the first input of the ninth counter 379 receives the clock signal CLKY. With a group of seventh output of the counter 377 is the number of points in the current object arrives at the group entrance fourteenth register 380. From the output of the thirteenth register 372 signal is supplied to the second input of the ninth counter 379, the first input of the tenth element And 381 and the first input of the tenth counter 382. To the second input of the tenth element And 381 signal from the first output of the ninth counter 379. The signal output through the tenth element And 381 to the input of the fourteenth register 380, allows the entry of data in the register. The group exit the fourteenth register 380 signal group input buffer element 383, with which he served in the group of input-output of the second RAM 72. With a group of tenth output of the counter 382 the number of the current object is fed to the first group the input of the second multiplexer 384, with the group out of which he comes to group the input RAM 72. Thus, in the RAM 72 records the number of pixels of the current object. With the first and second output ninth counter 379 signals at first and second inputs of the eleventh element And 385, the output of which the signal then goes to the second input of the twelfth element And 386. From the output of the twelfth element And 386 signal permitting/prohibiting writing of data to the WTO the CSOs RAM 72, supplied to the second input of the second RAM 72.

In the first group the input of the fourth adder 313 receives the value 1 with a group of fifth output of the counter 35; the second input of the fourth adder 313 receives the value of x with group of output of the first counter 31. In the first group the input of the fifth adder 314 receives a value from the group of the output of the second counter 32; the second input of the fifth adder 314 receives the value of m with a group of sixth output of the counter 36. With a group of outputs of the fourth adder 314 and the fifth adder 315 pixel coordinates (x+,y+m) are fed to the first and second group of the input data Converter 319, producing the merger of the two data bytes in the word. Inverter output data 319 data is coming to group the input of the second buffer 387, with which the coordinates of the current pixel is coming to group the input-output of the third RAM 73. Address records the coordinates of the current pixel is the current value of the total number of all points of interest, served with a group of eighth output of the counter 378 in the first group the input of the third multiplexer 388, with which it arrives at the group entrance to the third RAM 73. The first group entrance seventeenth comparator 379 receives the value of x with group of output of the first counter 31. In the second group the entrance of the seventeenth comparator 379 p what steps is the group of the output of the second counter 32. At the third entrance of the seventeenth comparator 379 is constant 0. The output of the seventeenth comparator 379 is formed of a single signal when coincidence of the values on all its inputs and fed to the second input of the eighth counter 378 and the second input of the tenth counter 382, reset these counters to zero state.

The entry in the first RAM 71 is made for each processed pixel. To do this, from the output of the element is NOT the signal received at the input of the first RAM 71 and permits the entry of data into the first RAM 71. Further, this same signal is supplied to the first and second inputs of the third buffer element 391, the output of which a signal having a single value, is supplied to the input/output of the first RAM 71. The result in the RAM 71 corresponding to the address generated by the second imaging unit address 318, recorded constant 1, corresponding to the characteristic processing of the pixel.

Permissive signal to write data into the second RAM 72 and the third RAM 73 is a signal generated at the output of the eighteenth comparator 392, the first group whose input is from the sixth group of input MOO 3 enters the number value of the mode of operation of the entire device and to the second input of the constant 2.

The correction module 4 operates as follows. With the first group of input MK 4 to group the input of the first register 453 receives the coordinate value x of the current obrabecim is imago pixel. With the second group of input MK 4 in the first group the input of the second comparator 456 receives the values of the coordinates of the currently processed pixel.

The third entrance MK 4 signal fed to the input of the first register 453. The third group of input MK 4 to group the input of the first register 453 receives the value of the quantity detected in the frame of interest. Thus, the first register 453 stores the value of the number of objects detected in the frame, which moves with his group the first group the first input of the comparator 454. In the second group the input of the first comparator 454 with a group of the output of the first counter 455 is served, the number of the next object being processed. From the output of the first comparator 454, the signal receiving unit value after processing of all the objects supplied to the second input of the first counter 455 and to the first output MK 4. Simultaneously with this, the group output of the first counter 455 the number of the current object is supplied to the first group output MK 4. The third group entrance MK 4 receives the value of the number of pixels of the current object, which is fed to the first group the input of the second comparator 456, the second group whose input is from the fourth group of input MK 4 receives a threshold value that determines the minimum number of pixels in the object at which he h is regarded as an obstacle. The output of the second comparator 456 in case of exceeding the threshold is formed by a single value, which is input to the pulse generator 457 and allows it to work. This is the output of the second comparator 456 is supplied also to the first input of the first flip-flop 461 and resets it to zero state. To group the input of the pulse generator 457 from the third group of input MK 4 receives the number of pixels of the current object. The pulse generator 457 generates at its output the number of pulses coinciding with the number of pixels of the current object. From the output of the pulse generator 457 pulses are received at the first input of the second element And 458, which pulses are received at the first input of the second counter 459. Group output of the second counter 459 is formed the number of the current pixel of the current object being processed, which is fed to the second group the input of the third comparator 460, the first group whose input is from the third group of input MK 4 served total number of points of the current object. After processing all pixels of the current object at the output of the third comparator 460 is formed of a single signal to the second input of the first flip-flop 461 and setting it in one state. At the output of the first flip-flop 461 is formed of a single signal supplied to the second input per the th element And 462 and allow the passage of signals from the first input, connected to the first input MK 4. As a result, the output of the first element And 462 is formed by a pulse applied to the first input of the third counter 465 and increasing the value of the number of objects per unit. The signal from the first input MK 4 is supplied also to the first input of the third element And 483, the second input of which receives the output signal of the second trigger 466. With an output of the third element And 483 signal is applied to a second input of the second element And 458.

With an output of the third comparator 460 signal is also supplied to the second input of the second counter 459 and a single value of the signal resets the second counter 459 in the zero state. From the second entrance MK 4 at the first input of the third counter 465 receives the clock signal CLKZ. To the second input of the third counter 465 output of the second comparator 456 receives the signal, allowing the third increment counter 465. The third counter 465 determines the phase correction value is from 0 to 4.

The number of the current phase correction group with an output of the third counter 465 comes to group the input of the fourth comparator 463, which takes one state at zero numbers mode. The output signal from the fourth comparator 463 routed to the first input of the second trigger 466, which data signal is transferred to the zero state, thereby preventing the processing of the current is th pixel of the current object. Also, this signal is fed to the input of the second register 467, in the group whose input is from the fifth group of the input module MK 4 is supplied to the brightness value of the current pixel. This same value is supplied to group the inputs of the third register 468 and the fourth register 469. To determine the address of the current pixel number value mode group with an output of the third counter 465 arrives at the ninth group input multiplexer 470. From the sixth group of the entrance MK 4 signal is applied to group the input data Converter 471, performs the function of dividing the word of 2 bytes, with the first group out of which the x coordinate is supplied to the first, third, and fourth group the inputs of multiplexer 470 and the first input of the first adder 472. From the second group of output data Converter 471 coordinate value y is supplied to the fifth, sixth, and eighth group of the inputs of multiplexer 470 and the second group the input of the second adder 473. In the second group the input of the first adder 472 and the first group the input of the second adder 473 served the third constant 474 equal to 1. With a group of outputs of the first adder 472 and the second adder 473 values (x+1) and (I+1) respectively received in the second and seventh group the inputs of multiplexer 470. In the first group the output of the multiplexer 470 is formed values that match the values on the PE the PTO, the second, third or fourth group of inputs, the second group the output of the multiplexer 470 is formed values that match the values on the fifth, sixth, seventh or eighth his group inputs, and defined by the value at its ninth group entrance. With the first and second group of outputs of the multiplexer 470 pixel coordinates are received at the first and the second input of the shaper address 475, respectively, the output of which is formed by the address value of the current pixel is supplied to the second group output MK 4. The outputs of the fifth comparator 464 and the sixth comparator 484 formed a single value for room correction stages 1 and 2, respectively, and fed to the inputs of the third register 468 and the fourth register 469, respectively. In the second group the input of the fourth comparator 463, the fifth comparator 464, the sixth comparator 484 serves a constant value specified by the fourth constant 476, the fifth constant 477, fourth constant 478, 0, 1, and 2 respectively.

Thus, in the group outputs of the second register 467, the third register 468 and the fourth register 469 at the end of the three stages of correction of the generated brightness values of the three pixels, defined by coordinates (x,y), (x+1,y) and (x,y+1), served respectively by first, second and third group the inputs of the module emphasizes the Oia contours 479, at the output of which is formed compensated brightness value of the pixel (x,y) in accordance with formula (16), and goes to group the input of the fifth register 480. The fifth register 480 signal at its input supplied with the output of the seventh comparator 481 taking the unit value if the value is 3 to group the output of the third counter 462 supplied to the first group entrance of the seventh comparator 481, at whose second input filed is the fifth constants 482 equal to 3, and writes information on the group the input and output to the third group output MK 4. Simultaneously with the output of the seventh comparator 481 signal is supplied to the second input of the second trigger 466, which translates the trigger is in one state and enable the processing of the next pixel of the current object.

Module underscore circuits (IPC) 479 operates as follows. With the first group of input IPC 479 in the first group the input of the first adder 420 receives the brightness values of the pixel (x+1,y). With the second group of input IPC 479 for the second group the input of the first adder 420 and the first group the input of the second adder 421 receives the brightness values of the pixel (x,y). The third group of input IPC 479 for the second group the input of the second adder 421 receives the brightness values of the pixel (x,y+1). The first adder 420 to the group output form is the duty to regulate the value equal to the difference between values at the first and second group of inputs. The second adder 421 on the group output generates a value equal to the difference of the values at its second and first group inputs. The group output of the first adder 420 is supplied to the first and second group the inputs of the first multiplier 411. The group output of the second adder 421 is supplied to the first and second group the inputs of the first multiplier 412. With a group of outputs of the first multiplier 411 and the second multiplier 412 values are received at the first and second group the inputs of the third adder 417, the output of which is fed to an input of the selection square root 419. Thus, blocks 420, 421, 411, 412, 417, 419 perform the determining gradient values in accordance with the formula (17). Group output module selection square root 419 is served on the first group the input of the third multiplier 413, the second group whose input is from the fourth group of input IPC 479 filed a constant value k1, which determines the degree underscore circuit. Group output of the third multiplier 413 is supplied to the first group the input of the fourth adder 422, the second group the inlet of which a is the group output of the fourth multiplier 414. In the first group the input of the fourth multiplier 414 podes the brightness of the pixel (x,y) from the second group of input IPC 479. In the second group the input of the fourth multiplier 414 from the fifth group of input IPC 479 filed a constant value k2, which determines the degree underscore circuit. Group output of the fourth adder 422 is formed corrected brightness value of the pixel.

All modules of the device, except for the image sensor can be implemented in a programmable logic integrated circuit, the average degree of integration that will ensure high technical and economic performance of the device.

The periods of repetition of the clock signals should be connected by the following relations

signals CLK, CLK/3, CLK/25

TCLK=3*TCLK/3,

TCLK=25*TCLK/25,

where TCLK, TCLK/3, TCLK/25the periods of repetition of the clock signals CLK, CLK/3, CLK/25, respectively;

signals CLKX, CLKX6

TCLKX=6*7CLKX6,

where TCLKX, TCLKX- periods of the sequence of clock signals CLKX, CLKX6 respectively.

The periods of repetition of the clock signals CLK, CLKX, CLKY, CLKW, CLKZ is no Association between time constraints and are chosen when implementing device compensation of the image blur moving objects on the basis of specific components.

The invention provides for compensation of the image blur of moving objects in real time and can be used to correct the claim is each of the images in the video sensor, made on the basis of solid matrix of sensors of different types, vision systems, as well as the means of video information display - liquid crystal displays.

1. The compensation of the image blur moving objects, including calculating the difference between the measured brightness of the pixels of the image and a previously obtained its assessment based on the sequence of previous frames, the motion is detected by comparing the difference with a threshold value, characterized in that it further reads the image, determine the direction of each pixel, combine moving in the same direction adjacent pixels in the object, perform underline the contours of moving objects by adding them to the source B(k) and gradient ▿(B(k)) of the image forming output image

where k1, k2- weights.

2. The device for implementing the method according to claim 1, containing an image sensor (DI), characterized in that it introduced the controller module motion detection (MOD), the module object definitions (LEAs), the correction module (MK), the first RAM, the second RAM, the third RAM, counter, element, OR, the first comparator, the first multiplexer, the second multiplexer, the third multipl the CRRF, the fourth multiplexer, the fifth multiplexer, a sixth multiplexer, the seventh multiplexer, the first demultiplexer, the second demultiplexer, the input DI and the first input of the controller are the clock inputs CLK-RW, group output DI is connected to the first group the input of the controller, the second group output controller connected to the first group the inputs of the first multiplexer and a third multiplexer, group output of the first multiplexer is connected to the input of the first group of RAM, a group of input-output of the first RAM is connected to the input of the first group demultiplexer and to group the output of the fifth multiplexer, the first group output of the first demultiplexer connected to the fourth group to the input of the controller, group input-output of the second RAM connected to group the input of the second demultiplexer and to group the output of the sixth multiplexer, the third group controller output is connected to the system bus, the fourth group controller output is connected to the first group to the sixth input of the multiplexer, the first group output controller connected to the first group to the input of the fifth multiplexer, the first output of the controller is connected to the first input of the second multiplexer, the output of the second multiplexer is connected to the input of the first RAM, the second output controller connected to the first the course of the fourth multiplexer, the output of which is connected to the input of the second RAM, the second and third group PLC inputs are constants (H-1) and (Y-1), respectively, the second input of the controller and second input MODES are clock inputs CLK, the third input of the controller is connected to the output of the first comparator, the first group whose input is connected to group the output of the meter and the fifth group input MODES, the second group the input of the first comparator filed with the constant 0, the third output of the controller is connected to the first input element OR the first entry MODES is the clock input CLK/25, the first, second group the input MODES are designed to supply constant (X-3) and (Y-3), respectively, the third group sign MOU connected to group the output of the second demultiplexer, the fourth group sign MOU is connected to the second group to the output of the first demultiplexer, the first group output MODES connected to the second group to the inputs of the first multiplexer and a third multiplexer, a second group of the output MODES is connected to the second group to the entrance of the seventh multiplexer, the third group output MODES connected to group input-output RAM and the first group to the entrance of the IPO, the first release of the MOD is connected to the second input element OR the second output MODES connected to the entrance of the seventh multiplexer, the third output MODES connected to the input of the third RAM, second itrate group inputs LEAs are designed to supply constant (X-2) and (Y-2), respectively, the fourth group entrance LEAs connected to the first group out of the MC, the fifth group entrance LEAs connected to the fourth group MK outlet, the sixth group entrance LEAs connected to group the output of the counter, the first, second and third inputs of the IPO are intended to supply clock signals CLKX, CLKX6, CLKY, respectively, the first group output LEAs connected to the first group to the entrance of the seventh multiplexer, group output of which is connected with the entrance to the third group of RAM, the second group output LEAs connected to the first group entry MK, the third group output LEAs connected to the second group to the entrance of MK, the fourth group output LEAs connected to the third group input MK, the output of the NGO is connected to the third input of the OR element and to the third input of the MC, the fourth input element OR is connected to the output of the MC, the second group output MC connected to the third group input of the first multiplexer, the third group output MC connected to the second group to the input of the fifth multiplexer, the fourth group entrance MK, served a threshold P value that specifies the minimum number of pixels in the object, the fifth group entrance MC connected to the third group the output of the first demultiplexer, the first and second inputs MK are used to supply a clock signal CLKW and CLKZ, respectively, on the second input W is the second multiplexer filed with the constant 0, group the output of the counter is connected to the fourth group input of the first multiplexer, group the input of the second multiplexer, the third group to the input of the third multiplexer, the fifth group to the input of the fourth multiplexer, the third group to the input of the fifth multiplexer to the second group to the sixth input of the multiplexer, and the second group the inputs of the first demultiplexer and the second demultiplexer, the second, third, and fourth inputs of the fourth multiplexer is constant 0, the first multiplexer provides the signal with its first group of input on your group output at "0" on his fourth group the entrance, with his second group sign - in the value "1", from their third group of entry - when set to "3", the second multiplexer provides the signal with its first group of input on your group output at "0" at its third group the entrance, with his second group of input - when set to "3", the third multiplexer provides the signal with its first group of input on your group output at "0" at its third group the entrance, with his second group of input - when set to "1", the fourth multiplexer provides the signal with its first FCU the model input on your group output at "0" at its fifth group the entrance, with his second group of input - when set to "1", from their third group of entry - when set to "2", from their fourth group of input - when set to "3", the fifth multiplexer provides the signal with its first group of input on your group output at "0" at its third group the entrance, with his second group of input - when set to "3", the sixth multiplexer provides the signal with its first group of input on your group output at "0" at its second group, first demultiplexer delivers the signal from your group log on to the first group output at "0" at its second group input, a value of "1" - on his second group output, when the value "3" is on its third group output, the second demultiplexer provides the signal from your group log on to your group output when set to "1" at its second group the entrance, the seventh multiplexer provides the signal with its first group of input on your group output at "0" at its input, and the second group sign - in the value "1".



 

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