Method of digital information storage

FIELD: information technology, physics.

SUBSTANCE: Boolean logic function is constructed when recording the memorising information in the accomplished normal disjunctive form. The argument of this form is the address of memorised information and its value is the memorised information. After that the Boolean logic function gets converted into Zhegalkin polynomial, then the number of elementary Boolean operations, being a part of Zhegalkin polynomial, gets minimised, and then the minimised Zhegalkin polynomial gets realised on the programmed integrated circuit logic.

EFFECT: decrease of general-circuit expenditures for memorising the digital information.

2 tbl

 

The invention relates to the field of digital computer technology and can be used for storing digital information.

The method described in this application can be used in computer systems with programmable logic integrated circuits (FPGA). In such schemes may change the pattern of connections between logic elements, which provides the possibility of technical realization of different logic functions. The set of combinations of these links allows you to save and store large amounts of digital information.

There is a method of storing digital information, namely, that at the specified address selects a specific memory cell, which is then stored digital information (Alekseenko A.G., Sagarin I.I. Microcircuitry. The textbook. manual for schools. Ed. Ipplepen. - M.: Radio and communication, 1982, str).

The disadvantage of this method is the large number of memory cells and large hardware costs required to memorize large amounts of information, because for storing one bit of information requires one memory cell.

Closest to the proposed method is a method of storing digital information (prototype), which consists in the fact that when writing stored information based function, the parameters of which is set depending on the stored information, information is stored in the form of a circuit implementation of the built in functions, and when reading the stored information is restored by the values of this function [Kohonen So Associative storage device: TRANS. from English. - M.: Mir, 1982, p.39-45].

The disadvantage of this method is the large circuit costs when memorizing a large amount of digital information, as the complexity of the circuit implementation of the built in functions can be large.

The purpose of the invention is reducing the circuit cost and, thereby, increasing the volume of stored digital information by storing digital information in the FPGA in the form of minimized Boolean logic functions.

To achieve the goal of the proposed method lies in the fact that when writing stored information based function, the parameters of which are set depending on the stored information, the information is stored in the form of a circuit implementation of the built in functions, and when reading the stored information is restored by the values of this function. New is the fact that stored information is based Boolean logic function in a perfect disjunctive normal form, the argument which is the address of the stored information, and the value is memorized information, then bule is Skye logical function is converted to the form of the polynomial Zhegalkin, further minimizes the number of elementary Boolean operations included in the polynomial Zhegalkin, and then minimized polynomial Zhegalkin is implemented on a programmable logic integrated circuit.

The proposed method of storing digital information is as follows.

When recording information on the stored digital information is based Boolean logic function in a perfect disjunctive normal form (SNDF)whose values are equal to the bits of stored information. When setting the serial quantities of argument Boolean function values are equal to-remember information. To remember this digital information is represented as a truth table. The truth table (table 1) Boolean logic function consists of two columns. In the left column are the memory address or the value of the binary m-bit argument or variable x1x2x3...xmBoolean functions, and in the right bits of the stored digital information or the value of a Boolean logic function y=f(x1x2x3...xm)=0,1.

Boolean logical function is constructed in SDP (1) in the following order. Written disjunction of conjuncti all bits of the argument Boolean function for values of the argument, in which Boolean logic function is according to the truth table takes the value of 1. Then the sign inversion on those bits of the argument, which is equal to 0 in the truth table.

Table 1
x1x2x3...xmy
000...0f(000...0)
100...0f(100...0)
010...0f(010...0)
111...1f(111...1)

Next, a Boolean logic function is converted to the form of the polynomial Zhegalkin

where ai=0,1, i=1...n, n=2m- the maximum number of conjuncti in polynomial Zhegalkin of m variables, and ⊕ - the operation of summing modulo two.

To do this, convert all the operations of disjunction and inversion in equation (1) are replaced by the operations of addition modulo two and a conjunction according to the formula

and then there are such members.

In the polynomial Zhegalkin (2) from m independent input variables x1x2x3...xmcontains no more than n=2mconjuncti input variables connected by operation of summing modulo two. The number of elementary the x Boolean operations, included in the polynomial Zhegalkin (2)is not more than 2m-1<n operations of addition modulo two and no more than

the logical multiplication, and hence, not more than n1=(m+2)·n/2 elementary Boolean operations.

Then the polynomial Zhegalkin minimize the number of incoming elementary Boolean operations. Note that the polynomial Zhegalkin containing all sorts of conjunction (ai=1, i=1...n), is identically equal to the conjunction of all the variables are taken from the inversion, that is,

The procedure of minimization of the polynomial Zhegalkin is as follows.

Step 1. First calculate the number of elementary Boolean operations n1in the polynomial Zhegalkin (2).

Then do the identical transformation of the polynomial Zhegalkin (2)

where bi=andi⊕1, i=1...m.

Calculate the number of elementary Boolean operations n2in the expression (7). If n1≤n2then the polynomial Zhegalkin (2) remains unchanged, otherwise the polynomial (2) replaceable identical to expression (7).

Since n1+n2=(m+2)·n/2, and selects min{n1n2}, then the resulting expression (2) or (7) will contain no more than n3=(m+2)·n/4 elementary Boolean operations.

Step 2. Then doubt the remaining members without changing the polynomial Zhegalkin (2), either polynomial Zhegalkin included in the expression (7)

divide into two groups or two new polynomial Zhegalkin. In the first polynomial Zhegalkin y2 group members, which includes the multiplier x1(or x2, x3... ), while in the second polynomial Zhegalkin y3 - members, which does not include the multiplier x1.

When setting out the common factor x1in the polynomial (9) the number of elementary Boolean operations is reduced by the number of disjunctive in this polynomial.

Step 3. The procedure of minimization of the polynomial Zhegalkin ends when the polynomials Zhegalkin type (9) and (10) will contain no more than one member, otherwise go to step 1 procedures for minimizing polynomials (9) and (10).

After the minimization procedure will get a polynomial of the following form

where fiei=0,1.

When performing steps 1 and 2 of the procedure to minimize the number of elementary Boolean operations is reduced by half compared with the maximum possible number for a given number of independent variables of the polynomial Zhegalkin, however, the number of polynomials Zhegalkin doubled.

From the expression (11) recurrence relation for the number of elementary Boolean fu the capabilities of S mwhen performing the minimization procedure will be written

here

Then, after the minimization procedure after m-1 steps we have

Therefore, the number of elementary Boolean operations after minimization can be estimated by the value

Thus, for storing n bits of information used is minimized Boolean function, which requires no more than O(n) elementary Boolean operations.

Then is the circuit implementation of the minimized Boolean functions, for example, on the FPGA, as described in Knyshov D.A., Kuselan MO FPGA company "XILINX": the description of the structure of the main collections. - M.: Publishing house "Dodeca-XXI, 2001.

For storing n bits of information FPGA should allow to implement Boolean logic function with O(n) elementary Boolean operations. The criterion for the end of the procedure of minimization of Boolean logic functions can be obtaining polynomial Zhegalkin with O(n) and less elementary Boolean operations.

The complexity of the technical realization of elementary Boolean operations approximately commensurate with the complexity of the implementation of one memory cell, which, however, in the known method additionally requires the decoding of this memory cell. Therefore, if the complexity of the technical realization of the proposed method of storing digital information is of the order O(n), the complexity of the technical realization of the way in which information is stored in the memory cells is of the order O(m·n), so as to implement a memory cell requires 1 elementary Boolean function and to implement this decoder memory cell m-1 elementary Boolean functions. Since O(n)<<O m·n), the proposed method is simpler.

As an example, consider the case when stored 16 bits of information 1010011100101101. This information is addressed 4 independent Boolean variables, and the truth table for it are presented in table 2. Boolean logical function in SNDP will be written

Using formula (3) after reduction of similar terms, one can obtain a polynomial Zhegalkin

contains 21 elementary Boolean operation.

Minimize this polynomial. Because the number of members in the polynomial Zhegalkin equal to 11, more 16/2=8, we represent the polynomial Zhegalkin

Table 2
x1x2x3x4y
0000 1
10000
01001
11000
00100
10101
01101
11101
00010
10010
01011
11010
00111
10111
01110
11111

The number of elementary Boolean operations in the last expression is equal to 13. Convert it according to the procedure of minimization of the following form

containing 10 elementary Boolean operations.

Thus, for storing the specified 16 bits of information required circuit implementation of all 10 elementary Boolean operations, which is considerably lower than that needed for the implementation of the 16 memory cells and decoder to these memory cells (64 elementary Boolean operations).

With the increase in the volume of stored digital information gain in the circuit implementation costs of the proposed method increases.

In the proposed method, digital information volume of n bits remembers who I am in the FPGA in the form of minimized Boolean logic functions, circuit complexity is to remember any information no more than O(n) elementary Boolean operations that significantly less circuit complexity of order O(m·n) of storing digital information in a separate memory cells. For example, circuit cost when implementing a memory capacity of 1 GB can be reduced by approximately 30 times. In addition, circuit complexity depends on the specific type of information, and for information, which correspond to simple Boolean functions, will be negligible, but in any case will not exceed the value O(n).

Achievable technical result of the proposed method is to reduce circuit cost of storing digital information.

The method of storing digital information, namely, that when writing stored information based function, the parameters of which are set depending on the stored information, the information is stored in the form of circuit implementation built functions and when reading the stored information is restored by the values of this function, characterized in that stored information in the computer system based Boolean logic function in a perfect disjunctive normal form, the argument which is the address of stored information, and the value is stored information, then the Boolean logic function is converted to the form of the polynomial Zhegalkin, further minimizing the number of elementary Boolean operations included in the polynomial Zhegalkin, and then minimized polynomial Zhegalkin is implemented on a programmable logic integrated circuit.



 

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