Method for producing cmos transistor gate regions

FIELD: microelectronics; complementary metal-oxide-semiconductor transistors.

SUBSTANCE: proposed method for producing CMOS transistor gate regions includes formation of regions of second polarity of conductivity, insulator, and gate silicon dioxide in substrate of first polarity of conductivity, deposition of polycrystalline silicon layer, its doping, formation of gate regions of p- and n-channel transistors, thermal cleaning in trichloroethylene and oxygen, deposition of separating silicon dioxide, modification, formation of drain and source regions of both polarities of conductivity, thermal cleaning in trichloroethylene and oxygen, deposition of pyrolytic insulating silicon dioxide, its modification by thermal firing in trichloroethylene and oxygen, opening of contact windows, metal deposition, and process operations (removal of natural silicon dioxide, formation of gate silicon dioxide, formation of polycrystalline silicon layer) conducted within single vacuum cycle of one reactor, whereupon polycrystalline silicon layer is doped.

EFFECT: improved and regulated electrophysical properties of gate silicon dioxide enabling enhancement of threshold voltage reproducibility and yield.

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The scope of the invention is microelectronics, namely the technology of manufacturing the IC and can be used in the manufacture of BIP, MOS, CMOS, and BiCMOS devices.

One of the features of manufacturing the MOS transistor is the formation of a high quality dielectric, having a minimum density porosity, effective, moving charges and stability properties at the physico-thermal treatments. Of particular urgency is the quality of the gate dielectric layers defining mainly the efficiency of the device.

There are various technological options for making a MOS, CMOS, BiCMOS devices: Technology VLSI. Edited SSI, book 2, Moscow, Mir, 1986, SS-248, [1]; U.S. Pat. U.S. No. 5422290, H 01 L 21/265, 1995. [2], Gianrico.

Constructive and technological features of submicron MOSFETs. Part 1, "Technosphere", Moscow, 2002, p.137, [3].

However, various technological options for the production of MOS, CMOS, BiCMOS devices inherent characteristic. The sealing region such devices are made identical and consists of the following operations: chemical cleaning of the substrate; forming a gate silicon dioxide, forming a layer of conductor shutter and forming by photolithography packing areas. The disadvantages of the existing methods have formed the project of the sealing areas is that what: there is no cleaning of the substrates from natural silicon dioxide, which is formed with a thickness (8-12)And the atmospheric air with unmanaged properties density effective and moving charges within the period specified holding time storage of substrates (including infrastructure) before formation of the gate silicon dioxide; after forming the gate silicon dioxide there is also the Ministry of amelioration and before forming the polysilicon, during which the gate dielectric is exposed to uncontrolled external atmosphere, negatively affecting its electrical properties; forming a gate silicon dioxide and polysilicon posted at the place of their formation (gate silicon dioxide is formed on the same hardware, and polysilicon on the other, which necessitates including infrastructure, during which the gate silicon dioxide is exposed to uncontrolled external atmosphere, negatively affecting its quality.

There is a "Method of manufacturing semiconductor device" Japan's bid No. 60-38482 B4, H 01 L 27/092 [4], including the formation of the substrate of the first conductivity type regions of the second conductivity type, protivoradarnyh regions of the first type conductivity, dielectric isolation between the transistor structures, the formation of pojat the priori of silicon dioxide, forming a gate conductive layer regions, forming by photolithography gate regions of p - and n - channel transistors, the formation of sinks and sources of the second conductivity type in regions of the first conductivity type, the formation of sinks and sources of the first conductivity type in regions of the second conductivity type, forming a pyrolytic silicon dioxide, anisotropic etching which is forming on the side walls of the sealing areas of the separation of silicon dioxide, the formation of titanium silicide on the bolt, stock and stokovyh regions, forming an insulating dielectric, opening contact Windows, and forming a metallic wiring.

The disadvantage of this method [4] is the lack of cleaning substrates from natural silicon dioxide and posted at the place of formation of the gate silicon dioxide and a layer of polycrystalline silicon (gate dielectric and a layer of polycrystalline silicon are formed on different plants), resulting in contact of the substrate with uncontrolled external atmosphere. The closest analogue adopted us for the prototype, is a Method of manufacturing integrated circuits on the CMOS transistors", U.S. Pat. Of the Russian Federation No. 2185686, H 01 L 21/8238, 1992 [5], including the formation of the substrate of the first conductivity type regions of the second type p is ultimate, protivoradarnyh regions, dielectric isolation, the formation of the gate silicon dioxide, forming a layer of polycrystalline silicon, its doping, the formation of the gate regions of the n - and p - channel traistaru, thermal cleaning of the surface of the wafer in a gas mixture of trichloroethylene with oxygen (TAE+O2), sedimentation separation of silicon dioxide on the vertical walls of the closures by the pyrolysis of organosilicon compounds, modifying its thermal annealing in a gas mixture of trichloroethylene with oxygen, forming areas of sinks and sources of the second conductivity type in the substrate of the first conductivity type, the regions of sinks and sources of the first conductivity type in regions of the second type conductivity, thermal cleaning of the surface of the wafer in a gas mixture of trichloroethylene with oxygen, pyrolysis deposition of insulating silicon dioxide, modified its thermal annealing in a gas mixture of trichloroethylene with oxygen, opening contact Windows and metallization.

The disadvantage of this method [5] is the lack of clean plates from natural silicon dioxide prior to formation of the gate silicon dioxide, and the formation of the gate silicon dioxide and a layer of polycrystalline silicon is posted at the place of their formation (the formation of the E. gate of silicon dioxide and a layer of polycrystalline silicon is performed at different process units), which leads to the negative impact of uncontrolled external atmosphere on the electrical properties of gate silicon oxide, consisting in non-repeatable threshold voltages of the MOS transistors, which reduces the yield of IC.

The technical result of the invention is to eliminate the disadvantages of the prototype, leading to the improvement and stabilization of the electrical properties of gate silicon dioxide, which increases the reproducibility of the threshold voltage, resulting in increased yield of IC.

The essence of the invention is that the process operations: natural etching of silicon dioxide, forming a gate silicon dioxide and a layer of polycrystalline silicon is carried out in a single vacuum cycle, a single reactor without contact with the external environment (i.e. the above-mentioned group a group of processing operations performed in one working volume within which the substrate is not exposed to uncontrolled external environment). After chemical treatment of the substrates, they are loaded into the reactor, the latter is pumped to a pressure of 500 PA, the reactor serves gaseous hydrogen fluoride diluted with argon (1:10). In pairs gaseous hydrogen fluoride is a natural etching of silicon dioxide. Then the reactor PR is duvaut argon with pumping, stop the flow of argon into the reactor an oxygen stream which is formed the gate silicon dioxide, the temperature of the reactor to reduce the temperature of formation of the gate silicon dioxide to a temperature deposition of a layer of polycrystalline silicon with the pumping of the reactor with argon. Stop the flow of argon and the reactor serves monosilane and form a layer of polycrystalline silicon. Stop the supply of monosilane, pumped to the reactor with argon, produce depressurization of the reactor and unload the substrate. Alloyed layer of polycrystalline silicon by photolithography to form gate region of the MOS transistor. Gate silicon dioxide may be formed in the oxygen flow, and the flow of gas mixture of trichloroethylene with oxygen.

Thus, the hallmark of the invention is that of forming the gate regions of the MOS transistors of the group of technological operations: removing the natural oxide, forming a gate silicon dioxide layer of polycrystalline silicon are carried out in a single vacuum cycle one reactor. These three processes are integrated in a single reactor, during these processes, the substrate is not in contact with uncontrolled external environment that improves the quality of manufacturing pozzato the aqueous silicon dioxide and increase the percentage yield of the IC. This set of distinctive features allows to solve the problem.

Figure 1-3 shows the basic steps of manufacturing a CMOS transistor with a gate regions according to the invention.

Figure 1 presents a section of the structure where the semiconductor substrate 1 is formed a pocket p-type conductivity 2, formed of dielectric insulation 3, formed protivokomarinye region 4 and in the same vacuum cycle removed natural silicon dioxide, formed gate silicon dioxide 5, polycrystalline silicon 7 and after his doping by photolithography formed gate region of the p - and n - transistors. At the gate areas formed by dividing the dielectric 7.

Figure 2 presents the incision patterns, where in the pocket of n-type conductivity formed effluents-sources 8 p-channel transistor, and in the pocket p-type conductivity formed effluents-sources 9 n-channel transistor.

Figure 3 presents the incision patterns which are formed of insulating dielectric 10, the opened contact window and formed metallization 12 p-channel transistor and the metallization 11 n-channel transistor.

1. Example. On a single crystal substrate EFC-4,5 (100) formed of silicon dioxide with a thickness 0,165 mm at T=920°With water vapor. Through photolithography and the silicon dioxide is cracked open under the n-pocket and ion doping with E=60 Kev and D=0,8 µc/cm 2introduced phosphorus. After chemical treatment formed of silicon dioxide of a thickness of a 0.035 μm at T=950°With oxygen. Through photolithography and the silicon dioxide cracked open under the p-pocket and ion doping with E=100 Kev and D=2,2 µc/cm2introduced boron. After chemical treatment produced the bulk impurity at T=1150°C for 17 h in oxygen. It was received the following parameters: resistance of the n-pocket - (800±50) Ohm/sq; the resistance of the p-pocket (2000±150) Ohm/sq; the depth of the p-pocket (5±of 0.2 μm. Was stravovali silicon dioxide and after chemical treatment has formed a double dielectric: silicon dioxide with a thickness of 0.04 μm in trichloroethylene (TAE) with oxygen; silicon nitride with a thickness of 0.12 μm at T=800°and the pressure (P) in the reactor 20 PA. In two-layer dielectric cracked open under the local oxidation and ion doping of boron with E=20 Kev and D=10 µc/cm2formed p-protection. Conducted local oxidation under the protection of silicon nitride at T=920°P=10 ATM water vapor, the thickness of the silicon dioxide was (0,65±0,05) μm, the resistance of the p-security areas (5±1,5) ohms/sq, and the depth (1,5±to 0.3 microns). After chemical treatment of the substrates, the latter was loaded into the reactor and led a group of technological operations: a) destruction of natural silicon dioxide in vapor gaseous hydrogen fluoride is, diluted with argon 1:10=HF:Ar at T=800°and P=500 PA for 5 min; b) blew the reactor with argon for 10 min, was applied to the reactor oxygen and formed a gate silicon dioxide with a thickness of 0.015 mm at the same temperature at P=1000 PA for 150 min; (C) purging with argon reactor at last reduced temperature T=800°C to T=620°S, was applied to the reactor monosilane flow rate of 15 l/h and formed a layer of polycrystalline silicon with P=40 PA thickness of 0.5 μm. The substrate unloaded from the reactor and perform the doping of the layer of polycrystalline silicon from PCl3at T=920°With resistance polysilicon - (17±3) Ohms/square by photolithography formed mask gate region of the p - and n-channel transistors and plasma-chemical etching (PCTs) in SF6+O2etched polysilicon with P=(2-3) PA and RF power discharge 100 watts, after chemical treatment of the substrates was performed heat treatment of the substrate at T=850°in TAE+O2(20-30) minutes flocked to silicon dioxide by pyrolysis of tetraethylorthosilicate (TEOS) at T=720°and P=80 PA thickness (0,2±0,02) μm, produced its modification by thermal annealing at T=900°in TAE+O2within 30 minutes the Reaction ion etching in CHF3+CF4+Ar at P=(60-70) PA and RF power discharge (350-380) W pyrolysis of silicon dioxide formed on the side walls of the Ah gates separating the dielectric. The photolithography opened window under stock and ishikawae the region of n-channel transistor and ion doping successively introduced phosphorus with E=40 Kev and D=15 µc/cm2and arsenic with E=100 Kev and D=800 µc/cm2and conducted thermal annealing at T=500°, 60 minutes by photolithography opened window under stock and ishikawae region of the p-channel transistor and ion doping was introduced boron with E=25 Kev and D=500 µc/ cm2conducted thermal cleaning of the substrate at T=850°C, 30 minutes in trichloroethylene with oxygen. Besieged pyrolytic silicon dioxide from TEOS at T=720°and P=80 PA thickness of 0.5 μm, was performed annealing of deposited silicon dioxide in TAE+O2at T=900°C, 30 min plasma-Chemical etching opened the window to the p - and n-channel transistors, the deposited aluminum and etching of aluminum formed layout.

Sources of information

1. The VLSI technology. Edited SSI, book 2, Moscow, Mir, 1986, s-248.

2. Pat. U.S. No. 5422290, H 01 L 21/265, 1995.

GY Krasnikov. Constructive and technological features of submicron MOSFETs. Part 1, "Technosphere", Moscow, 2002, p.137.

3. Japan's bid No. 60-38482 B4, H 01 L 27/092.

4. Pat. Of the Russian Federation No. 2185686, H 01 L 21/8238, 1992 prototype.

1. Method of forming gate regions of the MOS transistor, including forming the substrate of the first conductivity type regions Vtorov what type of conductivity, protivoradarnyh regions, dielectric isolation, the formation of the gate silicon dioxide deposition of a layer of polycrystalline silicon, its doping, the formation of the gate regions of p - and n - channel traistaru, thermal cleaning of the substrate surface in trichloroethylene with oxygen, sedimentation separation of silicon dioxide on the vertical walls of the closures by the pyrolysis of organosilicon compounds, modified its thermal annealing in trichloroethylene with oxygen, forming areas of sinks and sources of the second conductivity type in regions of the first conductivity type, forming areas of sinks and sources of the first conductivity type in regions of the second type conductivity, thermal cleaning of the surface of the substrate in trichloroethylene with oxygen, the deposition of pyrolytic insulating silicon dioxide, modificatio its thermal annealing in trichloroethylene with oxygen, opening contact Windows and the metallization, wherein the process steps: removal of natural silicon dioxide, forming a gate silicon dioxide, forming a layer of polycrystalline silicon is carried out in a single vacuum cycle, one reactor, after which the alloyed layer of polycrystalline silicon.

2. The method according to claim 1, characterized in that the formation of the gate dioxi is and silicon is carried out in oxygen.

3. The method according to claim 1, characterized in that the formation of the gate silicon dioxide is carried out in a gas mixture of trichloroethylene with oxygen.

4. The method according to any one of claims 1 to 3, characterized in that after forming a gate silicon dioxide the temperature in the reactor to reduce the temperature polysilicon deposition.



 

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