Multichannel reader

FIELD: optical data processing systems.

SUBSTANCE: proposed multichannel reader built on semiconductor substrate has N input units, multiple-output switching unit, common read-out bus, write bus, pre-processor signal processing unit incorporating comparator, arithmetic-logic device, and memory unit; one of two comparator inputs is designed to apply digital-code signal thereto and is connected to common read-out bus; other comparator input is designed to feed reference signal; comparator output is connected to input of arithmetic-logic device whose output is connected to input of memory unit whose output is coupled with write bus; each input unit is made in the form of amplifier that has input, output, and control input, as well as two MIS transistors; first MIS transistor gate is connected to output of respective cell of multiple-output switching unit and gate, to common read-out bus; second MIS transistor gate is connected to output of next cell of multiple-output switching unit and gate, to write bus; each input unit is provided in addition with K-capacity analog-to-digital converter and L-capacity digital-to-analog converter; first MIS transistor source is connected to output of analog-to-digital converter whose input is connected to amplifier output; second MIS transistor source is connected to input of digital-to-analog converter whose output is connected to amplifier control input; common read-out bus is assembled of K buses, K being equal to capacity of analog-to-digital converter and to number of first MIS transistors connected through their gates to respective outputs of multiple-output switching unit, through drains, to respective buses of common read-out buses, and through sources, to respective inputs of analog-to-digital converters; write bus is assembled of L buses, L being equal to digital-to-analog converter capacity and to number of second MIS transistors connected through drains to respective buses forming write bus, through gates, to output of next cell of multiple-output switching unity, and through sources, to respective inputs of digital-to-analog converter.

EFFECT: extended dynamic range, enhanced speed, enlarged functional capabilities.

1 cl, 1 dwg

 

The invention relates to integrated microelectronics and can be used in processing systems optical data.

Photosignal with multiple sensors, in particular for infrared photodetectors (IR FPU), especially in the middle and far IR range, low contrast, high levels of geometric noise. Therefore, an integral part of modern multi-element IR FPU third generation is the realization of complete systems, including preprocessing processing of information from multiple sensors in digital form (L.J.Kozlowski, .Vural at all. Progress toward high-performance infrared imaging systems-on-a chip. Proceeding of SPIE, vol.4130 (2000), p.245-253).

Known multi-reader (A.S. USSR №1702829, IPC: 6 H 01 L 29/768), performed on the semiconductor substrate containing mnogolyudnoe switch, range of N amplifiers, a common bus read, bus write, the block preprocessing signal processing with the signal input and a compensating output.

A disadvantage of the known device is the limitation of the dynamic range, performance, functionality preprocessing signal processing. The disadvantage is due to the fact that the information signal and the correction voltage is transmitted in analog form and is Asano to this particular reader, and preprocessing signal processing in analog form, serial converting the analog signal to digital.

The closest technical solution to the claimed is multi-reader (III, Mphepo. Multiple-input processor with adaptive devices preprocessing signal processing for multi-element sensors. Avtometrija, No. 6, 1997, p.20-25), is performed on the semiconductor substrate containing N input nodes, mnogolyudnoe switch, a common bus read, bus write, the block preprocessing signal processing, contains a comparator, an arithmetical and logic unit, a memory unit, and of the two inputs of the comparator, one is to feed it signal into a digital code and connected with a common bus read, and the other comparator input is designed to supply the reference signal, the comparator output is connected to the input of arithmetical-logical unit, the output of which is connected to the input of the memory block, and the output of the memory block associated with the bus entries, each input node is made in the form of an amplifier having input, output and control input, two MOS transistors, the gate of the first MOS transistor is connected to the output of the corresponding cell mnogolyudnogo switch, and the drain - General bus read, the gate of the second MOS transistor is connected with in the course of the next cell of mnogolyudnogo switch and the flow - bus write. The source of the first MOS transistor is connected to the output of the amplifier, and the source of the second MOS transistor is connected with the control input of the amplifier. The amplifier is made on the basis of the input block with direct injection on the charge-coupled devices and United with him three MOS transistors. Block preprocessing signal processing in addition to the above elements contains a digital to analog Converter (DAC)through which the output of the memory block associated with the bus is in write mode, with the output of the memory block is additionally associated with arithmetical-logical unit. One of the inputs of the comparator that is used to feed the signal into a digital code, is connected with the common bus read through serially connected analog-to-digital Converter (ADC), the node correlated double sampling and the preamplifier.

This known device operates as follows. The amplifier input is connected to the sensors. Mnogolyudnoe the switch provides a serial connection of the outputs of the amplifier through the first MOS transistor on a common bus read. The signal in analog form is fed to the input of the ADC, the ADC output on the comparator. To the second input of the comparator receives the reference code. Depending on the ratio of the information signal and the reference code at the output of the comparator will be generated codes: +1 if Uwhitefish<Uop; - U whitefish>Uop; 0 if Uwhitefish=Uod.When code +1 information in the i-th cell of the memory block (RAM) is increased by the increment LSB of RAM, and if code -1 decreases. In the next cycle by reading the information signal from the i+1 cell amplifier (input node) corrected voltage value of the i-th cell of the amplifier via the bus entry and second MOS transistors is supplied in analog form to the control input of i-amplifier, which stores it in analogue form before the next cycle of reading (correction). At constant maximum signal through the 2ncycles of reading, where n is the bit width of the RAM potentials on all control inputs of the input nodes will be formed in such a way that the output signals on the shared bus read with accuracy to the LSB of the ADC will be equal to the reference regardless of current-voltage characteristics of the attached sensors to the inputs of the amplifiers and the heterogeneity of the transmission characteristics of the amplifiers. The sensors can be, in particular, IR photodetectors.

The disadvantage of the closest technical solution is to limit the dynamic range, performance and functionality. The limitation of the dynamic range due to the fact that the information signal and the correction voltage is passed to the analogue to the new form. The limit speed is a limitation of the speed signal transmission due to the need serial conversion of the analog signal in digital form. The functionality is limited due to preprocessing signal processing in analog form.

The technical result of the invention is the expansion of dynamic range, improved performance and enhanced functionality.

The technical result is achieved by the fact that in multi-channel reader, performed on the semiconductor substrate containing N input nodes, mnogolyudnoe switch, a common bus read, bus write, the block preprocessing signal processing, contains a comparator, an arithmetical and logic unit, a memory unit, and of the two inputs of the comparator, one is to feed it signal into a digital code and connected with a common bus read, and the other comparator input is designed to supply the reference signal, the comparator output is connected to the input of arithmetical-logical unit, the output of which is connected to the input of the memory block, and the output memory block associated with the bus entries, each input node is made in the form of an amplifier having input, output and control input, two MOS transistors, the gate of the first MOS transistor seediness the output of the corresponding cell mnogolyudnogo switch and Stoke - on with a shared bus read, the gate of the second MOS transistor is connected to the output of the next cell of mnogolyudnogo switch, and the flow - bus entries, each input node is further provided with an analog-to-digital Converter, having the capacity To, digital to analog Converter having a width L, the source of the first MOS transistor is connected to the output of analog-to-digital Converter, an input connected to the output of the amplifier, the source of the second MOS transistor is connected to the input of digital to analog Converter, the output of which is connected with the control input of the amplifier, common bus reading is made of the number of tires, is equal to the bit analog-to -digital Converter and the number of first MOS transistors connected gates with the corresponding output mnogolyudnogo switch, drains with appropriate tires General tires read the sources to the corresponding inputs of analog-to-digital converters, which is equal To the bus record made of the number of tires, is equal to the word length of the digital to analogue Converter and the number of second MOS transistors connected drains with appropriate tires, forming a bus write, the gates - with the release of the next cell of mnogolyudnogo switch sources with the corresponding inputs of the digital to analogue Converter, the cat is itself equal to L.

The invention is illustrated in the following description and the attached drawing, which shows a schematic diagram of the proposed device for reading a two-dimensional sensors with adaptive signal processing in digital form, where 1 - mnogolyudnoe switch, 2 - power, 3 - comparator, 4 - arithmetical-logical unit (ALU), 5 - a block of memory (RAM), 6 common bus read, 7 - bus recording, 8 - analog-to-digital Converter (ADC), 9 - analog Converter (DAC), 10 - input of the amplifier 11 to the control input of the amplifier, 12 - the output of the amplifier 13 is the first MOS transistor 14 of the second MOS transistor.

The proposed multi-reader, as well as the prototype provides preprocessing the processing of signals from multiple sensors in real time, which consists in the subtraction individually for each channel additive component signals for multiple sensors, as a rule, are bothered components. When reading information from the IR photodetectors in the wavelength range 5-14 µm bothered components of the signals due to background radiation, range from 80% to 90% of the total signal. A constructive solution of the proposed device allows you to track low-frequency changes in the characteristics of the sensors, before the exact characteristics of the amplifiers, etc., thus, realizing the function of the high pass filter, and individually for each channel of the multichannel sensor adaptive adjustment of the characteristics of such a filter.

Additional equipment each input node ADC and DAC (see drawing) solves the problem of expanding the dynamic range and sensitivity multi-element sensors. It is known that when creating systems of digital processing of signals from multiple sensors are the most problematic in the implementation of a node is the analog-to-digital Converter, which is determined by the dynamic range. This site limits the bit width of digital signal processing and, consequently, the dynamic range and sensitivity multi-element sensors based on them. For multi-element IR FPU operating in the far infrared range, the necessary digital measuring channel with the number of digits not less than 16. Up to the present time, even when using the most advanced silicon technology for multi-channel devices, with a strict limit on occupied single-cell readout area and power consumption cannot be realized ADC with the capacity of more than 10 and to obtain the required dynamic range and sensitivity multi-element IR FPU third generation output in C is proveu form. The proposed technical solution, this task is solved in that the full dynamic range of the device is determined by the total ADC and DAC. As you know the DAC is much easier to implement than the ADC.

The expansion of the dynamic range and higher performance, due to the fact that the design solution proposed device unlike the prototype allows you to go from serial conversion of the analog signal in digital form to a parallel and transmit an information signal and a correction voltage in analog form and digital. As a result, the speed of transmission over the shared bus read and bus write significantly increases the performance of the multi-reader. It also extends the functionality and scope multi-reader, because they contribute to the performance of different IR FPU based on it.

Finally, a constructive solution proposed device allows preprocessing signal processing in digital form in contrast to the known technical solutions. The result has been a significant expansion of the capabilities of different IR FPU executed based on the proposed multi-channel device sitiveni is. For example, the introduction of bus records in digital form signals characterizing the image of any object, in addition to the additive, deductible from the total signal bothered components, provides a better recognition system.

Reader for two-dimensional sensors with adaptive signal processing in digital form is performed on the semiconductor substrate. The inventive device includes structural elements: mnogolyudnoe switch (1), power (2), the comparator (3), arithmetical and logic unit (ALU) (4), a block of memory (RAM) (5), a common bus read (6), bus records (7), analog-to-digital Converter (ADC) (8), digital to analog Converter (DAC) (9), the first MOS transistor (13), the second MOS transistor (14) (see drawing).

Amplifier (2)having an inlet (10), an outlet (12), control input (11), analog-to-digital Converter (ADC) (8), digital to analog Converter (DAC) (9), the first MOS transistor (13), the second MOS transistor (14) form the input node (cell amplifier). The device comprises N input nodes (cells amplifier).

The comparator (3), arithmetical and logic unit (ALU) (4), a block of memory (RAM) (5) form a block preprocessing signal processing.

Mnogolyudnoe the switch provides 1-(N+1) cells and 1.1-1.(N+1) outputs.

Each input node (cell condition the amplifier) input (10) of the amplifier (2) is connected to the sensor, output (12) of the amplifier (2) is connected to the input of analog-to-digital Converter (ADC) (8) with the capacity To, and control input (11) of the amplifier (2) with the output of the digital to analogue Converter (DAC) (9) with a width L. the Source of the first MOS transistor (13) is connected to the ADC input (8), the output of which is connected to the output (12) of the amplifier (2), a gate connected with the corresponding output mnogolyudnogo switch (1), and flows associated with the given bus reading component of the total bus read (6). The source of the second MOS transistor (14) is associated with the DAC output (9), the input of which is connected with the control input (11) of the amplifier (2), the shutter associated with the release of the next cell of mnogolyudnogo switch (1), and the drain is connected with the corresponding bus write part of a common bus write (7). Common bus read (6) is made of the number of tires, is equal to the bit ADC (8). The number of first MOS transistors (13) T÷TK, United gates with the output of the corresponding cell mnogolyudnogo switch (1), drains with appropriate tires General tires read (6), origins to the corresponding inputs of the ADC (8), is also equal to K. Bus write (7) is made of the number of tires, is equal to the bit DAC (9). Number of second MOS transistors (14) T2.1÷T2.L, United runoff bus write (7), gates - with the release of the next cell of mnogolyudnogo switch (1), history is AMI - with the corresponding DAC outputs (9), is also equal to L.

Two inputs of the comparator (3) are first and second inputs of the block preprocessing signal processing, the first of which is designed to feed him the signal in digital form, is received by the shared bus read (6), and the second to supply the reference code. The output of the comparator (3) is connected to the input of ALU (4), the output of which is connected to the input of RAM (5), the output of RAM (5), which is the output of block preprocessing signal processing, connected with bus write (7).

As constructive elements of the proposed multi-reader can be used, for example, elements of known technical solutions (III, Mphepo. Multiple-input processor with adaptive devices preprocessing signal processing for multi-element sensors. Avtometrija, No. 6, 1997, p.20-25).

The device operates as follows. Suppose the inputs of amplifiers (2) the signals from multiple sensors. By applying control voltages to mnogolyudnoe switch (1) on the outputs 1.1÷1.N+1 form a pulse voltage, sequentially opening the first and second MOS transistors (13, 14). Amplified signals from outputs (12) amplifiers (2) served on the ADC input (8) and then sequentially through the first MOS transistors (13) T÷TCK signals in digital form bitwise pic is ouput on a common bus read (6). The signals on the shared bus read (6) proceed to one of the inputs of the comparator (3). To another input of the comparator (3) is a constant reference code. Depending on the ratio of the information signal and the reference code at the output of the comparator (3) will be formed codes: +1 if Uwhitefish<Uop; -1 if Uwhitefish>Uop; 0 if Uwhitefish=Uod.When code +1 information in the i-th cell of the RAM (5) is increased by the increment LSB of RAM, with code -1 decreases. In the next cycle by reading the information signal from the i+1 cell amplifier (2) the adjusted value of the corresponding cell of RAM (5) for the i-th cell of the amplifier (2) via the bus write (7) and second MOS transistors (14) T2.1÷T2.L arrives at the input of the DAC (9) and later in analog form at the control input (11) i-in amplifier (2), which stores it in analogue form before the next cycle of reading (correction). At constant signals at the inputs (10) amps (2)maximum in 2Lcycles of reading, the potentials on all control inputs (11) of the input nodes will be formed in such a way that the output signals on the shared bus read (6) to the nearest LSB ADC (8) will be equal to the reference, regardless of current-voltage characteristics of the attached sensors to the inputs of the amplifiers (2) and the heterogeneity of the transmission characteristics will enhance the lei (2). As sensors can be, for example, IR photodetectors.

Multi-reader can be used to read signals from multiple sensors such as a bar type, and two-dimensional. When reading data from a two-dimensional sensor multi-reader should be augmented matrix of the preamp, the amp inputs will be sequentially to receive signals from the column bus read, that is, with different lines and, consequently, with different sensors. In this case, you only need to change the format of RAM. When reading the signals from the two-dimensional matrix of sensors organisation of RAM should be M×N×L, where M is the number of rows in a two-dimensional matrix of sensors. When reading the signal from the (i+1, j) cell, where i is the element number of the row, j the number of the line on bus write to RAM must enter information about the element (i, j+1).

The positive effect of the proposed reader is the expansion of the scope.

Multi-reader, performed on the semiconductor substrate containing N input nodes, mnogolyudnoe switch, a common bus read, bus write, the block preprocessing signal processing, contains a comparator, an arithmetical and logic unit, a memory unit, and of the two inputs of the comparator one is rednaznachen to feed it signal into a digital code and connected with a common bus read and the other comparator input is designed to supply the reference signal, the comparator output is connected to the input of arithmetical-logical unit, the output of which is connected to the input of the memory block, and the output of the memory block associated with the bus entries, each input node is made in the form of an amplifier having input, output and control input, two MOS transistors, the gate of the first MOS transistor is connected to the output of the corresponding cell mnogolyudnogo switch, and the drain - General bus read, the gate of the second MOS transistor is connected to the output of the next cell of mnogolyudnogo switch, and the flow - bus write, characterized in that each input node is further provided with an analog-to-digital Converter, having the capacity To, digital to analog Converter having a width L, the source of the first MOS transistor is connected to the output of analog-to-digital Converter, an input connected to the output of the amplifier, the source of the second MOS transistor is connected to the input of digital to analog Converter, the output of which is connected with the control input of the amplifier, common bus reading is made of the number of tires, is equal to the bit analog-to-digital Converter and the number of first MOS transistors connected gates with the corresponding output mnogolyudnogo switch that discharges comply with them tires General tire reading origins to the corresponding inputs of analog-to-digital converters, which is equal To the bus record made of the number of tires, is equal to the word length of the digital to analogue Converter and the number of second MOS transistors connected drains with appropriate tires, forming a bus write, the gates - with the release of the next cell of mnogolyudnogo switch sources with the corresponding inputs of the digital to analogue Converter, which is equal to L.



 

Same patents:

The invention relates to a structure oriented on the radio, in particular, to the structure of the CMOS circuits for digital radio transceiver

Multichannel reader // 2282269

FIELD: optical data processing systems.

SUBSTANCE: proposed multichannel reader built on semiconductor substrate has N input units, multiple-output switching unit, common read-out bus, write bus, pre-processor signal processing unit incorporating comparator, arithmetic-logic device, and memory unit; one of two comparator inputs is designed to apply digital-code signal thereto and is connected to common read-out bus; other comparator input is designed to feed reference signal; comparator output is connected to input of arithmetic-logic device whose output is connected to input of memory unit whose output is coupled with write bus; each input unit is made in the form of amplifier that has input, output, and control input, as well as two MIS transistors; first MIS transistor gate is connected to output of respective cell of multiple-output switching unit and gate, to common read-out bus; second MIS transistor gate is connected to output of next cell of multiple-output switching unit and gate, to write bus; each input unit is provided in addition with K-capacity analog-to-digital converter and L-capacity digital-to-analog converter; first MIS transistor source is connected to output of analog-to-digital converter whose input is connected to amplifier output; second MIS transistor source is connected to input of digital-to-analog converter whose output is connected to amplifier control input; common read-out bus is assembled of K buses, K being equal to capacity of analog-to-digital converter and to number of first MIS transistors connected through their gates to respective outputs of multiple-output switching unit, through drains, to respective buses of common read-out buses, and through sources, to respective inputs of analog-to-digital converters; write bus is assembled of L buses, L being equal to digital-to-analog converter capacity and to number of second MIS transistors connected through drains to respective buses forming write bus, through gates, to output of next cell of multiple-output switching unity, and through sources, to respective inputs of digital-to-analog converter.

EFFECT: extended dynamic range, enhanced speed, enlarged functional capabilities.

1 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: in semiconductor instrument containing sink, source consisting of transistor cells and peripheral p-n junction, which are located under gate electrode, as well as of metal electrode of source, which is located above gate electrode, polysilicon gate electrode insulated from source areas with dielectric, which contains in middle part the matrix of transistor cells and peripheral end part overlapping above the dielectric the source peripheral p-n junction; end part of polysilicon gate electrode, which overlaps above the dielectric the source peripheral p-n junction, is topologically separated from end cell of matrix of transistor cells and not covered with source metal coating.

EFFECT: reducing the resistance of power double-diffused MOS transistors in open state, without increase in the size of crystal and deterioration of other parameters.

2 cl, 3 dwg

FIELD: electricity.

SUBSTANCE: thin-film transistor TFT includes a gate, a first insulating layer located above the gate, a second insulating layer located above the first insulating layer, a semiconductor layer, a source and a drain, located between the first insulating layer and the second insulating layer, an ohmic contact layer located between the semiconductor layer, the source and the drain, the ohmic contact layer including an opening passing through the ohmic contact layer by means of a gap between the source and the drain in order to open the semiconductor layer, and the second insulating layer is connected to the semiconductor layer through this opening, and a conductive layer located above the second insulating layer. The conductive layer and the gate are electrically connected to each other, so that when the TFT is in the on-state, the switching current generated in the conductive channels of the semiconductor layer is increased. When the TFT is in the off-state, the tripping current generated in the conductive channels is reduced.

EFFECT: the ratio of the making current to the tripping current is increased.

15 cl, 6 dwg

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