Telecommunication multi-functional multiplexer

FIELD: computer science, in particular, engineering of device for input-output of information in electronic computing machine, transferred along communication channels for transferring information; in particular, device is meant for acting as an intellectual multi-port telecommunication port of personal computer, used in mode of central transport station in data transfer networks for specialized use.

SUBSTANCE: multiplexer has system block, wherein four-channeled telegraph one-polar and two-polar modules are positioned, as well as four-channeled standard-joint C2 module, bi-impulse one-channeled and two-channeled modules, one-channeled telephone module, m modules of four-channeled asynchronous adapter, group control electronic board, and also block for adjustment and control, and combination board.

EFFECT: expanded functional capabilities, possible increase of number and types of connected input-output channels, possible synchronization with several types of specialized equipment.

4 cl, 4 dwg, 1 tbl

 

The technical field

This solution relates to the field of computer hardware, namely, devices of I / o electronic computing machine information transmitted over communication channels of data transmission systems.

The level of technology

The analogue of this technical solution is known device Group complex to enhance the reliability of GCPD-16M TO that converts information during transmission between the electronic computing machine Single system (EU) computer (via the interface I / o EC computer) and communication channels (through a multichannel device converting telephone signals SS RU, multi-unit conversion signals Telegraph SS RU and device pairing with special equipment SO RU).

The disadvantage of analog is its complexity and the impossibility of a pair of special data channels with personal computers compatible with IBM PC/AT.

The closest analogue (prototype) of the claimed device is the controller I / o BT01-204 system unit of a personal computer (for example, from the product V-11 UXO)containing two channel RS232 (see, for example, manual UXO manual, section 5, table 5.8 (RS-232)) and performs a sequential input-output the information.

The disadvantages of the known devices are limited functionality, insufficient number of channels I / o, no pairing with special equipment, with the C2 interface-SPEC (with extended lines, and the algorithm in comparison with RS-232). Implementation of the required number of input channels by increasing the number of the applied controllers I / o is limited by the ability of the slot of the PC.

Similar disadvantages from the point of view mate with multiple data channels has been observed in other PC, compatible with IBM PC/AT and having serial ports (COM1, COM2) RS-232 (see, for example, the system Board "FS10-ATX").

The invention

Known multiplexer telecommunications multifunctional modular and contains the system unit that hosts the module four-channel Telegraph unipolar (MTGO) for coupling a multiplexer with four dedicated or switched wire communication channels and converting logic signals of the multiplexer in the current Telegraph parcel when sending data to the communication channels and convert the current Telegraph parcels in the logical signals, multiplexer adapted to, when receiving data from a communication channel, four-channel module interface C2 (MS) for electrical matching single-pole circuits internal serial interface (VPI) multiplexer with four double-pole circuits standard interface S2 (RS-232C), the first group of inputs-outputs of which are connected with the tire C2 connect to the physical line module four-channel Telegraph bipolar (MTHD) for coupling a multiplexer with four dedicated or switched wire communication channels when transmitting bipolar current assumptions, the first group of inputs-outputs of which are connected with tires C1-TG connection to telegraphic communication channels, module dual iimpulse (MBI) for coupling a multiplexer with two dedicated wire iimpulse communication channels and converting logic signals from the multiplexer in iimpulse signal when transmitting data in the communication channel and the inverse transformation when receiving data from a communication channel, the first group inputs-outputs of which are connected with tires C1 And connect to the impulse channel module single channel iimpulse (MBI) for coupling a multiplexer with four selected iimpulse communication channel and converting logic signals from the multiplexer via RS-232C, iimpulse signal when transmitting data in the communication channel and the inverse transformation when receiving data from a communication channel, the first group of inputs-outputs of which are connected with the bus C1 And connect to reimburseme channel module single-channel telephone (MTC/TF) for suprarenalectomy leased and switched telephone communication channels with two-wire and wire termination and conversion of the logical signals of the multiplexer in the frequency-modulated signals in accordance with the recommendations of the CCITT v 23 when transmitting data in the communication channel and converting the frequency-modulated signals to logical signals of the multiplexer when receiving data from a communication channel, the first group of inputs-outputs of which are connected with the bus C1-VF connection to a telephone communication channel, and the block adjustment and control (BRC) to control the signal level in the communication channel and control its state in a separate enclosure, the first group of inputs-outputs of which are connected with the first group of input-output module four-channel Telegraph unipolar (MTGO), and the second group of inputs-outputs with tires C1-TGO connection to telegraphic communication channels.

The purpose of this technical solution is the extension of functional capabilities, which allows to increase the number and types of connected channels of I / o (communication channels), to be able to mate with several types of special equipment, use of personal computers compatible with the IBM PC.

The inventive multiplexer telecommunication multi function further comprises structurally placed in the system unit and multiplexer m modules adapter-channel asynchronous (MAA) to implement link-layer protocols and procedures, interaction with four communication channels asynchronously in the full-duplex or half-duplex data transmission mode, the first group of inputs and outputs which are connected via an internal serial interface (VPI) with the second group of input-output module four-channel Telegraph unipolar (MTG), or module four-channel interface C2 (MS), or module four-channel Telegraph bipolar (MTHD) or module dual iimpulse (MBI), module single channel iimpulse (MBI) and module single-channel telephone (MTC/TF), cost of group management (PSU) for the formation of the group of main signals and special control signals internal parallel interface (the WHEN) and the implementation of procedures to establish the connection, transformation and control during data transmission and data reception, the first group of inputs-outputs of which are connected through the internal bus of the parallel interface (the WHEN) with groups of second input-output m modules adapter-channel asynchronous (MAA), charge conjugation (PS) to negotiate signals PSU multiplexer system highway ISA control PC, structurally placed in the system unit of a PC, the first group of inputs-outputs of which are connected with the second group of input-output Board group management (PSU), and the second group of inputs-outputs connected to the system bus ISA personal electronic computer, with the compatible with IBM PC.

Charge conjugation (PS) contains the first register (WG), an input connected to the ISA bus (A[0-19]), and the output with the first input of the Board group management (PSU), the first decoder (LH), the first and second inputs which are connected respectively with the first (CS MEM) and the second (CS 10) inputs PSU, the first bus driver, the first group of inputs-outputs of which are connected to the ISA bus (D[0-15]), the CS input with the output of the first decoder LH, and a group of outputs D[0-15] to the corresponding inputs of PSU, the second bus driver chess Federation, the first group of five inputs connected to the ISA bus (MEM(R), MEM(W), IOR, IOW, AEN), the sixth input to an output IRQ[10] Board group management, five outputs connected to inputs of MEM(R), MEM(W), IOR, IOW, AEN Board group management, and the sixth output bus ISA IRQ[10], a chain of signal I/O CH RDY from the PSU connected to the corresponding circuit ISA bus.

Charge of group management (PSU) includes a third bus driver, two inputs of which are connected respectively to the outputs of the And[0-19], AEN Board pairing (PS), and the first output bus, the WHEN AND[13-19], the fourth bus driver, four inputs which are connected respectively to the outputs of the MEM R MEM W, IOR, IOW Board pairing (PS), a second decoder, three inputs which are connected respectively with the first output of the third bus driver and the two outputs of the fourth bus driver, and two outputs, respectively, with Shi is Oh the WHEN PNU_[0-7], RVR/RU[0-7], the third decoder, two inputs of which are connected respectively with the first SHA[0-19] and the second AEN outputs of the third bus driver and three output to the bus, the WHEN RAP and outputs MEM CS and CS I/O Board mates PS, the first controller interrupts the CRC, two inputs of which are connected respectively with the third output of the second decoder and bus in the WHEN IRQ[0-7], the fifth bus driver (chess Federation), the first input connected to the bus, the WHEN MEM W, sixth bus driver (chess Federation), two inputs of which connected respectively with the output of the first controller interrupt and I/O CH RDY, and two outputs respectively to the inputs IRQ[10] and the I/O CH RDY Board pairing, the second register interrupt WG, three inputs which are connected respectively with the second output of the first controller interrupt D[0-7], the output of the fifth bus driver D[0-15] and chain MEM W the WHEN, the fourth output of the fourth bus driver and MEM R the WHEN MAA, and the output to the input D[0-15] Board mates PS.

The adapter module four-channel asynchronous (MAA) contains the pulse generator G, the Central processor, the first input connected to the output of the pulse generator, the buffer register, two inputs of which are connected respectively to bus And[0-19] and the second output of the Central processor, the eighth bus driver, two inputs of which are connected according to the respectively bus D[0-13] and the second output of the Central processor, and the input-output bus VPI module adapter-channel asynchronous MAA, shaper pulses, the input and output of which are connected respectively with the second output of the Central processor and the bus, the WHEN STB_BR, tire amplifier, two inputs of which are connected respectively with the bus, the WHEN AND[0-16] and the second output of the Central processor, and the output from the output buffer register BR, random access memory, a first input connected to the output of buffer register And[1-11], and the output bus VPI module adapter-channel asynchronous, the fifth decoder interrupt vector, the input connected to the output buffer register And [0, 12, 19], and the first output with the second input of the random access memory, a permanent storage device, a ROM, an input connected to the second output of the fifth decoder interrupt vector, and the output bus VPI module adapter-channel asynchronous, the fourth decoder LH, two inputs of which are connected respectively with the output As[4-6] and the third output of the Central processor, the asynchronous serial ports (ABP 0-3), two inputs of which are connected respectively with the first output of the fourth decoder and bus VPI D[0-7], and the first output with one of the input sampling module adapter multichannel asynchronous, the seventh bus driver, two the stroke output of which is connected respectively with the output-input the WHEN and VPI, and the entrance to the third input of the CPU register I / o, three inputs which are connected to the bus, the WHEN D[0-7] and RVR/RU and the first output of the fourth decoder LH, the first input-output bus VPI module four-channel asynchronous adapter, the second controller interrupts, six inputs which are connected respectively with the second and third outputs of the input register output, a second output asynchronous serial port, the third and fourth outputs of the fourth decoder and the third output of the Central processor, and the output from the second input INT CPU, a scheme specifying the address, the comparison circuit address, three inputs which are connected respectively with the bus, the WHEN RAP and[13-15] and the output of the circuit specifying the address of the buffer BUF, two inputs of which are connected respectively with the bus, the WHEN MEM(R) and MEM(W), the first trigger (T), two inputs of which are connected respectively to the outputs of the comparison circuit addresses and buffer, the second trigger, two inputs of which are connected respectively with the output of the first flip-flop and the output of the pulse generator, and two outputs respectively with the third input HOLD CPU and the bus, the WHEN the I/O CH RDY.

List of drawings

Figure 1 shows the structural diagram of the multiplexer telecommunications multifunctional.

Figure 2 shows the structural diagram of the interface Board is.

Figure 3 shows the structural scheme of the group Board of management.

Figure 4 shows the structural diagram of the adapter module four-channel asynchronous.

Example options for performing device

The multiplexer telecommunications multifunction (figure 1) contains the charge conjugation (PS) 1, the system unit that hosts charge of group management (PSU) 2, the adapter modules-channel asynchronous (MAA) 3, module four-channel Telegraph unipolar (MTG) 4 module four-channel junction of C2 (MS) 6 module four-channel Telegraph bipolar (MTHD) 7, module dual iimpulse (MBI) 8 module single channel iimpulse (MBI). 9, module single-channel telephone (MTC/TF) 10 and the block adjustment and control (BRC) 5 in a separate enclosure, the system bus ISA PC 11, the internal parallel interface system module 12, and the following bus connection communication channels (CC): bus C1-TG connection to telegraphic communication channels 13, bus C2 14 connect to the physical line, bus C1-TG connection to a telephone channel 15, the bus C1 And connect to the pulse channel 16, the bus C1-VF connection to a telephone communication channel 17.

Charge conjugation (PS) (figure 2) contains the first register(WG) 18, the first decoder (LH) 19, the first bus driver (chess Federation) 20, the second bus driver (chess Federation) 21, the ins ISA 11 and bus interfacing with the Board group management (PSU) 22.

Charge of group management (PSU) (figure 3) includes a third bus driver (chess Federation) 23, the fourth bus driver (chess Federation) 24, the first interrupt controller (CRC) 25, the fifth bus driver (chess Federation) 26, the sixth bus driver (chess Federation) 27, the second and third decoders (LH) 28, 29, the second register(WG) 30.

The adapter module four-channel asynchronous (MAA) contains a pulse generator (G) 31, a Central processing unit (CPU) 32, the bus amplifier (SHU) 33, the seventh bus driver (chess Federation) 34, a register I / o (RVV) 35, a scheme specifying the address (be) 36, the comparison circuit address (SSA) 37, a buffer (BUF) 38, a pulse shaper (PHI) 39, buffer register(BR) 40, eighth bus driver (chess Federation) 41, a fourth decoder (LH) 42, a second interrupt controller (CRC) 43, the first trigger (T) 44, random access memory (RAM) 45, the fifth decoder interrupt vector (DSVP) 46, a persistent storage device (ROM) 47, asynchronous serial ports (ABP) 48, a second trigger (T) 49, internal serial interface (VPI) 50.

Multifunctional telecommunications multiplexer (hereinafter multiplexer) is designed to work as "intelligent" multi-input telecommunication port of a personal computer (PC)mode uses a hub transport station in data communication networks Spa is territorial assignment.

The multiplexer provides together with the management PC interaction with the communication channels in accordance with the data exchange protocols physical, data link, network and transport layers. While the transport and network layers are implemented in software management PC. Physical and link levels of interaction with the communication channels are implemented in hardware and internal software multiplexer.

The multiplexer in combination with the PC software provides a transport station, which provides:

- the special education file applications with the routing address information;

- establish physical and logical connections in the data network;

- transfer files between the node and the subscriber PC mode message switching using control points (recovery in case of failures of communication channels);

- automatic switching to a backup channel when the channel fails;

background sending service messages on any of the areas with the issuance of the alert tone for incoming correspondence without stopping the main information exchange;

compression and decompression (archiving and dearchive) transmitted information;

control file transfers control to the summation and the cycle of the economic numbers of messages (frames);

- maintenance of static information (log) documenting names and parameters can send and receive files and information about the process of transportation.

As software controls operation of the multiplexer can be applied Telecommunication software TS_NET RDPI-02 (certificate of official registration of the computer program No. 2000610629), checking the operation of the multiplexer is provided by the test software TS_NET RDPI-01 (certificate No. 2000610625).

To meet the particular requirements of the communication multiplexer can be supplied in various versions, differing in the number of system units, method of connecting to the PC, the number of lines of communication and types of accepted channels.

Main technical characteristics of the multiplexer is shown in the table.

The name of the parameterSpecifications
Type of plug-in PCCompatible with IBM PC
The type of joint with PCThe ISA bus 16 (8) digits
The exchange mechanism with PCTwo memory bit in the grid memory PC, group exchange registers, a two-way mechanism Prerow is any
The number of interrupts the PC used by the multiplexerIRQ10
The address space of the PC used by the multiplexerD0000 - DFFFF
Address space I/O PC used by the multiplexerS - 1CF, V - 1BF
The mode of data transmission in the communication channelSynchronous, asynchronous
The total number of organized duplex communications lines4-32
Type linear joints equipment dataThe junction of C1 And (bipolar sending redundant recoding in iimpulse signal); the junction of C1-TG (unipolar Telegraph parcel DC); the junction of C1-TG (bipolar Telegraph)
The data rate provided by the linear adaptersFrom 50 to 9600 bits/s

The composition of the multiplexer includes:

- system block (blocks), intended for installation of modules, PCB power supply;

- plugins and Board 2-4, 6-10 designed for hardware-software implementation of the telecommunications exchange and provide physical interaction signals in accordance with the types of connected joints;

Plata mate (SS) 1;

block adjustment and control (BRC) 5.

In nomencl the round plug and the circuit Board includes:

- Board group management (PSU) 2;

the adapter module four-channel asynchronous (MAA) 3;

module one-channel iimpulse (MBI) 9;

module four-channel Telegraph unipolar (MTG) 4;

module one-channel telephone (MTC/TF) 10;

module four-channel Telegraph bipolar (MTHD) 7;

module four-channel standard junction of C2 (MS) 6;

module dual iimpulse (MBI) 8.

The amount realized in the system unit areas of information exchange, as well as the number of system blocks (not more than three) will be determined by the embodiment of the multiplexer.

The structure of the multiplexer is implemented in accordance with the modular principle of construction and provides maximum flexibility in configuration and adaptation of the device for specific applications. In a set of functional modules present in the composition of the multiplexer, includes the group modules (General purpose), modules, linear control (linear adapters and modules signal transformation.

The functional basis of the construction of the multiplexer is a multi-microprocessor structure, oriented to the implementation of multi-channel data exchange via communication channels and consisting of a functional electronic modules connected with the battle interface connections.

Hardware-software interaction multiplexer with control PC organized through a standard system bus ISA PC IBM PC / AT. Information communication is performed through memory multiplexer placed in the address grid processor computers, and through a set of independent ports I / o accessible from the PC. Requests for information services, received from multiplexer, processed by the standard mechanism priority interrupt PC.

Board group management PSU and card pairing PS with the system backbone PC interact multiplexer with control PC and are unchanged in any configuration when connected to a PC via its internal parallel interface.

Group modules are the main "intellectual" elements of the multiplexer and is intended for hardware and software implementation procedures, connectivity, transformation, and control data during transmission and reception of information.

The modules convert signals provide the physical coupling line adapter (LA) with linear joints connected equipment data.

In the structure of the multiplexer interface involved the following types of communication:

- system bus ISA PC PC AT 11;

interface R-232C PC PC AT;

- internal parallel interface system module (the WHEN) 12;

- internal serial interface system module (FS) 50;

- linear joints equipment data 13-17.

The signal system line PC broadcast in charge of group management, responsible for the formation of the internal signals of the parallel interface (the WHEN). The WHEN is a system of electrical circuits and signals, including highway data, address, control and power, combining typical installation location (interface connector) circuit switching system unit.

Internal parallel interface system module (the WHEN) is a simplification of the system of highways ISA to PC compatible with IBM PC AT.

1. Group of main signals:

D[0-15] - line data;

[0-19] - line address;

NON - permission of transmission of the high byte of data, which together with the younger category addresses[0] defines the format of data transferred over the bus.

2. The control signals of the access operations to the memory and ports I / o:

IOR - command "Read port";

IOW - command "Write port";

MEMR command "Read memory";

MEMW command "Write memory".

3. Signals General management relayed from the system backbone PC:

AEN - resolution is the address of the RAP. Thus there is a logical disconnect source addresses and commands the system bus to enable data transfer over the channel of the RAP;

PDP - direct access memory (RAP);

RESET - reset;

I/O CHR DY - readiness system bus.

4. Special control signals in the WHEN:

IRQ LA - interrupt logical adapter;

PRQ LA confirmation processing interrupts from the logical adapter;

PND LA push setup logical adapter;

RO LA force sample logical adapter;

The t - direction of transfer;

EZ - resolution transmission.

Electrical and logical interaction modules, adapter modules, signal conversion is carried out through a system of links internal serial interface (VPI), similar to the RS-232 interface with a reduced set of chains.

Internal serial interface system module (VPI) is a simplified version of the RS-232C interface.

VPI provides a set of signals corresponding to the minimum (9-pin) range signal RS-232C interface:

3
Room chainName
1102Signal ground
2103The transferred data
104Received data
4105Request to send
5106Ready for pick-up
6107APD (equipment data) ready
7108.1Attach the ADF to the line
8109The detector received line signal data
9125Call indicator

Charge of group management (PSU) is designed to form a group of main signals and special control signals internal parallel interface.

Charge conjugation (PS) is designed to coordinate signals Board group management (PSU) multiplexer system highway ISA 11 controlling personal computer.

Main characteristics of the Board pairing:

- address bus - dvadtsatimetrovy;

- data bus - bit.

Fee substation relaying main signal (main data D[0-15], the line address And[0-19]), control signals of the memory access ports and input / output ("MEMW", "MEMR", "IOW", "IOR"), signals common control ("AEN") and interrupt request ("IRQ10").

The adapter module four-channel asynchronous (MAA) is sobo is a specialized microprocessor controller, designed for the implementation of link-layer protocols and procedures, interaction with the communication channels.

The main characteristics of the module:

- the number of communication channelsfour;
- the data transfer mode- asynchronous;
- transmission rate in the communication channel- 50, 100, 200,
(bit/s)300, 600, 1200,
2400, 4800, 9600;
- type of workduplex,
half-duplex

Internal software module stored in the program placed in ROM, and consists of two main parts:

test module;

program service communication channel.

The test program includes:

check microprocessor;

check RAM;

check controller interrupts;

- checking asynchronous serial port with four channels.

Program maintenance of communication channels provides:

transmission (reception) of information units from the channel(a) communication through the asynchronous serial ports;

- implementation of procedures to establish a physical connection;

- process synchronization information exchange dims the go and upper levels of the software transport system with input and output information buffer;

implementation of algorithms omegaseamaster encoding and correcting errors in the information received from the communication channel.

Module four-channel junction of C2 MS 6 is designed for electrical matching circuits internal serial interface with bipolar circuits standard interface S2 (RS-232C).

The main characteristics of the module:

the number connected to the junction of C2 external devices - 4;

- number of circuits formed in each joint 9;

- settings module in part mates with the junction of C2 - according to GOST 23675-79.

A module is a set of amplifiers transmitters and amplifiers-receivers that transform a single-pole TTL levels in bipolar (plus 12 minus 12) levels of joint C2.

The logical level "1" at the junction of C2 corresponds to the minus 12, and the level of logical "0" level plus the 12th Century

Module one-channel telephone MTC/TF 10 is designed to mate multiplexer leased and switched telephone communication channels with two-wire and four-wire termination.

The main characteristics of the module:
connection to the multiplexer- the junction of the serial interface (RS-232C);
- speed- 60, 1200 bps;
- type of channel- dial telephone with two-wire termination rented with two-wire end-leased four-wire termination;
- method of data transmission in the communication channel- asynchronous, synchronous duplex on four-wire communication channel, asynchronous half duplex over dial-up telephone and leased communication channel;
the modulation method of a discrete signalfrequency by CCITT v23
- transmit level- in dial-up telephone channel from -15 to 0 dB, in a rented four-wire channel from minus to minus 43 15 dB;
receiving level- in dial-up channel from minus 43 to 0 dB, in a rented four-wire channel from minus 30 to minus 0 dB;
- how to dial in dial-up telephone channelpulse;
- modes of operation- operating mode "DATA"control modes "TRAIN" (control flat cable from the RS-232C interface) and
"TRAIN US" (the control loop from the side lines).

The principle of operation of the module is to convert the logic signals of the multiplexer in the frequency-modulated si is Nala in accordance with the recommendations of the CCITT v23 when transmitting data in the communication channel and converting the frequency-modulated signal into a logical signal, adapted to the multiplexer, when receiving data from the communication channel.

The structure of the module consists of the following functional blocks:

block mates at the junction of C2;

- transmitter unit of the frequency-modulated signal;

- the receiver unit of the frequency-modulated signal;

block mates with the telephone channel.

The unit pair at the junction of C2 includes:

receivers, which convert the signals on circuits"108", "105", "103", having options TTL circuits, signals with parameters chips with 12V power supply, transmitter, which converts the signals with parameters coming from the module, the signals with parameters TTL chips on the circuit"107", "106", "104", "109", "114", "115", "125".

Transmitter frequency-modulated signal consists of a crystal oscillator, modulator, driver speed signal and the low pass filter, suppressing the by-products of the data signal. A crystal oscillator generates a highly stable frequency signal of 2400 kHz. The modulator is a switched depending on the value of information (the chain "103") divisor. The division ratio switchable divider, except for the value of information is determined by the condition of the chain "111". So when "on" the circuit "111" information "0" corresponding to the division ratio of 143, the information "1" is 231. the change of the coefficient of fact, the Oia switchable divider is carried out over a period of 88 times smaller than the period of the data signal, which is equivalent to the abrupt phase modulation on the angle from 0 to 4. This ensures that bezopasnosti phase of the frequency-modulated signal for transmission.

Speed signal processing of data is carried out on wasmerely frequency. This allows to achieve sufficient suppression of by-products formation by using relatively simple lowpass filter. The status "OFF" in the chain "105" blocks the operation of the driver, and consequently, the entire transmitter.

Receiver frequency-modulated signal consists of a bandpass filter, an amplifier-limiter, a frequency detector post-detection filter with a threshold device, divider 250 with the control circuit, the level detector and filter on the frequency of 2600 Hz. Bandpass filter extracts the data signal against the background noise of the communication channel. The frequency detector generates a signal of logic "1" of a given duration after any change of the polarity of the signal at the output of the amplifier-limiter and signal logic "0" until the next polarity change. The duration of the logical signal "1" is selected so that when receiving a signal with an average frequency of 1700 Hz at the output of the frequency detector to generate a signal with a duty cycle of 2, while the frequency of "clicking" and "squeezing" the duty cycle will change in the direction of decrease the Oia and increase, respectively.

Post-detection filter with a threshold device allocates a constant component of the signal output from the frequency detector and generates an asynchronous data reception.

The level detector generates a signal in the circuit "109". "On" in the chain "109" up until the received signal is more than -43 dB.

Block mates with the communication channels at the junction of C1 consists of two controllable amplifiers transmission and reception, four keys, two matching transformers, the node holding the line and dialing relay connection to the communication link, the signal receiver response station, the receiver of the CALL switches, which are different modes of operation.

The call signal, a frequency of from 16 to 50 Hz, is processed by the module, forming the signal chain "125". If you need to make a call with this module chain "108" translates to "on". At the input of the receiver begins to receive the signal Response station", translating circuit "109" in the "ENABLED"status. After that, you can start dialing a phone number that is on the chain "103". The operation of the transmitter and receiver by a signal in the circuit "105". When the chain 105 operates the transmitter, and the signal from its output through the key, adjustable amplifier and transformer flows into the communication channel. When the power is Noah chain "105" operations of the transmitter is blocked, and through the opened key channel is connected to the input of the adjustable amplifier of the reception.

When working on a leased channel with wire end in the chain of transmission includes the amplifier, transmitted through the transformer T1, and receiving through the transformer T2.

Module one-channel iimpulse (MBI) 9 is designed for coupling a multiplexer with a dedicated four-wire iimpulse communication channel, including private special equipment.

Module one-channel iimpulse converts logic signals from the multiplexer, iimpulse signal when transmitting data in the communication channel and the conversion iimpulse signal in the logical signals, multiplexer adapted to, when receiving data from the communication channel.

Main technical characteristics of the module:
connection to the multiplexer- the junction of the serial interface (RS-232C);
- speed- 1200, 2400, 4800, 9600 bps;
- type of channel- shown with wire end;
- method of data transmission in the communication channel- synchronous four-wire duplex;
- methods for the modulation of a discrete signal - bipolar send redundant recoding in iimpulse signal;
- rated peak value iimpulse signal when passing- 0.5 V;
- peak value iimpulse signal when receiving- 0.05 V

The structure of the module consists of the following blocks:

array receivers mates.

block transmitters mate

- block buffer;

unit clock frequency divider;

block encoder iimpulse signal;

block decoder iimpulse signal;

- block linear transmitter;

- block linear receiver.

The unit buffer includes:

receivers and transmitters mates on the junction of C2 chain "C", "C", "C";

- input registers with controls for "re-linking" asynchronous information under synchronous clock frequency.

The clock frequency is a highly stable crystal oscillator with divider. At different speeds require different frequencies, which are obtained at the output of the divider. The divider is set with a switch.

In block encoder iimpulse signal data is converted into iimpulse signal. The symbols "0" and "1" data signal is transmitted in takebayashi two pulses of equal duration and opposite polarity. The procedure of alternating polarity pulses compared to the previous clock interval is not changed during transmission of the symbol "1" and changes in the transmission of symbol "0". Iimpulse signal passes through a digital filter in order to form the fronts of the pulses transmitted in the line, to eliminate high-frequency components of the signal spectrum. Depending on the speed select switch corrective capacitors.

The linear part of the receivers and transmitters provide galvanic isolation and the symmetry of the input and output circuits of the module.

Taken from the channel iimpulse the output signal from the comparator, normalized under the logic levels supplied to the decoder iimpulse signal.

For correct decoding is used with a preset clock frequency. It is formed by using a phase lock the frequency to the fronts of the received signal. The decoded information is transferred to the input of the transmitter buffer.

Module dual iimpulse (MBI) 8 represents two independent submodule conversion of signals, similar to the single module reimburseme (MBI) and is used for converting logic signals from the multiplexer via RS-232C, iimpulse signals when transferring data in one of the two communication channels and transformation is iimpulse signals in a logical, adapted to the multiplexer, when receiving data from the communication channel.

Module four-channel Telegraph bipolar MTHD 7 or module four-channel Telegraph unipolar MTGO 4 are intended for coupling a multiplexer with four dedicated or switched wire communication channels.

The main characteristics of the module:
connection to the multiplexer- interface serial interface RS-232C;
- speed- from 50 to 200 bps;
the number of communication channels- 4;
- type of channel- dedicated or dial-up wire;
the modulation method of a discrete signal- bipolar send with parameters corresponding to GOST 22937-78, or unipolar current and no-current parcels;
- way transmission of information in each channel communications- asynchronous duplex;
- the value of the current during no-current packages- no more than 2 mA;
- the current value when the current packagesno more than 50 mA

The principle of operation of the module is to convert logic signals multiple the Sora in the current Telegraph parcel when sending data to the communication channels and the conversion of current Telegraph parcels in the logical signals, adapted to the multiplexer, when receiving data from the communication channel.

Functional module consists of the following blocks:

- block connection with Telegraph channels;

- block signal conversion interface S2 (RS-232C) standard TTL levels and Vice versa.

The module is controlled by the input logic signals "C" and "C". The combination of the States of these signals determines the following three operating modes of the module:

1) "C" - "1", "C" - "1". This is the initial mode in which only receiving information from a channel operating current in the transmission line is not present, the communication is prohibited;

2) "C" - "1", "C" - "0". This mode is ready to send, which along with accepting information from a channel in the transmission circuit operating current flows, while the transmission is still prohibited;

3) "C" - "0", "C" - "0". This operating mode duplex information exchange channels, which allowed the transmission and reception.

The module with the Telegraph channels possible in two ways:

1) unipolar - current and no-current parcels;

2) bipolar - bipolar pulses in accordance with GOST 22938-78.

Change options work is carried out by soldering jumpers in the circuit Board of the module.

The module consists of the following parts:

pulse power source;

- four hodnoty the data transceiver circuits for channels 0, 1, 2, 3;

- node communication module MAA;

- node communication channel for unipolar option.

Switching power supply module is designed to provide eight a constant voltage of 20 V, which provides power to an independent four-node formation and stabilization of the current reception and four-node formation and stabilization of the current transfer.

Transmitting paths for channels 0, 1, 2, 3 serve for the reception of Telegraph lines and transmission in the adapter information packages and back. Transmitting paths for all channels of the same type.

The transmitter unit consists of the following functional units:

schema generation input shapers parcels;

scheme of formation of the positive assumptions;

scheme of formation of negative assumptions;

schema pair of formers parcel line;

scheme limit short circuit current in the line.

The receiver unit consists of the following functional units:

- regimens and generate the input signals;

schema registration received data;

- shaping circuit output signals.

The communication module MAA is designed to convert a single-ended TTL signals adapter group in bipolar pulses plus/minus 12 transceiver channels and back.

ramireddy scheme to operate in unipolar mode channel consists of the following components:

- linear filters transmit and receive;

- linear diode rectifiers transmission and reception, providing insensitive to the polarity of the connection line;

diagrams of the formation and stabilization of the current transmission and reception, providing a potential separation of the logical and linear circuits, control shapers currents and stabilization of the set values of the currents.

The multiplexer operates as follows.

The operation is carried out in two modes:

- information transfer from the PC to the communication channel;

- receiving information from the communication channel in the PC.

Transfer.

For each channel of the multiplexer in the memory device, RAM adapter module four-channel asynchronous MAA 3 selected two buffers for transmission and two buffers for the reception. The block of information in the PC is prepared on the ISA bus 11.

From a PC, the information block is placed in the buffer for transmission as follows. Set the address on the a[0-19] ISA bus, which is in charge of the mate PS 1 through the first register RG 18, the third bus driver chess Federation 23, analyzes the digits And[16-19] the third decoder LH 29. When an address match with the memory D0000 produced signals CSMEM and RAP. The signal CSMEM enters the Board pairing on the first decoder LH 19 and allows the first bus driver chess Federation 20. The RAP signal p which enters MAA 3 in the comparison circuit addresses SSA 37. In SSA 37 signals And[13-15] together with the signal of the RAP are compared with the values given in the diagram specifying the address be 36. When compared to the input D of the first trigger T 44 a permissive signal is received. The PC sends the recording signal MEMW, which passes through the second bus driver chess Federation 21, the fourth bus driver chess Federation 24, the buffer BUF 38 and is fed to the input entered From the first trigger T 44. On the second trigger T 49 is synchronized with the internal frequency MAY 3, a request for direct access HOLD, which enters the Central processor CPU 32. The CPU 32 terminates the current cycle, puts its output in an inactive state, exhibits a signal HLDA - permit direct access, which translates buffer register BR 40, the seventh bus driver chess Federation 41 inactive and permit the passage of signals And[0-16] via a bus amplifiers SHU 33. Address And[0,12,19] in the fifth decoder interrupt vector DSIT 46 forms the cell selection random access memory RAM 45, the address And[1-11] selects the memory cell. Data D[0-15] are the ISA bus 11 through chess Federation 20, chess Federation 26, the interface 12 WHEN the sixth bus driver chess Federation 34 and stored in RAM 45. Thus sequentially from a PC in MAY 3 recorded the entire block transfer. Then the Central processor CPU 32 under the control of the driver that is in constant saponin the next device ROM 47, selects sequentially one byte and writes to asynchronous serial port APT 48. APT 48 issues of bytes in serial code, Reformirovanie bits START and STOP. This byte is supplied to one of the modules convert the signals (MTG 4, block adjustment and control DBK 5, MS 6, MTHD 7, MU 8, MBI 9, MTC/TF 10), where a linear signal of a certain type 13-17 for transmission in the communication channel.

Welcome.

Information from communications channels COP comes in one of the modules 4-10, where the linear signal type 13-17 converted into a signal of RS-232 and enters the asynchronous serial port APT 48, which receives bytes, generates an interrupt request to the second controller interrupt CRC 43. CRC 43 generates an interrupt request INT, which enters the Central processor CPU 32. The CPU 32 terminates the current loop generates two signals INTA, for which the CRC 43 puts the number in the asynchronous serial port APT 48, from which it was interrupted. After that, the CPU 32 takes the byte of data from the APT 48 via the internal serial interface VPI 50, the seventh bus driver chess Federation 41. After receiving the entire data block of the CPU 32 sets the fourth decoder LH 42 address register I / o RVV 35 and writes the address, determining that the unit is ready for transmission to the computer. RVV 35 generates a signal IRQ[10], which, through the fifth and sixth tire is haunted shapers 27, 21 comes into the PC. The PC polls the first controller interrupt CRC 25, reading room MAY 3, from which it was interrupted. After that, the PC reads the contents of register I / o RVV 35 and starts receiving the data block.

PC puts the address on the bus And[0-19] ISA 11, which passes through the first register WG 18 and the third bus driver chess Federation 23. Analyzes the state And[16-19] in the third decoder LH 29. When an address match with the content area D0000 produced signals SCMEM and RAP. The signal SCMEM comes first decoder LH 19 and allows the first bus driver chess Federation 20. The RAP signal is supplied in MAY 3 in the comparison circuit addresses SSA 37. The contents of the address bus And[13-15] RAP signal is compared in SSA 37 values defined in the schema specifying the address be 36. When compared to the input D of the first trigger T 44 a permissive signal is received. The PC sends a signal read MEMR, which passes through the second bus driver chess Federation 21, the fourth bus driver chess Federation 24, the buffer BUF 38 and is fed to the input of the first flip-flop T 44. On the second trigger T 49 is synchronized with the internal frequency of the pulse generator G 31 MAY 3. Output trigger T 49 are formed signals I/O CHRDY and HOLD. The signal CHRDY through sixth bus driver chess Federation 34 comes into the PC and delays the read cycle. The CPU 32 terminates the current cycle, sets si is cash HLDA, which translates buffer register BR 40, the seventh bus driver chess Federation 41 in the inactive state. The HLDA signal allows the passage of a bus address And[0-16] via bus amplifier SHU 33. Address And[0,12,19] in the fifth decoder interrupt vector DSIT 46 forms the cell selection RAM 45. Address And[1-11] selects the desired memory cell. Data D[0-15] of the RAM 45 through sixth bus driver chess Federation 34 is written into the second register WG 30 by signal STB BR, which is formed by the pulse shaper PHI 39. From WG 30 data D[0-15] through the first bus driver chess Federation 20 is supplied to the personal computer, and the read cycle is terminated. Similarly, the PC reads the entire block of data from the adapter module four-channel asynchronous MAA 3.

Industrial applicability

The proposed device is industrially realizable, has more functionality, allowing you to connect to a personal computer compatible with the IBM PC, a large number of communication channels of different types, including those with special equipment.

1. The multiplexer telecommunications multifunctional, modular and contains the system unit that hosts the module four-channel Telegraph unipolar (MTGO) for coupling a multiplexer with four dedicated or switched wire communication channels and convert the Finance logic signals of the multiplexer in the current Telegraph parcel when sending data to the communication channels and convert the current Telegraph parcels in the logical signals, adapted to the multiplexer, when receiving data from a communication channel, four-channel module interface C2 (MS) for electrical matching single-pole circuits internal serial interface (VPI) multiplexer with four double-pole circuits standard interface S2 (RS-232C), the first group of inputs-outputs of which are connected with the tire C2 connect to the physical line module four-channel Telegraph bipolar (MTHD) pairing multiplexer with four dedicated or switched wire communication channels when transmitting bipolar current assumptions, the first group of inputs-outputs of which are connected with tires C1-TG connection to telegraphic communication channels, the module dual iimpulse (MBI) for coupling a multiplexer with two dedicated wire iimpulse communication channels and converting logic signals from the multiplexer in iimpulse signal when transmitting data in the communication channel and the inverse transformation when receiving data from a communication channel, the first group of inputs-outputs of which are connected with tires C1 And connect to the impulse channel module single channel iimpulse (MBI) for coupling a multiplexer with four selected iimpulse communication channel and converting logic signals from the multiplexer p is RS-232C, in iimpulse signal when transmitting data in the communication channel and the reverse conversion when passing data from a communication channel, the first group of inputs-outputs of which are connected with the bus C1-connection and reimburseme channel module single-channel telephone (MTC/TF) for coupling the multiplexer leased and switched telephone communication channels with two-wire and four-wire termination and conversion of the logical signals of the multiplexer in the frequency-modulated signals in accordance with the recommendations of the CCITT v 23 when transmitting data in the communication channel and converting the frequency-modulated signals to logical signals of the multiplexer when receiving data from a communication channel, the first group of inputs-outputs of which are connected with the bus C1-VF connection to a telephone communication channel, and the block adjustment and control (BRC) to control the signal level in the communication channel and control its state in a separate enclosure, the first group of inputs-outputs of which are connected with the first group of input-output module four-channel Telegraph unipolar (MTGO), and the second group of inputs-outputs - with tires C1-TGO connection to telegraphic communication channels, wherein the multiplexer further comprises a structurally placed in the system unit and multiplexer m modules adapter four the channel asynchronous (MAA) to implement link-layer protocols and procedures, interaction with four communication channels in asynchronous full-duplex or half-duplex data transmission mode, the first group of inputs and outputs which are connected via an internal serial interface (VPI) with the second group of input-output module four-channel Telegraph unipolar (MTGO), or module four-channel junction of C2 (MS), or module four-channel Telegraph bipolar (MTHD), or module dual iimpulse (MBI), module single channel iimpulse (MBI) and module single-channel telephone (MTC/TF), cost of group management (PSU) for the formation of the group of main signals and special control signals internal parallel interface (the WHEN) and the implementation of procedures to establish the connection, transformation and control during data transmission and data reception, the first group of inputs-outputs of which are connected through the internal bus of the parallel interface (the WHEN) with groups of second input-output m modules adapter-channel asynchronous (MAA), charge conjugation (PS) to negotiate signals PSU multiplexer system highway ISA control PC, structurally placed in the system unit of a PC, the first group of inputs-outputs of which are connected with the second group of input-output Board group management (PSU), and the second group of inputs-outputs connected to the system bus ISA personal electronic computer, with the compatible with IBM PC.

2. The multiplexer according to claim 1, characterized in that the charge conjugation (PS) contains the first register (WG), an input connected to the ISA bus (A[0-19]), and the output from the first input of the Board group management (PSU), the first decoder (LH), the first and second inputs which are connected respectively with the first (CS MEM) and the second (CS I0) inputs PSU, the first bus driver, the first group of inputs-outputs of which are connected to the ISA bus (D[0-15]), the CS input - output the first decoder LH, and a group of outputs D[0-15] - to the corresponding inputs of PSU, the second bus driver chess Federation, the first group of five inputs connected to the ISA bus (MEM(R), MEM(W), IOR, IOW, AEN), the sixth input - output IRQ[10] Board group management, five outputs connected to inputs of MEM(R), MEM(W), IOR, IOW, AEM Board group management, and the sixth output - ISA IRQ[10], the signal chain I/O CH RDY from the PSU connected to the corresponding circuit of the ISA bus.

3. The multiplexer according to claim 1, characterized in that the card group control (PSU) includes a third bus driver, two inputs of which are connected respectively to the outputs of the And[0-19], AEN Board pairing (PS), and the first output bus, AND WHEN[13-19], the fourth bus driver, four inputs which are connected respectively to the outputs of the MEM R MEM W, IOR, IOW Board pairing (PS), a second decoder, three inputs which are connected respectively with the first output of the third bus FD is MyRoutes and two outputs of the fourth bus driver, and two outputs respectively from the tire WHEN PNU_[0-7], RVR/RU[0-7], the third decoder, two inputs of which are connected respectively with the first SHA[0-19] and the second AEN outputs of the third bus driver and three outputs respectively from the tire WHEN the RAP and outputs MEM CS and CS I/O Board mates PS, the first controller interrupts the CRC, two inputs of which are connected respectively with the third output of the second decoder and bus in the WHEN IRQ[0-7], the fifth bus driver (chess Federation), the first input connected to the bus The WHEN MEM W, sixth bus driver (chess Federation), two inputs of which are connected respectively with the output of the first controller interrupt and I/O CH RDY, and two outputs respectively to the inputs IRQ[10] and the I/O SP RDY Board pairing, the second register interrupt WG, three inputs which are connected respectively with the second output of the first controller interrupt D[0-7], the output of the fifth bus driver D[0-15] and chain MEM W the WHEN, the fourth output of the fourth bus driver and MEM R the WHEN MAA, and the output from entrance D[0-15] Board mates PS.

4. The multiplexer according to claim 1, characterized in that the adapter module four-channel asynchronous (MAA) contains the pulse generator G, the Central processor, the first input connected to the output of the pulse generator, the buffer register, two inputs of which are connected respectively to bus And[0-19] and the second is hodom CPU eighth bus driver, two inputs of which are connected respectively to the bus D[0-13] and the second output of the Central processor and input-output - bus VPI module adapter-channel asynchronous, pulse shaper, the input and output of which are connected respectively with the second output of the Central processor and the bus, the WHEN STB_BR, tire amplifier, two inputs of which are connected respectively with the bus, the WHEN AND[0-16] and the second output of the Central processor, and the output from the output buffer register BR, random access memory, a first input connected to the output of buffer register And [1-11], and the output bus VPI module adapter-channel asynchronous, the fifth decoder interrupt vector, the input connected to the output of buffer register And[0, 12, 19], and the first output to the second input of random access memory, a permanent storage device, a ROM, an input connected to the second output of the fifth decoder interrupt vector, and the output bus VPI module adapter-channel asynchronous, the fourth decoder LH, two inputs of which are connected respectively with the output As[4-6] and the third output of the Central processor, the asynchronous serial ports (ABP 0-3), two input of which is connected respectively with the first output of the fourth decoder and bus And D[0-7], and the first output to one of the input sampling module adapter multichannel asynchronous, the seventh bus driver, two input-output of which is connected respectively with the output-input the WHEN and VPI, and input to the third input of the CPU register I / o, three inputs which are connected to the bus, the WHEN D[0-7] and RVR/RU and the first output of the fourth decoder LH, the first input-output - bus VPI module four-channel asynchronous adapter, the second controller interrupts, six inputs which are connected respectively with the second and third outputs of the register I / o second output asynchronous serial port, the third and fourth outputs of the fourth decoder and the third output of the Central processor, and the output from the second input INT CPU, a scheme specifying the address, the comparison circuit addresses three inputs which are connected respectively with the bus, the WHEN RAP and[13-15] and the output of the circuit specifying the address of the buffer BUF, two inputs of which are connected respectively with the bus, the WHEN MEM(R) and MEM(W), the first trigger (T), two inputs of which are connected respectively to the outputs of the comparison circuit addresses and buffer, the second trigger, two inputs which are connected respectively with the output of the first flip-flop and the output of the pulse generator, and two outputs respectively to the third input HOLD a CPU and the bus, the WHEN the I/O CH RDY.



 

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