Non-destructive reading method

FIELD: data carriers.

SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

 

The technical field to which the invention relates.

The present invention relates to a method of determining a logical state of the selected memory cells existing in a storage device of a passive matrix addressing containing control line (numeric type) and data line (bit bus), in which, in accordance with the specified Protocol specific logic States assigned a unique logical values and in which a memory cell stores data in the form of a state of electric polarization kondensatoprovodov structures containing polarizable material, preferably ferroelectric or electret, which can exhibit hysteresis, as well as to maintain stable electrical polarization in the absence of an external field applied to the specified condensational structures. Selection of cells produced by the activation of the control line and/or line of data skew on the selected cell, while the activation of the control line or the data line is carried out by application of a potential difference between them, with the flow so to the selected cell small-signal probing voltage caused by the applied potential difference and ensure the generation of cells of the current response. Under small-signal excitation voltage is the context of this application refers to the voltage, submission to the memory cell leads to the formation of this cell current response is proportional to the submitted voltage, while maintaining the same direction of polarization in a given cell. In other words, the values of the amplitude and/or duration of the small-signal probing voltage is chosen smaller than the values required to create a substantial permanent changes of the polarization States of these cells. This small-signal probing voltage is time varying, whereas the specified logical state of the cell is determined by detecting the current response of the selected cell components, correlated in time with small-signal excitation voltage or reference signal generated from the specified voltage, and the decision in relation to the logical state of the selected cell are admitted based on a specified comparison of the current response with a set of given criteria.

The level of technology

In recent years demonstrated the storage of data in the electrically polarizable medium consisting of thin films. Of particular interest in this respect are electrets, as well as a ceramic or polymer ferroelectric. When using the logic state of individual memory cells is represented by the direction of vecto is and the polarization of the ferroelectric thin film in the cell. In the case of ferroelectric data is written into the cell by providing a polarization film in the desired direction by applying a correspondingly oriented electric field is more intense than the coercive field in ferroelectric. The main advantage of such materials is that they retain their polarization without a constant supply thereto of electrical energy, i.e. data storage is non-volatile.

Were created storage device (storage device)belonging to two main groups with fundamental differences in the architecture of the device.

In the devices belonging to the first class, each memory cell comprises at least one transistor. In General, the memory architecture of this type matches the type of the active matrix. Its main advantage compared to traditional devices such as SRAM and DRAM is the independence of the logical state stored in the ferroelectric. The need for one or more of the transistors in each cell represents a serious drawback of devices of this type from the point of view of complexity and reducing the recording density of data on the total area of the device.

In the devices belonging to the second class and special interest in the context of the invention, cake memory is used in a passive matrix architecture, in accordance with which two sets of mutually orthogonal electrodes form sets kondensatoprovodov structures in areas of crossing electrodes. Each capacitor forms a memory cell of a type of sandwich with ferroelectric film enclosed between the electrodes.

In accordance with the prior art record in the individual memory cells or read data from these cells is made by application to the material of each corresponding cell in the electric field sufficient to overcome the effect of hysteresis and to Orient the electric polarization in the cell in the direction of the electric field. If the material has already been polarized in this direction up to the application to him of the field, no invert polarization does not occur and flows through the cell, only a small transient current. However, if the material was polarized in the opposite direction, is the inversion of the polarization, which leads to flow much more transient DC. Thus, the logical state, i.e. the direction of the electric polarization in the individual memory cell is determined by the application thereto of an electric field, the intensity of which is sufficient to overcome the coercive field in ferroelectric, and the detection result of the current

Compared with devices based on active matrix, passive matrix devices can be manufactured with a much higher density of memory cells; however, the matrix memory is less complex. However, the known process of reading from such a matrix is destructive, i.e. leading to loss of content in the cell from which you are reading. As a consequence, the data that must be read, must again be written to the storage device, if you want to continue saving data. A more serious consequence of the polarization switching is fatigue, i.e. the gradual loss of the ability to switch polarization. Generally, this phenomenon is accompanied by the necessary application to the cell of a higher voltage for the purpose of inverting polarization. Fatigue limits the number of read cycles that can withstand the particular memory cell. Thereby limited and the range of applications. In addition, fatigue leads to slower response times and higher requirements to the device supply voltage. What if this is a gradual change in performance for individual memory cells in a specific device only in rare cases can be predicted a priori. Therefore, Proektirovanie and operation should be based on the "worst case" which leads to suboptimal modes.

Attempts were made to find solutions to make non-destructive elucidation reading from the memory based on ferroelectric while maintaining a simple architecture of a memory cell.

So, Brennan (C. J. Brennan) in the U.S. patent№5343421; 5309390; 5262983; 5245568; 5151877 and 5140548 describes the ferroelectric capacitor of the cell and their associated elementary modules for reading data storage devices. By sensing capacitance using weak signals with simultaneous application to the ferroelectric moderate fields offset, i.e. fields that do not lead to the creation of the memory cell during the read peak voltage exceeding the coercive field in ferroelectric, is the determination of the direction of spontaneous polarization in the capacitor and, as a consequence, the logical state of the memory cell. However, for practical application of the methods and devices described in these patents requires very specific conditions that lead to the phenomena associated with the accumulation on the electrodes of space charge. These phenomena are directly dependent on the materials used in the electrodes, as well as from adjacent ferroelectric. Reading data associated with the assessment of the space charge, which can be obtained in the scale of BP is like, compatible with the specified charge accumulation. In addition, these patents do not explain how to implement the timing and correlation of the small signal voltage and offset relative to each other, which is essential for use in real conditions. Not explained how you can place and to address memory cells in large matrices, ensuring effective operations read and write.

In international patent application no PCT/N01/00472 belonging to the applicant of the present invention, disclosed a method of providing non-destructive elucidation reading, and device for its implementation with regard to storage devices based on thin-film ferroelectric capacitors. Reading is performed by applying to the memory cell combination time-varying voltage, causing current response in the regime of weak signals (small-signal current response) with linear and nonlinear components, which are processed in order to determine the logic state of each memory cell. Although it is considered in the application of the structure of the memory cells can obviously be adapted to the circuits of the passive matrix addressing, practical solutions such address is not disclosed. This problem seems to the ain, important, because it was her decision will determine whether or not the above-mentioned schemes non-destructive elucidation reader to imagine ultimately practical value or not.

Summarizing the discussion of the prior art, it is possible to conclude that there was a need for devices and methods capable in conjunction with memory cells formed in a memory structure with passive matrix addressing and having the form of a capacitor filled with the electrically polarizable material having hysteresis, for example, ferroelectric, to provide non-destructive elucidation read the data without distorting the read data of spurious contributions from non-addressable cells of the matrix.

Disclosure of inventions

Thus, the main task to be solved by the present invention is directed, is to develop strategies and methods of non-destructive elucidation reading the logical state of the selected memory cells which are addressable by the passive matrix addressing. At the same time should be eliminated distortion of the measurement results due to the contributions of spurious signals due to capacitive connections in the matrix, since it is capacitive coupling will play a major role, for example in the form of capacitive crosstalk signals (charges) from unselected (i.e. non-addressable) cells in the matrix and the and capacitive interference from the network of electrodes and cells, surrounding the selected cell in the matrix.

A further goal of the invention is to describe General procedures and provide concrete examples of devices for implementing the above strategies and methods.

Another problem solved by the invention is the provision of reading in a storage device, essentially free from fatigue, without writeback after each read operation.

The solution of these problems, and the implementation of additional features and advantages provided by the creating method according to the present invention. This method is characterized by the fact that the selected control line and the data line or to the group of control lines and data lines apply time-varying potentials. These potentials are mutually coordinated on the level and time so that the resulting voltage, filed for all or some of the unselected cells in the crossing points between the inactive control lines and the active line data or active data lines and/or between the inactive data lines and at least one active control line, contain only negligible components in a temporary correlation with small-signal excitation voltage or reference signal is, formed from the specified voltage.

Usually (which corresponds to a preferred variant of the method according to the invention) in each moment of time is active, only one control line.

In addition, it is desirable that the inactive control lines and/or a non-data lines were applied potentials that dynamically track with high precision and in real time voltages applied respectively to the active line data and/or to an active control line. In addition or alternative management capabilities on the inactive control lines appropriately be made by the associated signal sources, which receive the input signal from the active line data or from the active data lines for dynamic tracking capacity specified on the active line data or on the specified active data lines.

The control potentials on the inactive data lines should preferably be conducted through the associated signal sources, which receive the input signal from the active control line for the dynamic tracking of the potential for active management of the data line. The management of the potentials on the inactive control lines preferably carried out by them is amerciana through routers (keys) and mounting connections on the value of the potential on the active line data or line data. You can also control the potentials on the inactive data lines through their place through routers (keys) and mounting connections on the value of the potential on the active line data or the active control line.

It may also be appropriate to use when implementing the method according to the invention the active electronic circuit connected to each of the active line data and support given value of the potential on the active line data. In this embodiment, as the set value of the potential it is advisable to choose a ground potential. Preferably also, to all the lines of data were active lines of data. Next, it is advisable to use a multiplexer or a set of routers to alternately connect the active data lines to an active electronic circuit, which maintains a given value of the potential on the active line data.

Alternatively, it may be preferable to use a multiplexer or a set of routers to alternately connect the active groups of the data lines to the group of active electronic circuits that support a given value of the potential on the active data lines. In addition, in this embodiment is considered to be preferable to active electronically the second circuit has provided information about the charge or current, flowing through the active line data.

According to one preferred variants of the method according to the invention inactive control lines zamalchivaut to earth potential via a set of switches or routers.

In addition, multiplexer or a set of routers can be used to alternately connect the active control lines to the electronic circuit that controls the potential on the active control line in accordance with a specified Protocol. In this case, the potential on the active control line preferably is a small-signal probing voltage superimposed on the bias voltage.

According to a first particularly preferred variant of the method according to the invention carried out an analysis of the current response of the selected memory cells using the method of time-window when receiving the synchronizing signals from the circuits that control the potential on the active control line and/or on the active line data or line data.

According to a second particularly preferred variant of the method according to the invention carried out an analysis of the current response of the selected memory cells using synchronous detection when receiving reference signals in the desired frequency range from circuits that control the potential on the active the second control line and/or on the active data lines. When this reference signal is formed from the component of the voltage applied to the selected memory cells, which corresponds to the excitation voltage. Alternative reference signal is formed from the component of the voltage applied to the selected memory cells, which corresponds to the bias voltage. In addition, this analysis can be performed using two reference signals, generated from components of the voltage applied to the selected memory cells, one of which corresponds to the excitation voltage and the other voltage offset.

As another alternative, the analysis is performed using the dominant frequency components, at least one of the following time-varying stress: primary or higher harmonics (e.g., second or third) of the probe voltage when the probe voltage has a single dominant frequency, or a primary or higher harmonics (e.g., second or third) one or more components of the probe voltage in the case where these components have two or more separate dominant frequency, or amount, or the difference between the frequencies generated by the addition and/or subtraction of two or more specified the dominant frequency.

To achieve the objectives and implementation of the l the comparative advantages offered also the first device to implement the method according to the invention. It contains the read amplifier circuits, each of which is connected to one of the data lines and clicks into place on the virtual ground, and a synchronous amplifier connected to the outputs of each of the read amplifier circuit and having input supply reference signal and an output for removing the read signal. The device also contains a combined source of bias voltage and signal, one output of which is connected to the input supply reference signal synchronous amplifier to feed him the reference signal, the active driver control line, which is connected to another output of the combined source bias voltage and signal. The driver output is connected to the multiplexer producing the active control line, and configured to connect to one end of each control line. There is also a set of routers connected to other ends of the control lines to place all inactive control lines to the ground potential. This device is designed with the possibility of parallel reading all the memory cells on the active control line.

In addition, to solve problems and implement additional advantages are offered a second device for implementing the method according to the invention. This device is characterized by the eat, that contains a multiplexer, connected to one of ends of the data lines and engaged in the active line data to read, and the read amplifier circuit, coupled to the multiplexer and clicked on the virtual ground. The structure of the device also includes a synchronous amplifier connected to the output of the read amplifier circuit and having input supply reference signal and an output for removing the read signal, a combined source of bias voltage and signal, the output of which is connected to the input supply reference signal synchronous amplifier to feed him the reference signal. There is also an active driver control line, which is connected to another output of the combined source bias voltage and signal and the output of which is connected to the multiplexer. The multiplexer selects the active control line, and configured to connect to one end of each control line. The device is equipped with the first set of routers connected to other ends of the control lines to place all inactive control lines to the ground potential, and a second set of routers that are configured to connect to the other ends of the data lines to place all inactive data lines to the ground potential. Device is about according to the invention is made with the possibility of parallel addressing all memory cells on the active control line in combination with a sequential read signal from the read amplifier circuit in accordance with the relevant the synchronization Protocol.

Brief description of drawings

The present invention will become clearer from the following detailed description of preferred variants of the invention, which should be read in conjunction with the accompanying drawings.

Figure 1 shows the General view of the hysteresis curve for the storage of ferroelectric material type.

Figure 2 presents the scheme of arrangement of electrodes for the case of passive matrix addressing, for example, applied to the ferroelectric memory used to implement the present invention.

Figure 3 shows a typical small-signal response with respect to, for example, ferroelectric memory cell.

On figa shows an example of voltage curve when reading.

On fig.4b shows the curves of the potential corresponding to the voltage curve when reading.

Figure 5 illustrates the principle of the first variant implementation of the method according to the invention.

Figure 6 presents the modification option in figure 5.

Figure 7 presents another modification of the variant in figure 5.

On Fig presents an example of the arrangement of the read amplifier used in conjunction with the present invention.

Fig.9 illustrates the principle of the second variant implementation of the method according to the invention.

Figure 10 illustrates the structure of the first device is accordance with the invention, intended for realization of the second variant of the method according to the invention.

11 illustrates the structure of the second device in accordance with the invention, also intended for the implementation of the second variant of the method according to the invention.

The implementation of the invention

Before detailed description of the invention will be briefly discussed its physical basis.

Figure 1 shows a typical hysteresis curve for a ferroelectric material having at zero external field the two stable States of polarization, which correspond to the logic state indicated in figure 1 as "0" and "1".

The hysteresis curve corresponds to the values of the electric polarization, expressed in μf/cm2depending on the electric potential V in volts. In the variant shown in figure 1, the positive polarization is taken corresponding to the logical state "0", whereas a negative polarization is logical "1"state. Through Vcmarked the coercive voltage through the PRresidual polarization, and through- the difference between the electric polarization when the saturation voltage and the residual polarization of the PRThen through R*indicated total change of the polarization as a result of its treatment (i.e. changes sign is), that is, when the memory cell is switched from a logic state "0" to logical "1" state (such switching can be destructive when reading the content of the memory cell).

Figure 2 illustrates the location of the electrodes, usually applied in the case of ferroelectric memory with passive matrix addressing. Proper storage environment, i.e. ferroelectric material, is located between the first set of parallel electrodes WL1WLmthat hereinafter will be referred to as the horizontal electrodes and the second set of parallel electrodes BL1-BLnthat are oriented orthogonal to the electrodes of the first set and hereinafter will be referred to as vertical electrodes. All these electrodes form an electrode matrix. Supply voltage for the horizontal and vertical electrodes affects memory cells located in areas of intersection of the electrodes of the matrix. In case of applying voltage to a specific horizontal and vertical electrodes to the selected memory cell is applied potentials. As a result, it will acquire an electric polarization, positive or negative, i.e. corresponding to the logical state "0" or "1"that is defined by the Protocol.

In the context of this izopet is of special attention will be given some specific schemes non-destructive elucidation reading which were mentioned in the analysis of the prior art and are considered relevant to the present invention. In a typical case, the information is read out by measuring the response of the memory cells in the region of small signals when applying to the selected memory cell time-varying probe voltage corresponding to the low signal (low signal voltage) with a simultaneous imposition of the reference voltage with a slower change in time in comparison with the excitation voltage. The logical condition is usually determined by registration according to the received response from the reference voltage. The reference voltage can be made variable according to a predetermined schedule. For example, it can switch between two values that have the same or opposite polarity, or periodically modulated between two limit values. As a small-signal response can be selected, for example, the capacity of the memory cell at the frequency of the excitation voltage. An alternative response might be amplitude or phase of one of the higher harmonics of the recorded signal.

In accordance with the common terminology is further shown in figure 2, the horizontal electrodes WL will be referred to as control lines, and the vertical electron is childbirth BL - the data lines. Those memory cells that are selected for writing, reading, erasing or updates will be referred to as a selected cell, while the other memory cell is unselected cells. The control line WL and line BL data, which is connected to one or more selected cells, respectively referred to as the active control line (AWL) and the active data line (ABL). Similarly, the control line WL and line BL data, which are not connected with any of the selected cells, respectively referred to as an inactive control line (IWL) and inactive line (IBL) data.

Fundamental and recurring problem when storing, reading and erasing data in matrix devices with passive addressing associated with a large number of electrical connections within the network and electrodes of the memory cells in the matrix. In particular, the supply voltage at the intersecting direction lines and lines of data with the aim of addressing a selected cell or group of selected cells in the matrix can lead to an unselected memory cells is the applied voltage, which can have a harmful effect on their logical status. In addition, these unselected cells can contribute to electric charges, and thus to distort the response that metering is located on the addressed cells.

This problem can be illustrated using figure 2. Let's assume you want to read the logical state of the memory cell 1, located at the intersection of the active control line AWL and active line ABL data in the matrix. Suppose further that the information is read out by feeding the cell 1 time-varying voltage and measuring the resulting current response. Because measurements are made by connecting to the active lines AWL and ABL at the edges of the matrix, the potentials applied to these lines are also applied to the unselected cells connected with the data lines. Thus, depending on the total distribution of potentials and impedances of the matrix spurious signals from a large number of unselected cells can contribute to the measured response from the addressed cell 1. Considering the fact that the real storage device may contain a matrix with hundreds or thousands of control lines, this problem is well known to the specialists in the field of electronic engineering.

Passive matrix addressing is unique in that it combines a high density of cells in the memory with the simplicity and flexibility of the architecture. However, developers of the present invention not know of any incoming in the prior art solution to the problem of spurious signals in the storage device the I-V characteristics with passive matrix addressing, using schema non-destructive elucidation reading of the type described by Brennan in the above patent documents or disclosed in the aforementioned international application PCT/NO01/00472, or the like. All these schemes are non-destructive elucidation reading will be of only academic interest, if they will not be able to be combined with a realistic and effective means of addressing.

As noted above, the present invention primarily aims to eliminate contributions from spurious signals such as those due to the presence of capacitive connections. Note, however, that storage devices with passive matrix addressing, the use of which designed the method according to the present invention can be also inductive or radiative coupling, which leads to inductive or radiation interference from the network of electrodes and cells surrounding the selected cell in the matrix. This phenomenon becomes more clear if we consider the matrix memory as a network of capacitive, inductive and resistive elements, through which distributed time-varying voltages and currents having different frequency components. It was, therefore, carried out simulation of large storage devices with passive matrix addressing based on use is the so called simplified model matrix, namely, the model in the form of a circuit with lumped parameters.

In this model, capacitive, inductive and radiative communication between the different lines in the matrix can be described using capacitive, inductive and radiative elements with lumped parameters.

Modeling the field based on a two-dimensional model, to accurately reflect real device, gave a result that cannot be attributed to the unexpected: the main contribution to the spurious signals provide capacitive coupling, whereas inductive connections in practical tasks can be neglected. Radiation effects were also negligible. Despite the fact that the signals propagating in the matrix can have a different frequency components, they can be considered as a slowly time-varying, i.e. having respectively low frequencies. Any capacitive and inductive coupling can be considered as effects in the near field; while the actual dimensions of the matrix ensures the absence of effects of lag. At 1 GHz, the length of the electromagnetic wave is 33 cm, whereas the device, which is applicable the method according to the invention have dimensions that comply with the technology of integrated circuits. In other words, their linear dimensions are of the order of a few mi is limitro, not exceeding 1 cm

The areal density of the data, i.e. the density of cells in a memory device can make it more susceptible to parasitic effects. However, any reduction of the scale line width, pitch matrix and cell size without changing the values of the charge density and voltage field must be accompanied by a corresponding reduction of operating voltages. Therefore, we can conclude that the storage device within any practical problems can be considered as consisting of capacitive structures with lumped parameters or charges with lumped parameters in the network, and during the operation addressing these charges are either static, or change only slightly. This leads, in the extreme case, only the interaction effects of the near field with frequencies significantly below those, which, according to the calculations, can cause any radiation ties. Taking into account the above considerations the following discussion of specific embodiments of the method and device according to the invention should be construed as referring mainly to the decrease in deposits of spurious signals caused only capacitive connections, without the need to pay special attention to inductive or radiac the traditional relations.

Hereinafter the present invention will be described in more detail and specifically on the example of various ways of its implementation.

The main idea of the present invention is based on the observation that the parasitic effects caused by the currents flowing through the cell and the electrodes in the matrix under the action of the potential difference. In other words, the current would cease to flow, if all parts of all matrices were equipotent. However, the processes of reading, relevant to the invention, require application to the selected cells by a time varying voltage.

In accordance with the present invention this problem is solved by the application of time-varying potentials to the electrodes in the matrix so that the appropriate bias voltage and the excitation voltage applied to the selected cells in the presence of a zero voltage on the unselected cells in the dynamic mode. This result is achieved due to the correlated management of time and the level of potential on the control lines and the data lines so that the potentials on the control lines and data lines that cross the unselected cells bound to each other. Thus, if the potential of the control line corresponding to the specific unselected cell is Peter evati changes accurate and real-time playback time-varying potential applied to the data line associated with the same cell, this cell will be equipotential in the dynamic mode. As will be described hereinafter with reference to the preferred embodiments of the control line and the data line crossing at certain unselected cells can both be time-varying potentials synchronized with each other, or to be tied (clicked) to the same quasi-static potential.

Further, the basic principles of the invention will be illustrated using figure 3 and 4. Figure 3 shows the nature of the response in the region of small signals for memory cells, polarized in any direction, the respective logical States "0" or "1". On figa shows the voltage during reading of the selected memory cell. The curve corresponds to the sine of the probe voltage in the regime of weak signals (small-signal probing voltage), superimposed on the bias voltage in the form of rectangular pulses. Let us assume that a memory cell in the regime of low signals are characterized by shown in figure 3 the dependence of the capacitance on the voltage. As you can see, the logical state "0" and "1" can be determined by the supply bias voltage, and Regis the radio net changes of capacitance. The bias voltage may change over time, for example, be in the form of a sine wave or square wave with a period much larger than the period of the small-signal probing voltage used to measure capacity. In the latter case, the observed voltage to the selected memory cell will change in time as shown on figa.

This voltage is generated due to the difference of the instantaneous values of the potentials on the active control line and the active line data skew on the selected cell. The corresponding potentials are indicated on fig.4b as AWL and ABL. Here, the potentials on the active control line and the active line data has the form of sine waves with opposite phases. If you manage the potential on the inactive control lines IWL so that he repeated the potential on the active line data, as can be seen from fig.4b, the potential difference between IWL and ABL (corresponding observed voltage on all unselected cells lying on the active line data at any point in time is equal to zero. Thus, when the registration of the current response with the help of the read circuit connected to the active line data for all cells except the selected will be zero applied voltage.

In many practical situations this simple is rocedure matches potentials on opposite sides of the unselected cells must be supplemented and modified. Depending on which mode you distinguish between logic States (the capacitance dependence on bias voltage, the second or higher harmonic, sum or difference frequency) is the most harmful deposits in the signal from the parasitic currents usually occur at frequencies considerably spaced from the frequencies that are contained in the attached to the selected cell component of the reference voltage, in a typical case, which is low. In this regard, dynamic equalization potential control line and the data line in many cases should take place only at certain specific frequencies, which are extracted from the total voltage applied to the selected memory cells. As a simple example, you can specify the case when the measurement of the capacitance dependence on the reference voltage is made using high frequency probe voltage with frequency ωimposed on low-frequency reference voltage having the frequency Ω. Assuming that the response is linear, in this case, it is sufficient to provide equipotential bonding direction line and the data line to the unselected cells on the frequency ω.

As already mentioned, the present invention focuses on eliminating or reducing the effect of capacitive connections. Therefore, the most important aspects is the ohms of the invention is the elimination of capacitive crosstalk in the reading process.

At high frequencies the reading results can be distorted by parasitic noise due to inductive and radiative relations, due to the control lines and data lines in other parts of the matrix. Although both of these types of interference, as shown above, are not as serious further and not just a minor aspect of the present invention is to minimize interference from spurious signals, is also due to the relationship data types. In accordance with one class of embodiments of the invention this task is solved in that during a read cycle, all non-addressable control lines and data lines to simultaneously change the potential of simulating the relevant components of the signal present on the active line data or group of data lines. Of course, this option ignores the effects of delay, however, in most real storage devices each addressable matrix is sufficiently small, and the frequency is low enough to consider the approximation was acceptable.

Shown in figa and 4b is an example of the excitation of a single cell shows that the capacitive coupling of the unselected cells on the inactive control lines crossing the active line data can be avoided by coordinated padinipadini on all the inactive control lines thus what to addressable cell is applied only small-signal excitation voltage, which is not negligible. Next will be considered the problem of implementing the principles of the present invention as applied to matrices containing the set of control lines and data lines. Will be described some preferred variants of the invention. Note that the examples in no case do not exhaust the entire scope of the invention.

The first variant implementation of the method according to the invention will be discussed with reference to figure 5-8, illustrating the addressing of a single randomly selected memory cell.

Figure 5 shows an example of reading from a single memory cell in the case of passive matrix addressing, which is used to read the active control line AWL and active ABL data line electrically isolated from the inactive control lines and data lines.

Figure 5 shows how the tip of the unselected cells on the active control line AWL and active ABL line of data is avoided by coordinated supply voltage to all of the inactive control lines IWL and lines IBL data so that the addressable cell 1 is applied the voltage, which is not negligible. As can be seen from figure 5, the effect of PR is the, all inactive control lines IWL repeat the instantaneous potential on the active line ABL data. All inactive line IBL data replicate the potential on the active control line AWL. Thanks to any unselected cell on the active control line AWL, and any unselected cell on the active line ABL data is not applied no pressure.

In the scheme shown in figure 5, the active and inactive control lines and data lines are fed from two galvanically separated but mutually coordinated generators 2, 2' signals. In the result of measurement of capacity addressable cell 1 can be made directly on the pins of the direction line and the active line data using various technologies and equipment.

Figure 6 shows how the detection of the current response with the help of the read amplifier circuit 3, is installed on an active payline ABL data, while the active power control line AWL is supplied from the oscillator 2 signal with low impedance. As shown in the drawing, inactive line IBL data can be associated with active management line AWL. Thus, presented on Fig.6 option can be viewed as a subclass of the scheme shown in figure 5, in which the inactive line IBL these right near St the bound state (clicked) voltage to the active control line AWL. The oscillator 2 signal to the control line in this case is seen as having a very low impedance, and the current response is detected the read amplification circuit 3 which detects the current flowing in the process of implementation of the Protocol cycle read on an active payline ABL data. The potentials on the inactive control lines IWL replicate the potential on the active line ABL data due to the presence of the slave generator 2', also shown in figure 5. Although inactive line IBL data do not contribute due to capacitive coupling to the signal on the active line ABL data presented on Fig.6 scheme has certain useful properties, in particular, because it provides management capabilities on the inactive lines IBL data. As a simpler alternative, of course, is to disable inactive data lines from a voltage source.

Figure 7 presents a scheme similar to scheme 6. Selected and in this case is cell 1; however, now all lines WL; BL in the electrode matrix bound (clicked) by using the slave oscillator 2' to the potential of the active line data. Thus, 7 is another subclass of scheme 5. In this case all the lines in the matrix, except for the active control line AWL, play the potential of the active line ABL data. The advantage of this scheme is the fact eliminated the influence of skew with active control line is inactive control lines IWL as sources of spurious signal, and it will also prevent interference from other parts of the matrix, in particular capacitive tip-off from adjacent lines of data.

Modification of the first variant embodiment of the invention shown in figure 5, 6 and 7, provide a nearly zero voltage on all cells in which the active line ABL data hybridizes with inactive control line IWL. In the only non-negligible contribution to the current flowing through the read amplifier circuit 3, proceeds from the addressable cell 1. The read amplifier circuit 3 may be configured as shown in Fig. Fig also shows that the active line ABL data can be defined as the line that has the potential of virtual ground. Such a scheme is the standard for measuring the capacity, but it can be used in any other detection schemes that are relevant in the context of the invention. In the case of using an operational amplifier with high gain input amplifier and, therefore, the data line can be locked at a desired, arbitrary potential. In many practical circuits, this potential is identical to the potential of the grounding system. In this case, the point of connection to the active line ABL data will hereinafter be called virtual point ZAZ is Melania. From Fig.7 we can see that when using contour detection with virtual grounding of the entire matrix, except for the active control line AWL, is at earth potential. This scheme has obvious advantages in terms of simplicity and shielding of interference from spurious signals. In this case, the peak-to-peak voltage (bias voltage and the excitation voltage applied to the selected cell 1, a fully active set control line AWL, while maintaining the basic principle of equalization of the potentials applied to the unselected cells.

Next, with reference to Fig.9, the description of the second variant implementation of the method according to the invention, in accordance with which is parallel addressing of control lines WL. Again, use the passive matrix addressing, but now with the simultaneous addressing the whole row of memory cells on the control line by the suppression of spurious signals.

According to this second variant, each line of data is read in parallel with one or more lines of data, potentially with all the other data lines by using a separate readout amplifier circuits 3 connected to each line BL data. Thus, during the cycle of reading the entire matrix, except for one addressable control line AWL, may derivatise at the same potential. So, all the inactive control lines IWL connected to the source of the selected potential, e.g. ground potential, whereas the active control line AWL is connected to the signal generator 2, which provides a development bias voltage and small-signal probing voltage. The signal generator 2 has a low impedance, i.e. it is able to support the programmed value, the bias voltage and the excitation voltage connected to it by the active control line AWL unaffected by leakage currents in the data lines intersecting with the active control line. Each individual line BL data is connected to the read amplifier circuit, for example, shown in figure 7. The result can be determined the value of the current in each line of data. The potential at the inputs of the read amplifiers and, therefore, on lines BL data is maintained at virtual ground. This ensures that there is no capacitive charge transfer in cells connecting line BL data from inactive (non-addressable) direction lines IWL.

When using this variant can be implemented two important advantages.

1) In addition to the elimination of capacitive crosstalk on an active payline ABL data from charges, Eleusis is on unselected cells, it is also desirable to minimize crosstalk due to capacitive, and in some cases also inductive and radiative relationships in other areas of the matrix addressing. Such problems are exacerbated with increasing frequency signals and/or reduce the physical distance between the control lines and data lines, i.e. the improvement of structures to achieve higher performance. When using this preferred option it is possible to achieve a significant reduction of interference from spurious contributions in the read signals, since all matrix (except for the active control line) can be maintained at the same potential, e.g. ground potential. This provides the opportunity to greatly reduce spurious noise on the read signals.

2) Since each line BL data hybridizes with active (addressable) direction line AWL and is associated with its own readout amplifier circuit 3, it becomes possible to perform reading in parallel to all cells in addressable control line AWL, with a corresponding increase in the speed of data output from the matrix.

For specialists in the field of electronic technology should be obvious that the second variant embodiment of the invention provides the capability is there potential simplification of the control circuit due to the direct installation.

This situation is illustrated in figure 10 and 11 are respectively diagrams of the first and second devices designed for the implementation of the second variant of the method according to the invention.

In the above-described scheme with simultaneous access to the full control of the line was taken that each data line is connected with their individual reading amplifying circuit 3. Generally, it is desirable to arrange the cells in the matrix with the highest possible density that corresponds to the minimization step of the data lines. This, however, leads to a lack of space to accommodate the read amplifier circuits at the edge of the matrix, and this problem is exacerbated as the complexity of such circuits.

One of the ways to solve the problem of lack of space is to reduce the number of driver circuits for the control lines and the number of the read amplifier circuits by connecting them to the control lines WL and lines BL data in the matrix by means of switches (routers). Accordingly, figure 10 presents the device according to the invention, intended for the implementation of the scheme read all of the control word using a multiplexed connection active control line, synchronized with switchable connection inactive control lines IWL to potentialization, in combination with the connecting lines BL data to the potential of the virtual ground through contour detection.

As can be seen from figure 10, to one end of each line BL connected data readout amplifier circuit 3, is similar to Fig and under the potential of the virtual ground. To each of the read amplifier circuit 3 connected synchronous amplifier 4 having input supply reference signal and an output for removing the read signal. The reference signal is generated combined channel 5 bias voltage and signal and the reference signal from this source supplied to the synchronous amplifiers 4. Source 5 bias voltage and signal is also output associated with the driver 6 active control line, the output of which is connected with AWL-multiplexer 7, producing the selection of the control line WL to be read, i.e. it is active multiplexer control line AWL. Simultaneously AWL-multiplexer 7 delivers, when necessary, the bias voltage on the inactive control lines IWL. The opposite ends of the control lines are connected with a set of 8 routers that allow you to connect an inactive control lines IWL to the earth potential through the respective switching means 8'. This provides the opportunity to read the full direction line, i.e. parallel read from all memory cells 1, in which lines BL data crossed with active control lines AWL.

Figure 11 shows a second device according to the invention, similar in many respects to the device according to figure 10, but using the connection lines BL to a data circuit detecting through the multiplexer. More specifically, the device 11 of the read amplifier circuit 3 is connected to the selected active line ABL data through ABL-multiplexer 9 active data lines that can connect to one of the ends of the lines BL data. As before, the read amplifier circuit 3 clicks into place on the virtual ground, and its output connected to the input of a single synchronous amplifier 4 having an outlet for removing the read signal and the input supply reference signal from the combined source 5 bias voltage and signal. Execute combined source 5 bias voltage and signal driver 6 active control line and AWL-multiplexer 7 active control line is the same as that in the device according to figure 10; naturally, these components perform the same functions. In addition, the opposite ends of the control lines WL in the device 11 also includes a set of 8 routers that allows you to connect an inactive control lines IWL to the earth potential h is cut switching means 8'. However, in the device 11 are additionally provided with a second set of 10 routers that are located at opposite ends of the lines BL data and similarly containing switching means 10', allowing you to lock inactive line IBL data on the same earth potential, and an inactive control lines.

As you can see, the device 11 implements the schema read a full line, which to some extent resembles the schema read full string with destructive readout described in patent documents belonging to the applicant of the present invention. However, it must be emphasized that, in contrast to schemes with destructive readout, the device according to the invention read in full lines in combination with multiplexing can be performed without loss of data. Since in this case the reading is non-destructive elucidation of the cell line data, which are not addressed by switches (routers) in a particular cycle, read, preserve its logical state. Thus, the reading of the complete row of cells can be performed by repeated excitation full control lines coupled with consistent reading, implemented the read amplifier circuit (or circuits).

For specialist is in the relevant field should be obvious, that the described embodiments of the method and device according to the invention are given only as examples and in no case should not be construed as making any restrictions. It should be clear that the experts in this field can offer other schemes to perform the necessary functions of switching and multiplexing, as well as your functions to be implemented when carrying out the method according to the present invention, without imposing any restrictions on this method and with the achievement of the main objective of the invention consisting in the exclusion of capacitive connections in memory with passive matrix addressing, consisting of a set kondensatoprovodov structures containing polarizable storage material, by providing a zero potential difference at the unselected cells.

1. The method for determining the logical state of the selected memory cells in a memory device with passive matrix addressing containing control line and the data line, in which in accordance with the specified Protocol specific logic States assigned a unique logical values and in which a memory cell stores data in the form of a state of electric polarization kondensatoprovodov structures containing polarizable material, preferably ferroelectric or electret the first, able to show hysteresis, as well as to maintain stable electrical polarization in the absence of an external field applied to the specified condensational structures, the choice of the cells produced by the activation of the control line and/or line of data skew on the selected cell, while the activation of the control line or the data line is carried out by application of a potential difference between supply thus to the selected cell small-signal probing voltage caused by the applied potential difference and ensure the generation of these cell current response small-signal probing voltage is time varying, and the values of its amplitude and/or duration is chosen smaller than the values needed to create significant permanent changes of the polarization States of these cells, with the specified logical condition is determined by detecting the current response of the selected cell components, correlated in time with small-signal excitation voltage or reference signal generated from the specified voltage, and the decision in relation to the logical state of the selected cell are admitted based on a specified comparison of the current response with a set of criteria, otlichuy is the, what to the selected control line and the data line or to the group of control lines and data lines apply a time varying potentials, which are mutually coordinated on the level and time so that the resulting voltage, served on some or all of the unselected cells at the points of crossing between the inactive control lines and the active line data or active data lines and/or between the inactive data lines and at least one active control line, contain only negligible components in a temporary correlation with small-signal excitation voltage or reference signal generated from the specified voltage.

2. The method according to claim 1, characterized in that in each moment active is only one control line.

3. The method according to claim 1, characterized in that the inactive control lines and/or a non-data lines is applied potentials that dynamically track with high precision and in real time voltages applied respectively to the active line data and/or to an active control line.

4. The method according to claim 3, characterized in that the control potentials on the inactive control lines shall be implemented by the associated signal sources, which receive the Ute input signal from the active line data or from the active data lines for dynamic tracking capacity specified on the active line data or on the specified active data lines.

5. The method according to claim 3, characterized in that the control potentials on the inactive data lines is realized by means of the associated signal sources, which receive the input signal from the active control line for dynamic tracking capacity at the specified active control line.

6. The method according to claim 3, characterized in that the control potentials on the inactive control lines carry through their place through routers and wiring connections on the value of the potential on the active line data or line data.

7. The method according to claim 3, characterized in that the control potentials on the inactive data lines carry through their place through routers and wiring connections on the value of the potential on the active line data or the active control line.

8. The method according to claim 1, characterized in that use active electronic circuit connected to each of the active line data and support given value of the potential on the active line data.

9. The method according to claim 8, characterized in that the set value of the potential is chosen earth potential.

10. The method according to claim 8, characterized in that all data lines are active data lines.

11. The method according to claim 8, characterized in that the use of multiple the PR or set of routers to alternately connect the active data lines to an active electronic circuit, which maintains a given value of the potential on the active line data.

12. The method according to claim 8, characterized in that the use of a multiplexer or a set of routers to alternately connect the active groups of the data lines to the group of active electronic circuits that support a given value of the potential on the active data lines.

13. The method according to claim 8, characterized in that active electronic circuit provides information about the charge or the current flowing in the active line data.

14. The method according to claim 1, characterized in that the inactive control lines zamalchivaut to earth potential via a set of switches or routers.

15. The method according to claim 1, characterized in that the inactive data line zamalchivaut to earth potential via a set of switches or routers.

16. The method according to claim 1, characterized in that the use of a multiplexer or a set of routers to alternately connect the active control lines to the electronic circuit that controls the potential on the active control line in accordance with a specified Protocol.

17. The method according to item 16, characterized in that the potential on the active control line is a small-signal probing voltage superimposed on the bias voltage.

18. The method according to claim 1, distinguishing the I, that analyze current response of the selected memory cells using the method of time-window when receiving the synchronizing signals from the circuits that control the potential on the active control line and/or on the active line data, or on an active payline data.

19. The method according to claim 1, characterized in that conduct analysis of the current response of the selected memory cells using synchronous detection when receiving reference signals in the desired frequency range from circuits that control the potential on the active control line and/or on an active payline data.

20. The method according to claim 19, characterized in that the analysis is performed using the reference signal generated from the component of the voltage applied to the selected memory cells, which corresponds to the excitation voltage.

21. The method according to claim 19, characterized in that the analysis is performed using the reference signal generated from the component of the voltage applied to the selected memory cells, which corresponds to the bias voltage.

22. The method according to claim 19, characterized in that the analysis is performed using two reference signals, generated from components of the voltage applied to the selected memory cells, one of which corresponds to the excitation voltage and the other voltage offset.

Cab according to claim 19, characterized in that the analysis of the current response is performed using the dominant frequency components, at least one of the following time-varying stress: primary or higher harmonics (e.g., second or third) of the probe voltage when the probe voltage has a single dominant frequency, or a primary or higher harmonics (e.g., second or third) one or more components of the probe voltage in the case where these components have two or more separate dominant frequency, or amount, or the difference between the frequencies generated by the addition and/or subtraction of two or more these dominant frequencies.

24. The device for implementing the method according to claim 1, is made connected to the ferroelectric storage device or forming part of, and the storage device comprises a memory cell in the passive matrix addressing, in which the first and second sets of electrodes formed respectively control lines (WL) and line (BL) data storage device, characterized in that it contains the read amplifier circuits (3), each of which is connected to one of the lines (BL) data and clicks into place on the virtual ground, synchronous amplifier (4)connected to the outputs of each of the read amplifier is on a path (3 and having input supply reference signal and an output for removing the read signal, combined source (5) of the bias voltage and signal, one output of which is connected to the input supply reference signal synchronous amplifier (4) to submit to it the reference signal, the driver (6) active control line, which is connected to another output of the combined source (5) of the bias voltage and signal and the output of which is connected with AWL-multiplexer (7), producing the choice of active control line, and configured to connect to one end of each control line (WL), and set (8) routers associated with the other ends of the control lines (WL) to place all inactive control line (IWL) to the earth potential, and the device is made with the possibility of parallel reading all the memory cells on the active control line (AWL).

25. The device for implementing the method according to claim 1, is made connected to the ferroelectric storage device or forming part of, and the storage device comprises a memory cell in the passive matrix addressing, in which the first and second sets of electrodes formed respectively control lines (WL) and line (BL) data storage device, characterized in that it contains ABL-multiplexer (9)connected to one end of the line (BL) data and performing the selection of the active line (ABL) for reading, the read amplifier circuit (3)connected with ABL-multiplexer (9) and clicked on the virtual ground, synchronous amplifier (4), connected to the output of the read amplifier circuit (3) and having input supply reference signal and an output for removing the read signal, the combined source (5) of the bias voltage and signal, the output of which is connected to the input supply reference signal synchronous amplifier (4) to submit to it the reference signal, the driver (6) active control line, which is connected to another output of the combined source (5) bias voltage and signal and the output of which is connected with AWL-multiplexer (7), producing the choice of active control line, and configured to connect to one end of each control line (WL), the first set (8) routers associated with the other ends of the control lines (WL) to place all inactive control line (IWL) to the earth potential, and a second set (10) routers are designed to connect to the other ends of the lines (BL) data to place all inactive lines (IBL) data at earth potential, and the device is made with the possibility of parallel addressing all memory cells on the active control line (AWL) in combination with consistent reading of signals from SGAs is yvouxeo amplifier circuit (3) according to the corresponding synchronization Protocol.



 

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