Multi-dimensional addressing structure for electronic devices

FIELD: electronics.

SUBSTANCE: device for providing possible addressing in device, containing one or more volumetric element, in form of memory cells, display cells, diodes, transistors and/or switching/modulating elements and forming together with said device a portion of two-dimensional or three-dimensional matrix being a component of said device, contains three sets of electric-conductive lines or ribbon electrodes, forming an additional portion of said matrix. Device for storing and/or processing data or receipt and/or processing, and/or displaying of signals contains said means and more than one matrix, while said matrices are made in form of stack, accurately placed on substrate, and device forms a volumetric structure dependently on functional properties of each matrix in a stack.

EFFECT: broader functional capabilities.

2 cl, 23 dwg

 

The technical field to which the invention relates.

The present invention relates to providing an opportunity of addressing the device containing one or more volume elements. Volume elements in the specified device, forming together with the above mentioned equipment part of a two-dimensional or three-dimensional matrix, constitute a memory cell, the cell displays, diodes, transistors and/or switching/modulating elements. To perform these functions each volume element contains one or more cells, with, depending on the electronic or electrical properties of the material of this element, the functionality of data storage, data processing or signal processing. This tool provides the ability to address site-specific three-dimensional element by establishing a selective electrical connection with a volume element or cell (in the case where the volume element contains more than one cell). Accordingly, the choice of a particular volume element or cell is done by creating not necessarily simultaneous electrical connections with three or more electrodes. These electrodes are formed by specified means and are in contact with a volume element for the implementation of selective interaction with him is but the plot of this element, located in close proximity to the electrodes, so that the specified area defines a cell in a specified volume element, which is therefore the interaction.

The invention relates also to a device containing the described means forming in conjunction with one or more volume elements part of a two-dimensional or three-dimensional matrix composed of the specified device. At the same time the volume element contains one or more cells having (possessing), depending on the electronic or electrical properties of the material of the cell, the functionality of data storage, data processing or signal processing. The device contains more than one matrix of the type described.

In a broad sense, the present invention provides addressing architecture, which provides electronic access via the N pins to volume elements or zones in a two-dimensional or three-dimensional matrix structures in which the number N of the conclusions that must be made the connection for each address in the matrix is at least three.

The level of technology

Orthogonal two-dimensional matrix addressing is very widely used in many different electronic devices, such as cameras, memory devices (storage device), and displays, in which you must ensure is ü individual electronic access to each individual element of the matrix.

The simplest type of such a matrix consists of a single set of mutually parallel electrode lines (referred to hereinafter for short "a electrodes"), lying in the same plane near the other, parallel to the plane containing a different set of mutually parallel electrode lines (referred to hereinafter for short "b-electrodes"). The sets of electrodes "a" and "b" are oriented so that they are crossed, usually orthogonal, thus providing the possibility of volume elements located between crossing electrodes. Thus, the volume element between the electrode andiin the set of electrodes and the electrode biin the set b-electrodes can be affected by electrically connecting the electrodes andiand bito an appropriate source of current or voltage. Three-dimensional elements may include active circuit elements, can be started by applying to them the input signal. Alternatively, they may be implemented as a switching or passive elements, the physical condition which can be changed by application of an input signal or defined when addressing electrodes "a" and "b". Such elements can be, in particular, used to build memory elements for storing binary or multi-level logic the ski values.

The device is based on the use of matrices of the type described, disclosed, for example, in international application no PCT/NO 98/00185 (similar to U.S. patent No. 6055180)owned by the applicant of the present invention. It is a passive device with electrical addressing, which can be applied in optical receivers, surround memory devices or data processing. The known device comprises a functional medium in the form of a continuous extended or shaped structure that can change its physical or chemical state. This functional environment, which in the framework of the present invention corresponds to the volume element, is composed of individually addressable cells, formed between the anode and cathode forming part of the electrode means in contact with the functional environment in the cell and thereby provide electrical connection with the cell. The anodes are made in the form of the first set of strip electrodes arranged in a layer in contact with the functional environment on one side. Similarly, the cathodes are made in the form of a second set of mutually parallel strip electrodes arranged in a layer in contact with the functional environment on the other side. When this tape electrodes within each set of mutually parallel the us, and the mutual orientation of the sets of electrodes such that the electrodes of one set are oriented orthogonal with respect to the electrodes of the other set.

Real cell volume element of the functional environment in this case is specified in the zone of mutual spatial overlap (i.e. crossing) tape electrode of the first set and the ribbon electrode of the second set. When addressing a cell in the known device, for example, to perform a recording, scanning or switching (i.e. changes the logical value assigned to a cell), electrical energy is applied directly to the functional environment of the cell through the selected pair of crossed electrodes included in the first and second sets of electrodes.

International application number PCT/NO 98/00212, also owned by the applicant of the present invention, describes a similar device. However, it uses an electrode matrix of sets of electrodes, mutually insulated and made in the form of bridges. When this functional environment covers and closes the specified sets of electrodes. In addition to its possible use as a memory device with electrical addressing this scheme with electrodes that are used as bridges and closed functional environment (in contrast to the previously described device, in which the functionality of the other medium is enclosed between the electrodes), more easily applicable, for example, optical or electronic camera or display with electrical addressing.

Finally, in international application no PCT/NO 98/00237 owned by the same applicant, describes a ferroelectric device for processing and/or storing data from the passive electrical addressing of the functional environment, which is a thin film of ferroelectric material is deposited on top of the sets of electrodes and closing sets of electrodes, which in this case is made in the form of bridges.

Across all of these known devices functional environment, the corresponding volume element positioned between sets of electrodes or on top of them, may be applied in the form of global (i.e. a single continuous layer, in which, of course, an individual cell will be determined by the mutual overlap of the electrodes of the first and second set of electrodes. However, functional environment can be structured or divided into pixels, so that in the zones between the mutually superimposed (crossed) electrodes or over them will be generated individual volume elements. Thus, in this case, the volume element will contain only one cell. This, of course, does not affect the total possible number of cells in the matrix, which, essentially, will ravnets is the product of the number of electrodes in each set.

Systems and matrices of the type described, for storing or processing the electrical signals, the elements of the system or matrix, defined in this way may include, depending on the particular application, the various components and circuits. However, each area of the electrodes can be made from the outside only two electrical connections. Thus, two sets of electrodes, giving only two connections, can provide individual (exclusive) addressing of devices or circuits having not more than two conclusions.

Currently, there are different approaches to working with electronic systems, based on matrices, where each matrix element requires more than two conclusions. In SRAM technology memory cells require more than two lines, in particular, four lines: Vcc, bit, bit, and word (number). A known solution for matrix addressing of cells in SRAM technology is shown in figure 1. It uses two parallel lines, Vcc line and the number line that is oriented perpendicular to the other two parallel lines, i.e. bit and bit-lines. No individual addressing is impossible between two parallel lines, for example, between bit and bit-lines.

Another known solution for individual addressing between more than two lines (or electrode and) are presented in figure 2. Here we use three-dimensional matrix. Individual addressability is provided between a specific set of lines, namely aibjand ck. In case you choose the combination andibjprovides choice of column, i.e. addressing the specific element does not occur until you have selected ck. Access to any element for which fulfilled the requirement i∈(1, imax), j∈(1, jmaxand k∈(1, kmax), can be provided using, for addressing combinations andibjand ck.

Physical realization of addressing schemes discussed above, is not simple, when access to each element in the matrix should be not less than three output.

In known two-dimensional diagrams of the type discussed above with reference to figure 1, for SRAM devices electronic circuits in a typical case are based on quasiplanar principle, when the physical position of the element in the matrix is defined by two coordinates. When the layers are bonded to each other by sequential deposition, masking and etching, which includes precision settings, etc. this approach provides only limited opportunities for further expansion and limited flexibility and leads to rapidly increasing topological complexity increases to the number of pins in each point of the matrix.

As for true three-dimensional diagrams matrix addressing type presented in figure 2, the applicant did not know examples of known devices, characterized by high density and manufactured by the methods of mass production. In practice, schemes of functional addressing for three-dimensional matrix addressing present challenges to implementation while providing low complexity and good compatibility with a simple and inexpensive methods of manufacture.

The invention

Thus, the main task, which directed the present invention is to overcome the above disadvantages of the known devices by creating a basic architectures for addressing electronic devices or elements having N outputs (N>2) and physically located in a matrix in two or three dimensions.

Another goal of the present invention is to create a simple and practical means for individual connection of a single element with N conclusions in a two-dimensional matrix having n external findings for applying current or voltage, where 2≤n≤N.

These tasks, as well as various properties and advantages are achieved in accordance with the present invention by creating tools to enable addressing in the equip, containing one or more volume elements, which is characterized in that it contains at least three sets of conductive lines (e.g., tape electrodes) to the location specified tape electrodes in each set are mutually parallel in the corresponding two-dimensional planar layer, forming an additional part of said matrix, at a mutually parallel arrangement of layers in which are located the tape electrodes, and a set of strip electrodes in one of said layers is oriented at an angle to the projection of strip electrodes of adjacent layers in the layer, with the result of mutually orthogonal arrangement of the sets of strip electrodes of adjacent layers. These electrodes are in contact with the specified section of a volumetric element, formed by mutual spatial overlap of three or more of these strip electrodes in said respective sets of electrodes in contact with the specified volume element, so that the specified cell or cells of a specified volume element is (are) in the zone of overlap of the three or more belt electrode, whereas the selective addressing of the cell is performed by applying current or voltage to the selected tape electrode in each set of electrodes at the same time, what about the or in a certain time sequence, defined pre-specified Protocol addressing.

In a preferred embodiment of the specified means according to the invention, essentially parallel to the tape electrodes in the set of electrodes are equidistant.

According to another preferred variant of the tool according to the invention the set of electrodes in the matrix is deployed at a given angle or at different preset angles around an axis essentially perpendicular to the matrix, relative to the adjacent electrode sets to prevent conformal imposition of strip electrodes in adjacent electrode sets. In this case, it is desirable that all the sets of electrodes in the matrix are mutually deployed at a given angle or at different preset angles around the specified axis to prevent the conformal imposition of strip electrodes in any of the electrode sets. Alternatively, the angle spread of the set of electrodes relative to the next adjacent set of electrodes may be selected equal to 2π/m·N (i.e. 360°/m·N), where N is the number of electrodes in contact with the output cell, a m is an integer when m<N.

In several preferred embodiments the means according to the invention it contains three sets of electrodes for providing electrical connections to the cells, with up to tre the conclusions or, alternatively, a set of four electrodes to provide electrical connections to the cells, with up to four conclusions. The tool can also contain three sets of electrodes to provide electrical connection of at least two cells, with up to two conclusions each.

The number of strip electrodes in the respective electrode set is selected according to the invention based on the number and geometric configuration of the cells in the matrix in such a way as to maximize the number of addressable cells in the matrix. While it is desirable that the number of strip electrodes in the respective electrode set was chosen from the condition allow addressing of individual cells in the matrix.

In a variant of the invention, corresponding to the case where each cell in the volume element in the composition of the matrix is provided with at least two terminals, it is preferable to perform the electrode layers and the layer or layers forming a volume element in a multilayer structure with alternating layers, with the possibility of contact interaction between the electrode adjacent to the surface of at least one layer of a volumetric element, and this layer. In this case, the overlap between the strip electrodes in each electrode layer will determine achak the volume element, moreover, the tool according to the invention preferably also contains a diode transition between the electrode at the area of the overlap of the electrodes and the cell formed in this zone.

Finally, if one or more cells comprising a volumetric element contains at least one transistor structure, in the appropriate version of the tool according to the invention, one electrode in at least two sets of electrodes are preferably electrically connects the above transistor structure with one another through their findings. If one or more cells comprising a volumetric element contains more than one transistor structure, one electrode in at least two sets of electrodes electrically connects the above transistor structure with one another through their findings.

Device for storing and/or processing data or receiving and/or processing and/or display signals according to the present invention is characterized by the fact that its constituent matrices made in the form of the foot, so that the device forms a three-dimensional structure based on the foot matrices for data storage, data processing or signal processing depending on the functional properties of each matrix in the foot.

In accordance with a preferred variant of the invention, the proposed device to perform the network on the substrate, bearing integrated circuits connected to the electrodes of the specified funds to ensure the implementation of management functions, control and correction of errors in the cell volume of matrix elements.

List of figures

Further features and advantages of the proposed solution will become apparent from the following detailed description and the accompanying claims.

Next, you will see a more detailed description relating to preferred options, which will be considered in conjunction with the attached drawings.

Figure 1 presents the above-mentioned known matrix addressing with four lines (buses).

Figure 2 presents also mentioned known three-dimensional orthogonal matrix scheme.

On figa, 3b presents known orthogonal scheme matrix addressing for devices with three terminals consisting of two blocks with two outputs.

Figure 4 illustrates the matrix addressing, made using the present invention.

On figa-5d are examples of the implementation of the first version of the matrix addressing.

On figa-6f are examples of the implementation of the second variant of matrix addressing.

On figa-7E are examples of the third variant of matrix addressing.

On figa, 8b presents an example of executing prefer inogo variant of the present invention.

Figure 9 presents an example of executing variant of the invention, in which elements in the matrix have the properties of a rectifier diode

Information confirming the possibility of carrying out the invention

As mentioned in one of the previous sections, figure 1 shows a known addressing scheme for the four memory cells of the type SRAM in planar orthogonal matrix. To perform the update, read and write 4 lines. If the selected bit and-bit addressing is performed to the entire column.

Figure 2 shows in three dimensions also mentioned formerly known orthogonal scheme matrix addressing elements having three output. Each point of overlap of the electrode lines specifies a physical coordinate in the matrix and can maintain a path or element with three conclusions.

In order to best represent the current level of technology and the basic ideas of the present invention, hereinafter will be briefly described, as may be addressing in the known device with three terminals consisting of blocks with two terminals each, using three groups of parallel electrodes oriented orthogonally with respect to a located above them or below them to the set of electrodes. However, in this regard it is important to note that the device submitted is a simple application of known principles of passive matrix device with the addressing of cells, asked mutual spatial overlap of the electrodes. As a consequence, it has the same shortcomings that have been mentioned in the description section relating to the state of the art.

If each element of a two-dimensional set contains two blocks, each of which has two outputs, addressing this element can in principle be carried out by means of an orthogonal passive matrix network. The well-known scheme of this type is shown in figa, 3b, which presents only three electrode layer 1, 2, 3 in the foot, which can contain a much larger number of layers. Two elements M1, M2, located as shown on figa, between the zones of overlap of the electrodes (e.g. electrodes 1 and 2 and 2 and 3), can be addressed separately by appropriate activation of mutually superimposed (skew) of the electrodes. The item really has three pins and is located in the zone of overlap of electrodes or close to it, cannot be placed between the zones overlap of the electrodes according to the variant shown in figa, i.e. in the form of two separate segments. As a consequence, it will be necessary, at least one separate direct connection to the third electrode. Such orthogonal passive matrix addressing has several disadvantages.

As you can see from the .3b, orthogonal electrode structure requires long parallel tracks (lines). This leads to inductive and/or capacitive crosstalk between the electrodes in each second electrode is shown of the foot. More importantly, the structure of devices based on application of one-piece (solid) extended functional layers located between the sets of electrodes inherent fundamental limitation due to the massive imposition of electrodes 1 and 3 outside the useful zone overlay that includes the element or cell device. More specifically, if each functional layer is conductive in the direction perpendicular to the layers between the electrodes 1 and 3 there is a direct channel for leakage current along the entire length of the electrodes from the zone specified overlap to the edge of the matrix. This limitation is very serious and makes it impossible for a number of important applications, such as a memory device with one bistable storage layer (between the electrodes 1 and 2) and one Manager, or switching layer (between the electrodes 2 and 3).

Moreover, there is the problem of over-saturation auxiliary electronics and connections at the edges of addressable matrix. The complexity of this problem increases rapidly with the increasing number of conclusions to address each elem is NTA. As shown in fig.3b, this problem can be slightly mitigated by placing control electronics for sets of electrodes 1 and 3 on opposite sides of the matrix. This strategy allows you to receive no more than four separately controlled sets of electrodes, which corresponds to the four-foot, instead of three-layer of the foot, shown in fig.3b. However, as already mentioned, in many cases it may be desirable to have a foot with a large number of layers.

It may also be desirable that all the electronics were located on the common substrate, for example, on a silicon wafer. This means that the multilayer orthogonal matrix of the type shown in fig.3b will require electrode connections high density, having a greater length in order to achieve other, unused parts of the substrate. In most cases, this solution is undesirable. Alternative control electronic modules belonging to different sets of electrodes may be in the form of the foot, one above the other. This entails a number of undesirable consequences, for example, the necessity of application of semiconductor technology another type (thin-film transistors and other), as well as difficulties associated with cross-interference, the need for temperature control and technological nesom the value when receiving the feet of active contours.

Figure 4 illustrates the basic principles of implementation means of the present invention, intended, in particular, for addressing matrix. The matrix includes a device, or a cell with three pins placed in a planar configuration. Electrode means comprising three planar set of electrode lines (also called tape electrodes or electrodes just) aibjand ckshown in projection onto a single plane. Electrode lines within each set are parallel to each other. Each set of electrode lines deployed at a certain angle relative to the other two sets. While the electrodes of one set are imposed on the electrodes of the other two sets (i.e. crossed with them) in the common areas (called also for ease of understanding points) overlay, which are addressable device. Although mutually deployed sets of electrodes are shown lying in the same plane, at the point of overlap they are physically separated and typically lie in separate planes. However, the data plane may lie in close proximity to each other, being separated by a thin profiled film or solid (one-piece) thin film, which forms the bulk of the matrix element (not depicted in figure 4). In this example, devices or options the regional elements, located in the dot matrix corresponding to the overlapping electrodes, have access to N=3 independent connections (lines), leading to the edges of the matrix, where the electrodes can be connected to the control or monitoring circuits.

Various electrodes can be mutually deployed in such a way as to form a symmetrical configuration without overlap even for large N. for Example, the angles between adjacent planes (or layers or sets) may correspond to 360°/mN, where N is the number of pins, a m is an integer less than or equal to N. Since in this scheme, no pair of adjacent electrode sets is not conformal overlapping, capacitive coupling will be largely absent.

An important aspect of the present invention, which is distinctive in relation to the prior art, becomes clear when comparing figure 4 with figure 3. As already explained previously, the configuration in figure 3 cannot be used to refer to devices made using solid functional layers that are conductive in the direction perpendicular to the layers. This impossibility is due to the considerable mutual overlapping of the electrodes included in sets 1 and 3. Besides this, the overlap can lead to invalid inductive or capacitive cross is Omaha. In non-orthogonal variant presented in figure 4, the only point area (point) overlap of the three electrodes associated with a particular device, is area (point) their crosses. It is obvious that, although this principle is illustrated for a configuration with N=3, it applies to non-orthogonal matrices with N>3.

Further, comparing the true three-dimensional matrix of known type, shown in figure 2, with matrix addressing of the present invention, is presented in figure 4, one can notice that in the latter case, the element can be completely specified by choosing only two non-parallel lines. Thus, an exclusive (private) addressing element at the point of overlap of the lines aibjand Ckprovided with the help of pairs (aibj), (aick) and (bjck), and triples (aibjck).

Each element of the above matrix associated with the three lines that can be electrically activated independently of one another, as pairs, or three. It should be noted that the permissible combinations of i, j, k obey the following rule selection:

i+j+k=2n+1, where n=imax=jmax=kmax.

This selection rule is applicable not only to the electrode configurations that form in the projection of the equilateral triangles of the type shown in figure 4, but to bwamu the occasion of the electrodes, forming triangles, which can have arbitrary shape, but when there are common points of overlap.

Next will be described examples of the implementation of the first version of the addressing matrix in accordance with the invention. All these examples are intended for devices or cells with four pins in the planar configuration.

On figa and 5b shows the distribution of the principle described for the case N=4. Addressable matrix in both cases remains the same, but the scheme external connections fig.5b is more compact than Figo. As you can see, in addition to the points overlay, corresponding to the four findings, there is also overlap only between the two lines oriented at right angles one to the other. Similar to the binary blend in principle correspond to the loss in density of addressing, if the matrix should include only addressable devices or clusters of devices with four conclusions. However, in some cases, it may be desirable to include in one matrix device with two and with four pins with a corresponding increase in the density of their location.

In the examples shown in figa and 5b, the matrix addressing is built in the form of a square with 8×8=64 elements or devices. However, if the number of lines addressing is limited to 8 for each electrode of the set a, b, C and d, the number of devices with four conclusions would be less 64. An embodiment that allows the use of 64 such devices in a square matrix 8×8 presented on figs. Each of the electrode sets b, d includes 8 lines respectively parallel to the rows and columns of the matrix. However, the sets a, C, deployed at 45° relative to the sets b, d, must be at 15 lines in order to provide access to all 64 items. In the General case, the matrix p; q is the number of lines parallel to the diagonal of the matrix is given by the expression p+q-1, and when p=q - expression 2P-1. Therefore, the matrix 8×8 must have 15 lines in a diagonal electrode sets. On fig.5d shows the application of the same principle to the matrix 5×3, in which the electrode sets and must have 5+3-1=7 lines to form a 15-element rectangular matrix with full access on four conclusions to all elements.

By simple extension of the basic principle of mutually deployed sets of parallel electrodes, the addressing can be obtained matrix addressing with N>4.

Next, with reference to figa-6f and 7a-7E are examples of the implementation of respectively the second and third embodiments of the invention. Examples of devices that may be included in the matrix addressing corresponding to the present invention can serve as a touch device, atsakymai, transistor components and circuits with three or four conclusions. The present invention first provides a practical opportunity to build a quasi-two-dimensional networks containing devices such types. These devices include planar device with both passive and active matrix characteristics. As an example of a class of such devices can serve as active matrix displays with cells that are fluorescent (e.g., led, microlaserpeel or discharge) or modulating the reflection/transmission (LEDs, the elements of the MEM). In addition, here, obviously, includes a memory device architecture SRAM, DRAM and FRAM (in particular, SRAM cell with four observations shown in figure 1). As should be obvious to specialists in this area, the possible range of applications is much wider than the above examples, so that the scope of the present invention in any case cannot be limited to these examples.

All are listed on figa-6f and 7a-7E examples correspond to the number of lines in pixels of the overlay average of N=3, i.e. three electrode sets according to the invention. To illustrate the adaptability of the present invention are two distinctly different options. On figa-6f presents device or ball is s with three conclusions connected to the three lines at the point they overlay (matrix address). On figa-7E two or more devices or cells with two terminals form clusters at the point of overlap (matrix address) with various joining three electrodes intersecting at this point.

In the first case, as can be seen from tiga-6f, the device (or cell) And with three pins attached to the three intersecting electrode lines. Figa and 6b correspond to a perspective and schematic picture of such a connection. The device may be a transistor of the type presented in figs, which is typically connected to other components to perform various tasks. Another example is a light-emitting pixel of the display shown in fig.6d, in which the light emitting element is controlled by a transistor is a Transistor And, in turn, is controlled by electrode lines bjthe shutter. Another example is given on file. Here in line bjshutter included chemical or physical sensor S. In the same building at other points in the overlay is a two-dimensional sensor or device imaging. If you are sharing all of the components a, b and C, as shown in fig.6f, is a two-dimensional display in which the spatial distribution of the emitted light is and corresponds to a spatial intensity distribution of the input stimuli, coming to component C.

In the second case, as shown in figa-7th, to a certain matrix address, i.e. to the point of overlap of the electrode lines (aibjck) in the matrix is connected to the three components (or devices) a, b and C with two terminals each. The components can be activated independently from each other, i.e. addressing the same area of the overlap can be carried out by activating any pair of electrodes (aibj), (aick) or (bjckas it is seen from a perspective and schematic images on figa, 7b.

On figs presents the scheme for the case of two components (or devices) and with two conclusions, both of which are located in one of the matrix address (ie. in this case, the dot overlap of the three electrodes). A particular variant of this scheme, suitable for use in a passive matrix memory type WORM (write once, read once, read many) or REWRITABLE (multiple entry), shown in fig.7d. Here a and b are the rectifier diode and the memory cell, respectively. Diode And provides suppression of parasitic current loops in the circuit of the passive matrix addressing, and the cell can be provided in a given logic state, then it is logical condition will be defined is but read operations.

In relation to one of the classes WORM memory is a jumper that during a write operation changes its resistance with moderate or low to high or infinite. In principle, this operation can be done in the scheme of two-dimensional passive matrix fig.7d and without the aid of the middle electrode bj. However, in this case, during a write operation through the diode should be a strong current. This imposes a limitation on the design and characteristics of the diode, which in General leads to a reduction in the overall efficiency of the device. The presence of the third electrode bjshown in fig.7d, provides direct access to the isolated memory cell during the recording, and it can be disabled during the read. Thus, there is a possibility to optimize the components a and b independently from each other. There are important cases when the presence of the third electrode, thereby providing access to the memory cell of the type shown in fig.7d, is critical. For example, the protocols of the read/write/erase for some types of memory with multiple entry provide the application to the memory cell voltages, which have different polarity and the level of which may vary within wide limits. This condition may be performed in the passive matrix addressing by fig.7d, but obviously newip is limo deleting output, associated with line bj.

On five presents three-piece (full color) pixel in the display, running on the emission, reflection or light transmission. For each item a, b and C can be served with different voltage VAVBand VCrespectively. It should be noted that stresses applied to all three electrodes simultaneously, you must be running the following condition:

VA+VB=Vc.

This does not preclude individual management elements a, b and C, which can be implemented by using multiplexing. However, in this case, means that the duty cycle of the electrical stimulation of each element may not in General be 100%.

Next will be examined in more detail a preferred variant of the invention with reference to figa, 8b, which shows a practical implementation of a system of passive matrix addressing for N=3, based on the placement of continuous layers of functional materials between the three sets of electrodes. In particular, figa depicts a single cell located in the zone of overlap of the electrodes a, b, C, functional materials M1, M2 which are located between the two pairs of electrodes a, b; b, C, respectively. On fig.8b presents the resulting matrix in which cells with functional materials M1, M2 formed is in the form of bulk items, asked by dots overlay crossed ribbon electrodes. In many preferred examples of the materials of the layers are non-crystalline materials, which can be caused by one of several different methods, for example, centrifugation, evaporation, using a doctor knife, etc. Sequence of operations in the manufacture of the following.

1. On a substrate is applied to the first electrode layer.

2. On top of the first electrode is applied, the material M1.

3. On top of the material M1 is applied to the second electrode layer.

4. On top of the second electrode is applied to the material M2.

5. On top of the material M2 put the third electrode layer.

Layers of materials should not have a too high electrical conductivity in the transverse direction (perpendicular to the film thickness, to prevent excessive crosstalk between the electrodes in the matrix. In those applications in which layers of material has a kind of finite conductivity, crosstalk are minimized through the use of layers that are very thin or have blank areas between the electrode lines. An alternative can be formed layers with anisotropic conductivity, which suppressed the currents in the transverse direction.

Parasitic currents represent the problem is, well-known with regard to well-known schemes for passive matrix addressing with two orthogonal sets of electrodes. This problem, together with measures for its overcoming, to some extent discussed in the three above-mentioned international applications owned by the applicant of the present invention. Data parasitic currents due to unwanted current channels within the grid electrode addressing, including the overlap between the electrodes in some non-addressable points overlay. In a typical case, these currents are suppressed by using an element with a nonlinear impedance, for example, a rectifier diode, at each point of overlap. The same measure can be provided in the device of the present invention. This is illustrated by figure 9, which depicts a device with three pins in a triangular matrix, where each device includes a rectifier diode.

The physical structure presented on figa is useful when creating a device class, which is illustrated figs (and includes options for fig.7d, 7e). In the memory devices of the type shown in fig.7d diode is formed spontaneously in contact area between the electrode andiand respectively selected semiconductor (for example, based on conjugated polymers), which forms the material MPI that cell In the memory is formed by using as the material M2, located between crossed electrodes bjand ckcorresponding substances with properties of memory. Similar patterns can be used for building displays. In this case, the materials M1 and M2 have the ability to either emit light when electrical stimulation (that is, for example, light-emitting conjugated polymers), or modify luminous flux by absorption, reflection or polarization (i.e. are liquid crystals). Naturally, in the case of a display with a volume element or elements, when the functional environment is fully enclosed between the electrodes, the electrode or electrodes, at least, situated (located) on one side of the volume element or elements must be transparent (translucent). The exception to this rule may be one electrode located on the opposite side of this multilayer structure.

It should also be noted that the materials M1 and M2 (see figa), which together comprise the volume element in contact with the electrodes a, b and C, can be formed as a solid layer, which are located throughout the matrix. In this area, which is a selective interaction with three-dimensional element is, of course, be placed between the electrodes, at the point (area) of their application, which is hereby ass is t the location of the cell in the specified volume element. However, to build more complex circuits of the type used in the embodiments according fig.6f, 7b or 7E, more efficient can be discrete volume elements of a given configuration of the type shown in figa. In such cases, at least part of the volume element must be separated from other parts located between the pairs of electrodes, and to be in the space between the top and the bottom electrodes in the immediate vicinity of the area of their application. In other words, the possibility of addressing a volumetric element in the zone of overlap of the electrodes does not mean that a single cell on the basis of volume element cannot be activated in areas outside the overlay of all three electrodes. You can represent discrete surround the element-forming cell in the form of a vertical transistor structure in which the electrodes of the source and drain respectively formed by the electrodes a and C, shown in figa, while electrode b forms a control electrode (gate electrode). In this case, the materials M1 and M2 must have the properties of insulators, while the semiconductor material (not shown)forming a transistor channel, will be from electrode a to electrode C. Thus, the means according to the invention can be used to implement the Mat is CI, containing the vertical structure of field-effect transistors of the type described in international application PCT/N0 99/0013 belonging to the applicant of the present invention.

In the case where the device embodying the present invention, attached to a structure similar to the structure described in the aforementioned international application PCT/N0 98/00212 at least part of the component in the form of a volume element will be opened in the surrounding area. In this case, there is no need to use at least one set of transparent electrodes, which makes the device with the two-dimensional matrix of this type is very suitable for use in cameras or displays, as already mentioned.

When the device architecture similar to that described in the above mentioned international applications owned by the applicant of the present invention should only be used as a device for the processing and storage of data, such devices can be made in the form of a multilayer foot with the formation of a volumetric element, as presented in this description. A two-dimensional matrix containing functional environment, forming a one-piece extended (continuous) volume element of the matrix or discrete elements in each two-dimensional matrix, can then be superimposed on one another with formation of a three-dimensional device really is obreteniyu with the appropriate number of electrode sets. The number of such sets assigned to each two-dimensional matrix in the three-dimensional foot of such matrices may be three or more. In that case, if the structure of the described type is a data storage device, functional environment in three-dimensional elements can be an appropriate inorganic or organic thin-film material with electronic or electrical properties, giving a volumetric element required functionality. Of course, you may be used and any suitable combination of such materials, including materials capable of forming spontaneous diode transitions with adjacent metal electrode, as described in the discussion of the prior art.

Functional environment volume element for the purposes of data storage may be based material having the desired characteristics in relation to the impedance and allows to define, identify and read the impedance value when the application of voltages to selected electrodes with the exclusive purpose of addressing any volume element or cell on the basis of this material. Functional environment volume elements can also be formed of polarizing material, such as electret or ferroelectric material having, for example, view reorganizes the th or organic thin film. In the latter case is the most appropriate copolymer type copolymer polyvinylidenedifluoride with triptorelin (PVDF-Trfe). Materials of this type are useful for storing data in addressable passive matrices. However, in this case, the write and read with respect to a specific cell or a volume element using the selected numeric and bit lines (Shin) may require grounding the other, not selected numeric and bit buses or feed them the appropriate offset. In this case, the device with two terminals for each cell embodying the principles of the present invention, are clearly preferred.

Similar considerations apply also to the active storage devices (storage devices), in which each memory cell contains at least one or more transistors and at least one ferroelectric capacitor. In this case, the volume element or memory cell such devices can be constructed in the form of a device with three or more conclusions, embodying the principles of the present invention.

1. Means to enable addressing of a device containing one or more volume elements constituting the memory cell, the cell displays, diodes, transistors and/or switch/mod the regulatory elements and forming together with the specified tool is part of a two-dimensional or three-dimensional matrix composed of the specified device moreover, the volume element contains three or more pins and one or more cells having (have) depending on the electronic or electrical properties of the material of the cell functionality, data storage, data processing or signal processing, and the tool provides the ability to address specific areas in a three-dimensional element by establishing a selective electrical connection with the specified volume element or cell in the case where the volume element contains more than one cell, whereas the choice of a particular volume element or cell is done by creating not necessarily simultaneous electrical connections with three or more electrodes, generated by the specified means and in contact with the specified volume element for the implementation of selective interaction with him on the plot of the specified element is in close proximity to said electrodes, so that the specified area defines a cell in a specified volume element with which it interacts, wherein the tool includes at least three sets of conductive lines or tape the electrodes to the location specified tape electrodes in each set are mutually in parallel according to the corresponding two-dimensional planar layer, forming an additional part of said matrix, at a mutually parallel arrangement of layers in which are located the tape electrodes, and a set of strip electrodes in one of said layers is oriented at an angle to the projection of strip electrodes of adjacent layers on the layer with the result of mutually orthogonal arrangement of the sets of strip electrodes of adjacent layers, the electrodes in contact with the specified section of a volumetric element, formed by mutual spatial overlap of three or more of these strip electrodes in said respective sets of electrodes in contact with the specified volume element, so that the specified cell or cells of a specified volume element is (are) between the area of mutual spatial overlap of these three or more belt electrode, whereas the selective addressing of the cell is performed by applying current or voltage to the selected tape electrode in each set of electrodes simultaneously or in a timed sequence determined in advance given addressing Protocol.

2. The tool according to claim 1, characterized in that, essentially parallel to the tape electrodes in the set of electrodes are equidistant.

3. The tool according to claim 1, distinguishing the I, the set of electrodes in the matrix is deployed at a given angle or at different preset angles around an axis essentially perpendicular to the matrix, relative to the adjacent electrode sets to prevent conformal imposition of strip electrodes in said adjacent electrode sets.

4. The tool according to claim 3, characterized in that all the sets of electrodes in the matrix are mutually deployed at a given angle or at different preset angles around an axis essentially perpendicular to the matrix, to prevent the conformal imposition of strip electrodes in any of the electrode sets.

5. The tool according to claim 4, characterized in that the angle spread of the set of electrodes relative to the next adjacent set of electrodes is chosen equal to 2π/m·N, where N is the number of electrodes in contact with the conclusion in the cell, and m is an integer with m≤N.

6. The tool according to claim 1, characterized in that it contains three sets of electrodes for providing electrical connections to the cells, with up to three conclusions.

7. The tool according to claim 1, characterized in that it contains four sets of electrodes for providing electrical connections with cells that have up to four conclusions.

8. The tool according to claim 1, characterized in that it contains three sets of electrodes to provide electrical connection for less than the least with two cells, with up to two conclusions each.

9. The tool according to claim 1, characterized in that the number of strip electrodes, which are included in the set is selected based on the number and geometric configuration of the cells in the matrix in such a way as to maximize the number of addressable cells in the matrix.

10. The tool according to claim 9, characterized in that the number of strip electrodes in the respective electrode set is selected so as to allow addressing of individual cells in the matrix.

11. The tool according to claim 1, characterized in that the electrode layers and the layer or layers forming a volumetric element, each cell of which is equipped with at least two conclusions made in the form of a multilayer structure with the possibility of contact interaction between the electrode adjacent to the surface of at least one layer of a volumetric element, and the specified layer, and the overlap between the strip electrodes in each electrode layer defines a cell in a three-dimensional element.

12. The tool according claim 11, characterized in that it further comprises a diode transition between the electrode at the area of the overlap of the electrodes and the cell formed in this zone.

13. The tool according to claim 1, characterized in that at least one electrode in at least two sets of electrodes to nachinaet with the conclusions at least one transistor structure contained (stored) in one or more cells comprising a volumetric element.

14. The means indicated in paragraph 13, wherein the at least one electrode in at least two sets of electrodes electrically connects one with the other through their findings transistor structure of one or more cells comprising a volumetric element, each of which contains more than one transistor structure.

15. Device for storing and/or processing data or receiving and/or processing and/or display signals containing the tool according to claim 1, with the tool in conjunction with one or more volume elements constituting the memory cell, the cell displays, diodes, transistors and/or switching/modulating elements, forms part of a two-dimensional or three-dimensional matrix composed of the specified device and volume element contains three or more pins and one or more cells having (have) depending on the electronic or electrical properties of the material of the cell capacity data storage, processing data or signal processing, the device contains more than one matrix of the type described, characterized in that the matrix is made in the form of the foot, whereby the device forms a three-dimensional structure based on the foot matrices for the injury data, data processing or signal processing depending on the functional properties of each matrix in the foot.

16. The device according to item 15, characterized in that the substrate carrying the integrated circuits connected to the electrodes of the specified funds to ensure the implementation of management functions, control and correction of errors in the cell volume of matrix elements.



 

Same patents:

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The invention relates to computing and can be used in the design of information storage cylindrical magnetic domains

FIELD: electronics.

SUBSTANCE: device for providing possible addressing in device, containing one or more volumetric element, in form of memory cells, display cells, diodes, transistors and/or switching/modulating elements and forming together with said device a portion of two-dimensional or three-dimensional matrix being a component of said device, contains three sets of electric-conductive lines or ribbon electrodes, forming an additional portion of said matrix. Device for storing and/or processing data or receipt and/or processing, and/or displaying of signals contains said means and more than one matrix, while said matrices are made in form of stack, accurately placed on substrate, and device forms a volumetric structure dependently on functional properties of each matrix in a stack.

EFFECT: broader functional capabilities.

2 cl, 23 dwg

FIELD: electronics.

SUBSTANCE: device for providing possible addressing in device, containing one or more volumetric element, in form of memory cells, display cells, diodes, transistors and/or switching/modulating elements and forming together with said device a portion of two-dimensional or three-dimensional matrix being a component of said device, contains three sets of electric-conductive lines or ribbon electrodes, forming an additional portion of said matrix. Device for storing and/or processing data or receipt and/or processing, and/or displaying of signals contains said means and more than one matrix, while said matrices are made in form of stack, accurately placed on substrate, and device forms a volumetric structure dependently on functional properties of each matrix in a stack.

EFFECT: broader functional capabilities.

2 cl, 23 dwg

FIELD: engineering of data storage devices, technology for performing non-destructive reading of data and method for inducing polarization onto pairs of memory sub-cells.

SUBSTANCE: device has a set of memory cells, first and second sets of electrodes, while electrodes of second set are directed orthogonally to electrodes of first set and are made in form of parallel doubled electrodes, positioned in mutually parallel recesses made in electrodes of first set, while in recess between electrodes of first set and parallel doubled electrodes of second set, on both sides of these doubled electrodes, memory cells are formed with sub-cells. Methods describe process of non-destructive reading of data from aforementioned device and possible induction of polarization onto pairs of memory sub-cells.

EFFECT: shorter time needed for accessing data storage device, prevented influence of piezo-electric activation of memory cells of certain memorizing matrix on other memorizing matrices included in composition of packet, improved signal-noise ratio.

3 cl, 23 dwg

FIELD: technological processes.

SUBSTANCE: module of semi-conducting memory and receiving unit of device of record-readout for it are related to structural elements of digital memorising devices and may be used in computer input blocks. Memory module is made with the shutter, which protects contact sites on the basis of frame. Shutter is installed in the bore of frame basis and has two end thrusts that interact with springs in slots of frame walls. Receiving unit of device of record-readout for such module consists of three main elements: frame with thrusts, spring-loaded slider and module holder. Slider has inclined slots on its side walls, with which the holder latches interact, lowering the holder with module on contact group of record-readout device. Position of slider is fixed by its thrust engagement with radial shoulder of lever, which is installed in the frame basis. Slider movement is limited by slots in its basis, which interact with frame basis thrusts. Memory module shutter is opened with end thrusts of holder when pressing the shutter projections, which interact with its springs. Latches-limiters of holder are installed in vertical slots of frame walls and provide only vertical movement of holder, and thrusts in frame basis at interaction with slots in holder guides fix it in lower position.

EFFECT: increase of reliability with simultaneous simplification of devices.

2 cl, 7 dwg

FIELD: technological processes.

SUBSTANCE: module of semi-conducting memory and receiving unit of device of record-readout for it are related to structural elements of digital memorising devices and may be used in computer input blocks. Memory module is made with the shutter, which protects contact sites on the basis of frame. Shutter is installed in the bore of frame basis and has two end thrusts that interact with springs in slots of frame walls. Receiving unit of device of record-readout for such module consists of three main elements: frame with thrusts, spring-loaded slider and module holder. Slider has inclined slots on its side walls, with which the holder latches interact, lowering the holder with module on contact group of record-readout device. Position of slider is fixed by its thrust engagement with radial shoulder of lever, which is installed in the frame basis. Slider movement is limited by slots in its basis, which interact with frame basis thrusts. Memory module shutter is opened with end thrusts of holder when pressing the shutter projections, which interact with its springs. Latches-limiters of holder are installed in vertical slots of frame walls and provide only vertical movement of holder, and thrusts in frame basis at interaction with slots in holder guides fix it in lower position.

EFFECT: increase of reliability with simultaneous simplification of devices.

2 cl, 7 dwg

FIELD: information technology; gambling.

SUBSTANCE: central controller contains control unit, which, in turn, contains processor unit, storage device and software. At that the control unit is programmed to receive first signal, defining the location of gambling device, transmitted by one of the transmitters; to receive second signal, defining the location of gambling device, transmitted by another transmitter; to determine the gambling device location considering the two signals, as well as to determine transmitters' location; to determine bearing angles of the transmitters relative to the receiver considering the two signals received and bearing angle determination angle, and, finally, to determine the gambling device location considering transmitters' bearing angles relative to receiver, as well as transmitters' location. Controller operation is described by versions of methods for determination of gambling device location in a casino.

EFFECT: capability to determine gambling device location in a casino automatically, while retaining standard mode of gambling device operation.

10 cl, 31 dwg

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing parallel computer systems. The technical result is achieved due to that in an s×m rectangular matrix of readings, where: s is the number of rows, m is the number of columns, where s*m equals 2P, m equals 2q, and p and q are integers and q is greater than or equal to 1, and p is greater than q, for all columns of the rectangular matrix of readings in the same row, are placed in columns with cyclic shift relative rectangular arrangement to the right (left) by Sh positions: , where: n=[p-q+1]/q-1; si is the coefficient of the number of rows sn, given in the form sn=snmn+…+s2m2+s1m1+s0m0.

EFFECT: possibility of simultaneous access to fast Fourier transformation readings saved in memory using traditional methods.

FIELD: information technology.

SUBSTANCE: receiving unit forms a housing and a receiving unit, the housing being detachable and the receiving unit having a rigid frame from which is suspended an assembly of an "П"-frame structure and a printed circuit board with a contact device. The rigid frame consists of a base with end supports, side panels and a front panel, all joined together. Under the inlet opening of the front panel there is a button with a spring-loaded pusher, the end plane of which slants and rests on the shelf of the "П"-frame structure depending on the angular position of its top and bottom part. Stability of the "П"-frame structure in the outermost positions (angular and horizontal) provide fixation mechanisms formed by a system of a spring-loaded P-shaped lever, a holder and a tension-compression spring, lying in corresponding grooves of each of the side panels.

EFFECT: improved manufacturability of the structure, which reduces requirements for accuracy of making elements of the structure and assembly thereof.

2 cl, 3 dwg

FIELD: information technology.

SUBSTANCE: bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis which is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.

EFFECT: reducing the area of the semiconductor substrate occupied by an STT-MRAM cell.

23 cl, 10 dwg

FIELD: information technologies.

SUBSTANCE: data storage device, comprising the following components: a memory layout configured for data storage; a substantially flat card comprising the first part, one or more additional parts, and a guide element, which marks a border between the first part and at least one of the specified one or more additional parts, and the specified memory layout; and an electric interface, which is electrically connected with a memory layout and arranged on the first face surface of the first part of the card; at the same time the card is made so that if the first part is arranged along the guide element in respect to at least one of additional parts so that one or more parts are directly under the electric interface, and the first part and one or more additional parts are parallel to each other, then the total thickness of the first part and one or more additional parts is sufficient to enter in contact both with the electric interface of a standard socket for telecommunications and with the body of this socket, when the folded card is inserted into a standard socket for telecommunications.

EFFECT: efficiency of device usage as a result of its ergonomics.

20 cl, 23 dwg

FIELD: information technologies.

SUBSTANCE: storage device comprising many interface ports; multiple drivers of discharge busbars; multiple discharge busbars corresponding to multiple drives of discharge busbars; at least two submatrices. Each of the specified at least two submatrices comprises a copy from multiple discharge busbars of the specified storage device and a part from multiple numerical busbars of the specified storage device; a decoder connected with the specified at least two submatrices and the specified multitude input/output ports. The specified decoder is arranged as capable of controlling the specified multitude of numerical busbars; and multiple multiplexers corresponding to multiple discharge busbars; at the same time each multiplexer functions to connect with its appropriate discharge busbar only one copy from its appropriate discharge busbar on the basis of an address of a storage device cell received in one or more of the specified multitude of interface ports.

EFFECT: reduced consumption of dynamic power.

10 cl, 7 dwg

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