Switching transistor protective circuit

FIELD: integrated circuit protective circuits including those of potential type.

SUBSTANCE: proposed circuit designed for protecting switching transistor that controls electromagnet or valve in control unit of motor-car forced idle run economizer upon occurrence of short circuit through common bus or reduction of load resistance below definite value has ten resistors 2, 3, 5, 9, 23, 26, 27, 32 - 34, seven transistors 1, 4, 10, 13, 22, 28, 30, two electronic switches 19, 29, two current supplies 7, 24, one reference voltage supply 31, one dynamic D flip-flop 1`1, one multiplexer 14, two delay circuits 16, 20, two matching units 18, 21, one regulated voltage supply 25, one power supply 6, thee input buses 12, 15, and 17 for passing initial setting signal, input signal, and clock pulses, respectively, and one output bus 8.

EFFECT: reduced number of leads in protective circuit of integrated type; ability of controlling its on-operation delay time.

1 cl, 1 dwg

 

The invention relates to protection circuits, in particular to the protection circuits of potential type, is designed to protect the switching transistors during a short circuit on a common bus or decrease the load resistance below a certain value and can be used to protect the switching transistors, the control solenoid or valve in the control unit economizer forced idling of the car.

The well-known scheme of powerful protection transistor is similar, which is based comparator is performed on the differential cascade, to one input of which is applied the reference voltage on the second voltage from the current sensor [UK Patent No. 2056808, CL N 03 To 17/08; F 02 D 11/00. Declared 13.08.1980. Published 18.03.1981].

The disadvantage of analogue is the inability to restore his health after removal of the overload, and the presence of the current sensor, to enable you want more output, and three capacitors, which are external elements in the manufacture of circuits in integrated circuits.

Known another protection circuit against short circuit potential type - analog, which is based on two transistors, the second of which contains a Schottky diode between collector and base, which simultaneously form the WMO is Noah signal in the base of the switching transistor and the base of the output transistor, respectively. The first transistor generates a signal in the base of the switching transistor with a delay relative to the input signal at the base of the output transistor to eliminate false positives when starting or at low output voltage during its growth. This delay is performed by a slower release of the first transistor from saturation mode as compared with a transistor containing a Schottky diode [U.S. Patent No. 4291357, CL N 02 N 9/02. Declared 27.12.1979. Published 22.09.1981].

The disadvantage of analogue is the inability to adjust the time delay required for the application of the key transistors with different parameters.

Known protection circuit prototype, containing the first transistor, the emitter of which is connected to the shared bus, and the manifold via a second resistor connected to the base of the second transistor and the third resistor, the second terminal of which is connected to a power source and to the emitter of the second transistor, the collector of which forms the output bus, the first resistor, a first output which is connected to the base of the first transistor and also connected to the first output of the seventh resistor, the second terminal of which is connected to a shared bus, and connected in series through the eighth and ninth resistors to the collector of the second transistor and an output bus, and vtoro the conclusion which is the connection point of the fifth resistor, the second output of which is connected to the shared bus, the fourth resistor, the second terminal of which is connected to the base of the fourth transistor and the collector of the third transistor, the emitter of which forms the input bus, and the emitter of the fourth transistor, the collector of which is connected simultaneously to the base of the third transistor, the first capacitor, the second terminal of which is connected to a shared bus, and the sixth resistor, the second terminal of which is connected to the positive output of the reference voltage, the negative output of which is connected to a common bus, a second capacitor that is connected between the connection point of the eighth and ninth resistors and a common bus. In this device a signal for actuation is the potential of the collector of the second transistor. In case of short circuit on a common bus this key transistor is in active mode during the charging of the first capacitor [Chirkov P., Akimov SV Electrical equipment hire. - M.: driving, 1999. -384 S. (s.219, RIS and s, ri)].

The disadvantage of the prototype is the presence of two capacitors, which in its manufacture in integrated circuits can be made only in the form of external elements, and will take an additional two conclusions. The total number of findings will be three.

The technical result is to reduce the Chi is La conclusions of the protection circuit during its production in the integrated design, and the ability to adjust the time-delay protection circuit. The total number of findings will be two.

The invention consists in that the device containing the first transistor, the emitter of which is connected to the shared bus, and the manifold via a second resistor connected to the base of the second transistor and the third resistor, the second terminal of which is connected to a power source and to the emitter of the second transistor, the collector of which forms the output bus, the first resistor, a first output which is connected to the base of the first transistor, introduced dynamic D-flip-flop, the input R which is connected to the first input bus, and the inverted outputconnected to the input S of the multiplexer, the first input D1 which is connected to the second input bus, a second input D2 is connected through a first delay element to the third input bus and the input dynamic D-flip-flop, a direct output Q connected to the input of the first block matching, and the inverted outputthrough the second delay element connected to the input of the second block matching, the first current source, the positive terminal of which is connected to a source of stabilized voltage and the negative output is connected to the first output of the first electronic switch controlled output which is connected to the output of the first block matching, and the second output via the fourth resistor is connected to the shared bus and is the connection point of the fifth resistor, the second terminal of which is connected to the second output of the first resistor and to the collector of the sixth transistor, and the sixth resistor, the second terminal of which is connected simultaneously to the output of the second block matching and the base of the third transistor, the emitter of which is connected to the common bus and the collector - managed output of the second electronic switch, the first output of which is connected to the negative output of the second current source, the positive terminal of which is connected to the power source and the second output is the connection point of the emitters of the fourth and fifth transistors, the source of the reference voltage, the negative output of which is connected to a shared bus, and the positive output is connected to the base of the fourth transistor, the collector of which is connected to the shared bus, the seventh transistor, the emitter of which is connected to the shared bus, the collector is connected to the input ofdynamic D-flip-flop, and a base connected to the ninth resistor, the second terminal which is a connection point of the seventh resistor, the second terminal of which is connected to the shared bus, the eighth resistor, the second terminal of which is connected to the base of the sixth transistor, the emitter of which is connected to the shared bus, and is of ollector of the fifth transistor, the base through the tenth resistor connected to an output bus.

The drawing shows a circuit diagram of the proposed protection circuit of the switching transistors. The device comprises a first transistor 1, the base of which is connected to the first output of the first resistor 2, the emitter of which is connected to the shared bus, and the manifold via a second resistor 3 is connected to the base of the second transistor 4 and to the third resistor 5. The second terminal of the third resistor 5 is connected to the power source 6 to the positive terminal of the second current source 7 and to the emitter of the second transistor 4. The collector of the second transistor 4 forms the output bus 8 and through the tenth resistor 9 is connected to the base of the fifth transistor 10. The input R of the dynamic D-flip-flop 11 is connected to the first input bus 12, the entranceconnected to the collector of the seventh transistor 13, and the inverted outputconnected to the input S of the multiplexer 14. The first input D1 of the multiplexer 14 is connected to the second input bus 15, the second input D2 is connected through a first delay element 16 to the third input bus 17 and to the input of the dynamic D-flip-flop 11. The direct output Q of the multiplexer 14 through the first block matching 18 is connected to a managed output of the first electronic key 19, and the inverted outputthrough the second element Z. the support 20 and the second block matching 21 is connected to the base of the third transistor 22 and to the first output of the sixth resistor 23. The positive output of the first current source 24 is connected to a source of stabilized voltage 25 and the negative output is connected to the first output of the first electronic key 19. The second output of the first electronic switch 19 is connected with the second output of the sixth resistor 23, via the fourth resistor 26 is connected with a common bus and via the fifth resistor 27 is connected with the second output of the first resistor 2 and the collector of the sixth transistor 28. The emitter of the third transistor 22 is connected to the common bus and the collector is connected with the controlled output of the second electronic switch 29. The first output of the second electronic switch 29 is connected with the negative output of the second current source 7, and a second output connected to the emitter of the fourth transistor 30 and the emitter of the fifth transistor 10. The base of the fourth transistor 30 is connected to the positive output of the reference-voltage source 31, the negative output of which is connected to a shared bus, and its collector connected to the shared bus. The collector of the fifth transistor 10 through the seventh resistor 32 is connected to the common bus through the ninth resistor 33 is connected to the base of the seventh transistor 13 and through the eighth resistor 34 is connected to the base of the sixth transistor 28. The emitters of the sixth transistor 28 and the seventh transistor 13 is connected to the shared bus.

The protection circuit operates as follows. The basis of the protection circuit with the hat differential cascade in the p-n-p transistors 30 and 10, operating as a voltage comparator, the current through which is set by the current source 7. On the base of the transistor 30 by the reference-voltage source 31 is set to the reference voltage. This voltage sets voltage collector-emitter voltage VCEtransistor 4, above which should trigger the protection circuit.

Output protection circuits are collectors of transistors 28 and 13. Dynamic D-flip-flop 11 analyzes the signal at the output protection circuit and controls the multiplexer 14. The multiplexer 14 at a high logic level at the input of the choice of S skips to the direct output Q signal from the input bus 15, which receives an input signal, and at a low logic level through the delay element 16 transmits to the direct output Q of the clock pulses from the input bus 17. Input R dynamic D-flip-flop 11 to the input bus 12 signal initial setup, representing a high logic level since the power supply within a few microseconds and a logic low during the rest time before removing power from the circuit. If the direct output Q of the multiplexer 14 high logical level, the output of block matching 18 low potential. At the inverse outputmultiplexer 14 is a logic low and the output of block matching 21 high potential.

Light source is to the current 24 is controlled by the electronic key 19 from block matching 18. Part of the current from current source 24 flows through the resistor 26, the part through the resistors 27 and 2 flows into the base of transistor 1 and opens it. This opens the transistor 4 and the collector current of the transistor 1 IC is limited by the resistor 3. The collector current of the transistor 4 is determined by the load resistance connected to the output bus 8. The remainder of the current from current source 24 through resistor 23 to flow into the base of transistor 22 and thus provides performance protection circuit.

In case of short circuit collector of the transistor 4 on a common bus or decrease the resistance of the load is below the maximum permissible value, the transistor 4, if he was in saturation mode, goes into active mode. Voltage collector-emitter voltage VCEtransistor 4 increases, and the potential on the base of transistor 10 decreases. When the potential on the base of the transistor 10 becomes less than the potential on the base of the transistor 30, the transistor 10 will open the transistors 28 and 13. The current of the current source 24, which flowed into the base of transistor 1 begins to flow through transistor 28. The transistor 1 is closed, which leads to the closure of the transistor 4, protecting it from thermal destruction of the excessively large current. After you open the transistor 13, an inverse inputdynamic D-flip-flop 11 receives a low logic ur the level. With the advent of the slice clock pulse at the input dynamic D-flip-flop 11 at its inverted outputand , consequently, on the selection input S of multiplexer 14 is set to a logic low. Through the delay element 16 at the direct output Q of the multiplexer 14 is cut clock pulse from the input bus 17, which causes the transistor 4 and the protection circuit is de-energized.

With the arrival of the front of the next clock pulse from the input bus 17 to direct the output Q of the multiplexer 14 is set to a high logic level, and the transistors 1 and 4 are opened. Through delay element 20 opens the transistor 22 and includes a protection circuit.

If after switching circuit protection short circuit collector of the transistor 4 or the load resistance is below the maximum permissible value is stored, then again triggered the protection circuit according to the above-described algorithm.

If after switching circuit protection short circuit collector of transistor 4 and no load resistance is not below the maximum permissible value, the transistor 4 manages to enter into the saturation mode. The transistors 10, 28 and 13 are closed. With the advent of the slice clock pulse at the input S of the multiplexer 14 is set to a low logic level on its direct output Q passes the input signal from the input bus 15.

In affect, the, the proposed device provides protection transistor 4 from a short circuit in the load or reduce the resistance of the load, allows you to adjust the time delay protection circuit by changing the number of inverters in the delay element 20, and when used in integrated circuits to reduce the number of conclusions.

The protection circuit of the switching transistors, containing the first transistor, the emitter of which is connected to the shared bus, and the manifold via a second resistor connected to the base of the second transistor and the third resistor, the second terminal of which is connected to a power source and to the emitter of the second transistor, the collector of which forms the output bus, the first resistor, a first output which is connected to the base of the first transistor, characterized in that it introduced dynamic D-flip-flop, the input R which is connected to the first input bus, and the inverted outputconnected to the input S of the multiplexer, the first input D1 which is connected to the second input bus, a second input D2 is connected through a first delay element to the third input bus and the input dynamic D-flip-flop, a direct output Q connected to the input of the first block matching, and the inverted outputthrough the second delay element connected to the input of the second block matching,the first current source, the positive output of which is connected to a source of stabilized voltage and the negative output is connected to the first output of the first electronic switch controlled output which is connected to the output of the first block matching, and the second output via the fourth resistor is connected to the shared bus and is the connection point of the fifth resistor, the second terminal of which is connected to the second output of the first resistor and to the collector of the sixth transistor, and the sixth resistor, the second terminal of which is connected simultaneously to the output of the second block matching and the base of the third transistor, the emitter of which is connected to the common bus and the collector with a controlled output of the second electronic switch, the first output which is connected with the negative output of the second current source, the positive terminal of which is connected to the power source and the second output is the connection point of the emitters of the fourth and fifth transistors, the source of the reference voltage, the negative output of which is connected to a shared bus, and the positive output is connected to the base of the fourth transistor, the collector of which is connected to the shared bus, the seventh transistor, the emitter of which is connected to the shared bus, the collector is connected to the inputdynamic D-flip-flop, and a base connected to the ninth resistor second terminal which is a connection point of the seventh resistor, the second output of which is connected to the shared bus, the eighth resistor, the second terminal of which is connected to the base of the sixth transistor, the emitter of which is connected to the shared bus, and the collector of the fifth transistor, the base of which through the tenth resistor connected to an output bus.



 

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