The memory cell

 

The invention relates to the field of pulse technique and can be used in computer equipment and control systems. The technical result is to increase the reliability in the storage memory. The device includes a switch, serial N RC-circuits, asynchronous D-trigger, two bi-directional key, three logical element OR NOT, the multiplexer, the pulse counter, two synchronous D flip-flop. 1 Il.

The invention relates to the field of pulse technique and can be used in computer equipment and control systems.

A known memory location (see and. C. the USSR 1706362 from 02.04.90, MKI N 03 To 3/037, "Trigger device", Eryomin A. N., Shishkin, I., publ. 28.08.97, bull. 24), containing D-trigger, the first, second and third elements OR NOT, the element AND-NOT bi-directional key, a resistor and a capacitor. One of the conclusions of the resistor across the capacitor is connected to the shared bus. The first and second inputs of the first element OR NOT connected respectively with the first installation of the input device and the output of the second element OR NOT. The first and second inputs of the second element OR NOT connected respectively with the second installation input devices and direct itororo connected with the first inputs respectively of the first and second elements OR NOT. Output bi-directional key is connected to the information input of D-flip-flop and the other output resistor, the input - output of the first element OR NOT, and control input - output element. The first and second inputs of the element AND IS NOT connected respectively with the output of the third element OR NOT, and with additional input devices.

The disadvantage of this memory cell is the small amount of stored data.

A known memory location (see RF patent 2042268 from 28.06.91, MKI N 03 To 23/64, "the Count of pulses in the code gray", Dikarev I. I. Shishkin, I., publ. 20.08.95, bull. 23) that contains the digits from zero to N-th, serial RC circuit on the number of digits, demultiplexer, two switches, and each discharge - asynchronous D-flip-flop and a multiplexer, which contains two bi-directional key and the element OR NOT, the inputs of which are the address inputs of the multiplexer. Each discharge outputs of the bidirectional keys are connected to the input of the trigger and to the corresponding input of the first switch, the output of which is connected to the output of the second switch, the inputs of which are connected with the first conclusions of the respective RC circuits, the latter findings are connected to a common bus. The input of the demultiplexer is connected to the first input bus, address why items OR IS NOT relevant bits the second input of the element OR NOT each discharge is connected with the control input of the first bi-directional key and an entry permit recording of information, and the output connected with the control input of the second bi-directional key, the input of which is connected to the direct output of the flip-flop. Information on the second input bus is changed when the signal on the first input bus. Input the first bi-directional key information is the input of the discharge cell memory.

The memory cell is closest to the technical nature of the claimed device and is taken as a prototype.

The disadvantage of the prototype is the complexity of the device.

The problem solved by the invention is the creation of a memory cell with a simpler circuit implementation while increasing reliability in the storage memory.

The technical result is achieved in that in the memory cell containing the switch, serial N RC-circuits, the first conclusions which are connected to respective inputs of the switch, and the latter findings - with a shared bus, asynchronous D-trigger, two bi-directional key, the first of which is connected to the input of the second bi-directional key and the input of the asynchronous D flip-flop p is the output of the first logic element OR, which is connected to the output of the first logical element OR NOT. What's new is that inputs of the multiplexer, a pulse counter, two synchronous D flip-flop, two logical element OR NOT, the output of the second logic element OR NOT is the output data of the memory cell and the first input is connected to the inverse output of the asynchronous D flip-flop whose input is connected to the output of the switch control inputs of which are connected to respective outputs of the multiplexer, the first two inputs of which are connected to respective outputs of the pulse counter, and the other two inputs of the multiplexer are the address inputs of the memory cell, the input of the pulse counter connected to the first input of the first logic element OR NOT, WITH inputs of the first and second synchronous D-triggers, direct outputs which are connected respectively with the first and second inputs of the third logic element OR NOT, the output of which is connected with the control input of the multiplexer and gate is the output of the memory cell, the inverted output of the second synchronous D flip-flop is connected to the second input of the second logic element OR NOT, direct the output of the first synchronous D-flip-flops connected to a second input of the first logic element OR NOT and managing the input of the first dunayevskaya D-flip-flops are respectively inputs the read and write.

This set of features allows you to simplify the memory cell while increasing reliability in storage mode by introducing a pulse counter and a multiplexer.

The drawing shows an electrical schematic diagram of the memory cell.

The memory cell contains a logical-OR-NOT 1, asynchronous D-flip-flop 2, bi-directional key 3, the logical element OR NOT 4, bi-directional key 5, the pulse counter 6, the synchronous D-flip 7, 8, a multiplexer 9, the logical element OR NOT 10, switch 11, a serial RC circuit 12-15, data input 16, the address bus 17, and inputs the read and write 18, 19, the gate output 20, the clock input 21 and output. The first conclusions serial RC circuit 12-15 connected to respective terminals of the switch 11, and the second - with a shared bus. Data input 16 is connected to the input of bi-directional key 5, the output of which is connected to the output of the switch 11, the input asynchronous D flip-flop 2 and the output bi-directional key 3, direct asynchronous D flip-flop 2 is connected to the input of bi-directional key 3, a control input connected to the output of the logical element OR NOT 4, the first input connected to the input of the pulse counter 6, With inputs of two synchronous D-tryweryn inputs of the logic element OR NOT 10, respectively, the output of which is connected with the control input of the multiplexer 9 and gate is the output 20 of the memory cell. Inverted outputs asynchronous D flip-flop 2 and the synchronous D-flip-flop 8 is connected respectively with the first and second inputs of the logic element OR NOT 1 whose output is the output of the memory cell, the first input of logic element OR NOT 10 is connected with the second input element OR NOT 4-managing input bi-directional key 5. Informational inputs synchronous D-flip-flops 7, 8 are respectively the input record 18 reading 19 of the memory cell.

As the hardware components of the device selected series 564 implemented on CMOS-tehnologii.

The memory cell operates as follows.

The memory cell has a write mode data read mode and data storage mode in which the dynamic regeneration of data.

In write mode, the data arrives at the input of the bi-directional key 5 via the data input 16, and a signal of logic "1", allowing the record to the input data of the synchronous D-flip-flop 7 through the input record 18. On the front of the clock supplied to the clock input 21 of the memory cell, the output of the synchronous D-flip-flop 7 a signal of logical "1" which is which closes the bi-directional key 3, disallowing entrance D-flip-flop 2 from its direct output. Signal is logical "1" output from the synchronous D-flip-flop 7 is also fed to the control input of the bidirectional key 5, resulting in data from the data input 16 of the memory cell is fed to the input X of the switch 11 (output). This same logic, the outputs of the synchronous D-flip-flop 7 is supplied to the first input of logic element OR NOT 10, the output of which produces a signal of logical "0" which is supplied to the gate output 20 of the memory cell and the control input of the multiplexer 9, the outputs X, Y are connected to the address bus 17, the combination of signals which determines the address discharge of the memory cell in which the write data.

In the reading mode to the input data of the synchronous D-flip-flop 8 through the entrance read 19 receives the signal of logical "1". Edge of the synchronization signal received at the input 21 of the memory cell, to direct the output of the synchronous D-flip-flop 8 is a signal of logical "1" which is supplied to the second input of the logical element OR NOT 10, then set the address of the memory cell from which data is read, similarly to the recording of data. The data comes from the output X commutor of the element OR NOT 1. With the inverted output of the synchronous D-flip-flop 8 to the second input of the logical element OR NOT 1 signal logic "0", then the data arrives at the output of the memory cell.

In storage mode at the inputs of records 18 and read 19 present the logical levels "0", and the input synchronization 21 is supplied clock pulse, which leads to the appearance at the output of the logical element OR NOT level 10 logical "I", which is supplied to the control input of the multiplexer 9. It outputs X and Y are connected to the inputs XI and Y1, respectively, and the pulse counter 6 produces a sequential scan of the address bits of the memory cell. Edge of the synchronization signal on the synchronization input 21 of the memory cell is correspondingly a change of address discharge device and through the logical element OR NOT 4 and bi-directional key 3 is turned off input asynchronous D flip-flop 2 from its direct output. The information stored by the discharge device with the selected address (regenerated category) appears at the output X of the switch 11. Data from direct access asynchronous D flip-flop 2 is fed to the input bi-directional key 3, at the end of the sync pulse at the output of the logical element OR NOT 4 produces a signal of logical "1", resulting in sambranky discharge cell memory.

The frequency of the sync pulses to the trigger input 21 of the memory cell must be such that in the storage state of the discharge cell memory was preserved in the intervals between pulses (capacitors, RC circuits 12-15 must retain their charge).

Made laboratory model of memory cells, tests confirmed the feasibility and practical value of the proposed object.

Claims

The memory cell containing the switch, serial N RC-circuits, the first conclusions which are connected to respective terminals of the switch, and the latter findings - with a shared bus, asynchronous D-trigger, two bi-directional key, the first of which is connected to the input of the second bi-directional key and the input of the asynchronous D flip-flop, a direct output of which is connected to the input of the second bi-directional key, a control input connected to the output of the first logic element OR NOT, characterized in that additionally introduced multiplexer, pulse counter, two synchronous D flip-flop two logical element OR NOT, the output of the second logic element OR NOT is the output data of the memory cell and the first input is connected to the inverse Udinese with the corresponding outputs of the multiplexer, the first two inputs of which are connected to respective outputs of the pulse counter, and the other two inputs of the multiplexer are the address inputs of the memory cell, the input of the pulse counter connected to the first input of the first logic element OR NOT, WITH inputs of the first and second synchronous D-triggers, direct outputs which are connected respectively with the first and second inputs of the third logic element OR NOT, the output of which is connected with the control input of the multiplexer and gate is the output of the memory cell, the inverted output of the second synchronous D flip-flop is connected to the second input of the second logic element OR NOT, direct the output of the first synchronous D-flip-flops connected to a second input of the first logic element OR NOT and managing the input of the first directional key input which is the input data of the memory cell, the information inputs of the first and second synchronous D-flip-flops are respectively inputs the read and write.

 

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4 cl, 8 dwg

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