The memory cell

 

The invention relates to the field of pulse technique and can be used in computer equipment and control systems. The technical result is a large amount of stored information. The device includes a switch, serial N RC-circuits, three input bus, an address bus, a bus read, multiplexer, asynchronous D-flip-flop, a logic element OR NOT, two logical element AND-NOT, a comparator, and a pulse counter. 1 Il.

The invention relates to the field of pulse technique and can be used in computer equipment and control systems.

A known memory location (see and.with. The USSR 1706362 from 02.04.90, MKI N 03 To 3/037, the Trigger device, Eryomin A. N., Shishkin, I., publ. 28.08.97, BI 24), containing D-trigger, the first, second and third elements OR NOT, the element AND-NOT bi-directional key, a resistor and a capacitor. One of the conclusions of the resistor across the capacitor is connected to the shared bus. The first and second inputs of the first element OR NOT connected respectively with the first installation of the input device and the output of the second element OR NOT. The first and second inputs of the second element OR NOT connected respectively with the second installation of the input device and the second input of which is connected with the first inputs respectively of the first and second elements OR NOT. Output bi-directional key is connected to the information input of D-flip-flop and the other output resistor, the input - output of the first element OR NOT, and control input - output element. The first and second inputs of the element AND IS NOT connected respectively with the output of the third element OR NOT, and with additional input devices.

The disadvantage of this memory cell is the small amount of stored data.

A known memory location (see RF patent 2042268 from 28.06.91, MKI N 03 To 23/64 pulse Counter code in gray, Dikarev I. I. Shishkin, I., publ. 20.08.95, BI 23). contains the digits from zero to N-th serial RC circuit on the number of digits, demultiplexer, two switches and each category of asynchronous D-Triger and a multiplexer that contains two bi-directional key and the element OR NOT, the inputs of which are the address inputs of the multiplexer. Each discharge outputs of the bidirectional keys are connected to the input of the trigger and to the corresponding input of the first switch, the output of which is connected to the output of the second switch, the inputs of which are connected with the first conclusions of the respective RC circuits, the latter findings are connected to a common bus.

The input of the demultiplexer is connected to the first input bus, address why items OR IS NOT relevant bits the second input of the element OR NOT each discharge is connected with the control input of the first bi-directional key and an entry permit recording of information, and the output connected with the control input of the second bi-directional key, the input of which is connected to the direct output of the flip-flop. Information on the second input bus is changed when the signal on the first input bus. Input the first bi-directional key information is the input of the discharge cell memory.

The memory cell is the closest to the technical nature of the claimed device and is taken as a prototype.

The disadvantage of the prototype is the complexity of the device.

The problem solved by the invention is the creation of a memory cell, which is simple circuit implementation.

Technical result is achieved in that in the memory cell containing the switch, serial N RC-circuits, the first conclusions which are connected to respective inputs of the switch, and the latter findings - with a shared bus, three input bus, the multiplexer and asynchronous D-flip-flop, an input connected to the output of the multiplexer, and direct the output to the first input of the multiplexer, the second and third inputs of which are connected with pervolenko D-flip-flop connected to the first input of the logical element OR NOT.

What is new is the fact that additionally introduced pulse counter, two logical element AND-NOT and the comparator, the first and second inputs which are connected to the address bus, and the third and fourth inputs and first and second address inputs of the switch and the first and second outputs of the pulse counter, the input of which is connected to the second input bus, the second address multiplexer input coupled to the output of the first logical element AND-NOT, the first input connected to the third input bus and a second input from the output of the comparator and the first input of the second logical element AND-NOT the second input is connected to the bus are read and output to the second input of the logical element OR NOT, the output of which is the output device, the input asynchronous D flip-flop connected to the output of the switch.

This set of features allows you to simplify the circuit implementation.

Schematic diagram of the memory cell shown in the drawing.

The memory cell contains 4 digits (zero through three), three input bus 1, 2, 3, bus reading 4, the address bus 5, output bus 6, a switch 7, a serial RC circuit 8 (8-0...8-3), asynchronous D-flip-flop 9, the multiplexer 10, the pulse counter 11, a comparator 12, a logical element of the odes of the comparator 12 is connected to the address bus 5, and the third and fourth inputs to the first and second address input of the switch 7 and to the first and the second output of the pulse counter 11, the inlet of which is connected to the second input bus 2 and the first address input of the multiplexer 10, the second address input connected to the output of the first logical element AND-NOT 14, the first input of which is connected to the third input bus 3, and the second input to the output of the comparator 12 and to the first input of the second logical element AND-NOT 15, a second input connected to the bus reading 4, and its output connected to the second input of logic element OR NOT 13 whose output is the output device.

The first input of logic element OR NOT 13 connected to the inverse output of the asynchronous D flip-flop 9, and the outlet of which is connected to the first input of the multiplexer 10, the second and third inputs of which are connected to the first input bus 1 and the output to the input of asynchronous D flip-flop 9 and the output of the switch 7, the corresponding input of which is connected to the first findings of a serial RC circuit 8 (8-0...8-3), the latter findings are connected to a common bus 16.

The memory cell operates as follows.

When the power supply voltage on all tires device is the unit not shown), the output X of the switch 7 is connected to its input X0, so a serial RC circuit 8-0 connected to the input of the asynchronous D flip-flop 9. Other serial RC circuit (8-1.. .8-3) is disabled. The output of the logical element AND-NOT 14 is a logic level "1". therefore, the output X of the multiplexer 10 is connected with its input x2, and the entrance and direct access asynchronous D flip-flop 9 is connected.

When applying clock pulses to the second input bus 2 (clock input devices) pulse counter 11, sequentially through his state, alternately connects a serial RC circuit 8 (8-0...8-3) to the input of the asynchronous D flip-flop 9 and the output X of the multiplexer 10, which leads to regeneration of the data stored in the respective bits of the memory cell.

The pulse counter 11 changes its state on the front of the clock pulse and thus interrupts the connection of input and direct output asynchronous D flip-flop 9, since in this point in time, the output X of the multiplexer 10 is connected to input X3. The frequency of the clock pulses should be such that the time between calls of the pulse counter 11 to any discharge devices, capacitors corresponding serial RC circuit 8 (8-0... 8-3) can lose only small the config mode of the device is the storage of data.

Writing data to the bits of the memory cell is as follows. On the bus reading 4 signal with a logical level "0" on the input bus 3 (enable input recording device) signal of logical level "1" on the input bus 1 (data bus) are recorded data and the address bus 5 address discharge devices where you want them to write.

When applying clock pulses to the pulse counter 11 enumerates their status (device regenerates the stored data) and at the moment of equality in his state of the address placed on the address bus 5, the comparator 12 generates at its output a signal of logic "1". who is doing the second input of the logical element AND-NOT 14 and causes its output signal with a logic level "0". This leads to the connection of the data bus 1 (through inputs X0 or X1) to the output X of the multiplexer 10 and, through the output X of the switch 7, to a serial RC circuit 8 (8-0...8-3) selected discharge device. At the transition of the pulse counter 11 in the next state (other than set on the address bus 5) the device continues to carry out the regeneration of the data. This mode of working memory is the storage of data.

Read details the bus 3 - a signal with a logical level "0", the address bus 5 address discharge device where data is to be read. The operation of the pulse counter 11 and the comparator 12 is similar to the write mode, the signal from the output of the comparator 12 produces the output of the logical element AND-NOT 15 signal with a logical level "0". The data of the category of the memory cell with the address set on the address bus 5, received from the output X of the switch 7 to the input of asynchronous D flip-flop 9, and its inverted output to the second input of the logical element OR NOT 13, the first input signal with a logical level "0". In the read data appears at the output of the memory cell.

Made laboratory model of a memory cell made according to the scheme of drawing, tests confirmed the feasibility and practical value of the proposed object. The model was implemented on chip series 564.

Claims

The memory cell containing the switch, serial N RC-circuits, the first conclusions which are connected to respective inputs of the switch, and the latter findings - with a shared bus, three input bus, the multiplexer and asynchronous D-flip-flop, an input connected to the output of the multiplexer, and properly address multiplexer input connected to the second input bus, inverted output asynchronous D flip-flop connected to the first input of the logical element OR NOT, wherein the added pulse counter, two logical element AND-NOT and the comparator, the first and second inputs which are connected to the address bus, and the third and fourth inputs and first and second address inputs of the switch and the first and second outputs of the pulse counter, the input of which is connected to the second input bus, the second address multiplexer input coupled to the output of the first logical element AND-NOT, the first input connected to the third input bus, and the second input with the output of the comparator and the first input of the second logic element AND IS NOT, a second input connected to the bus are read and output to the second input of the logical element OR NOT, the output of which is the output device, the input asynchronous D flip-flop coupled to the output switch.

 

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FIELD: magnetic materials whose axial symmetry is used for imparting magnetic properties to materials.

SUBSTANCE: memory element has nanomagnetic materials whose axial symmetry is chosen to obtain high residual magnetic induction and respective coercive force. This enlarges body of information stored on information media.

EFFECT: enhanced speed of nonvolatile memory integrated circuits for computers of low power requirement.

4 cl, 8 dwg

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