Universal memory element with systems using this element, the method and the device for reading, writing, and programming universal memory element


G11C7/08 - Control thereof
G11C17/14 - in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM

 

The invention relates to programmable memory elements, to a method and device for reading, writing, and programming. The technical result is the ability to use such elements in cryptography. Method of storing and retrieving information in the memory element with phase transitions is to remember information in the memory element, by applying at least one software energy pulse in the material memory, retrieving the information stored in the memory element by filing additional software energy pulses, counts the number of said additional pulses required to switch the memory element in a state with a low resistance. The control device level connectivity between nodes in the mesh network system of the neural network contains a single cell containing material with phase transitions, two electrodes, the output of the control output signals, a common output for control and signal control system neural network. The method of controlling the element in the relationship to change connectivity in a neural network describes the operation of the specified device. 3 S. and 18 C.p. f-crystals, 16 ill.

The technical field of the invention This invention relates in General to programmable memory elements and, in particular, to erase the memory elements, which are embodied in such applications as data storage, multi-valued logic and computation in neural networks/artificial intelligence systems, and to methods and apparatus for reading, writing, and programming of such elements. The memory elements are programmed by the supply of energy to any one or multiple of the following types: for example, electrical, optical, energy, pressure and/or heat. In one embodiment of the invention, the information can be saved in memory in encrypted form, i.e. it can only be removed through the use of specially programmed devices and special ways. Thus, this invention can be used to store information in an encrypted or secret format. In another embodiment, the invention finds its embodiment in the system of the neural network.

The level of technology the Basic concept of using materials with phase transitions, in which there is a possibility of Ortego state mainly in the crystalline state and back), for electronic memory is well known to specialists in this field of technology, which are disclosed, for example, in U.S. patent 3271591 issued Ushinskogo September 6, 1966, and U.S. patent 3530441 issued Ushinskogo (Ovshinsky) September 22, 1970, the rights to which are owned by the assignee of the present invention and the contents of which are incorporated here by reference (hereinafter "patent Ushinskogo").

As disclosed in the patents Ushinskogo, structural condition of materials with phase transitions may change, moving from mainly amphora state of local order in generally crystalline local order and back, or can be installed in one of the excellent from each other detectable States of local order across the entire spectrum between completely amorphous and completely crystalline States. First the materials described in the patents Ushinskogo could be in one of two detectable structural States: generally amorphous and generally crystalline local order, and change from one to another, facilitating the storage and retrieval unit-bit encoded binary data, or these materials may be installed intermediate detectable UB i.e. patents Ushinskogo says, the electrical switching between completely amorphous and completely crystalline States for these materials is not required, but that in the whole range of local order between completely amorphous and completely crystalline States can be at any level with a specific detectable characteristic, for example the resistance. This characteristic changing local procedure provides a "gray scale" represented by the spectrum between completely amorphous and completely crystalline States. The specified gray scale can be used as virtually unlimited (infinite) variable parameter, for example a virtually unlimited variable resistance varying from maximum to minimum levels, or can be used to set the values of the increments selected parameter, for example resistance to individual discover the steps between the maximum and minimum levels.

The ability of a variable parameter, such as resistance, adjustable throughout the range of the gray scale, allows the use of these devices, for example, in neural networks and artificial intelligence systems, as described in U.S. Pat the memory element for the installation of speed stackable and selectively detectable levels parameter can provide memorizing in one memory element of multi-bit data.

Summary of the invention the Present invention relates to a newly opened and completely unexpected properties of these materials with phase transitions and devices, allowing you to create a universal memory elements, using the specified properties, and to methods and devices for programming of such memory elements, and to systems storing data, multi-valued logic and neural networks/artificial intelligence, where most of these devices with a universal memory elements.

In one embodiment of the invention these universal memory elements are used in the form and format in which information is stored by filing one or more successive electric pulses of selected amplitude and duration in the memory elements, which is initially set to a state with a high resistance. The amplitude and duration of each pulse are selected so that the flow of one of the initial pulse is not able to cause switching of the memory element from a state with high resistance state to low resistance. However, the amplitude and the duration of each pulse are selected so that each pulse is uniquely structured pulses are defined here as "pointervalue pulses, and when they are served in a specific sequence for recording and/or reading, they are called "programming pulses". Although the characteristics of these potentially pulses more detail in the following detailed description, the following is a brief explanation of the essence of the present invention.

What is disclosed in this invention and that really should be paid special attention in connection with the universal memory elements Ushinskogo, is the fact that the installation of the current pulse to set the memory element from a state with high resistance state to low resistance can be divided into pointervalue pulses, and every time pointervalue pulse resistance memory device is not actually modified until then, until the total accumulated duration potentially pulses becomes equal to or exceeds the "installation length". As soon as the last potentially pulse received last increment of energy, the device enters a state with a low resistance.

Thus, "installation length" installation of the current pulse can be divided into the required number of programmirovanie element. (In one embodiment of the invention the total number of States of the programming more than the number of pointervalue). Once filed a specified number potentially current pulses, read the current state of the memory element by filing additional potentially programming pulses until the memory element will not be switched from the high resistance state to low resistance. The number of additional pulses can be determined and compared with the number of all States programming by reading the resistance element between each of the additionally supplied potentially pulses. The difference represents the current state of the memory element. Pointervalue pulses are defined here as "programming pulses. In each case potentially pulses or programming pulse is not enough to change the material with phase transitions, but rather in combination with accumulated additional pointervalue or programming pulses to force the material from phase transitions to switch from a state with high resistance state to low resistance.

who here is "reading with destruction." So after reading the memory element, it must be "reprogrammed". This is accomplished by first mounting the device in its original state with high resistance using a current pulse of high amplitude, defined here as "current reset pulse, and then supply a number of potentially current pulses required to return the item in the current state that occurred before the read operation. Thus, the information that has been read from the memory element is restored when reprogramming the given element.

In one embodiment of the invention a universal memory element of the present invention is embodied in a system for storing data, where each individual memory element is memorized many bits. This dramatically increases the density of storing in memory, as each universal memory element may be remembered many bits. In this embodiment, data is also stored in non-detectable, and such data cannot be read or removed, except by the use of methods and devices according to the invention that is disclosed in the following detailed description. Thus, this option is how to use the devices and methods according to the present invention.

In another embodiment of the invention a universal memory element according to the present invention is implemented in the system of the neural network and/or artificial intelligence, where the memory element generates and adjusts the function of the connectivity between nodes or between rows and columns of the neural processor. In the specified second variant of realization, when the memory element is connected between nodes or between the columns and rows of the neural processor receives a selected number potentially pulses with the selected assigned weights, and the chosen number and the distribution of weights potentially pulses is determined, for example, the strategy of programming and management of the neural network, the memory element moves to a state with low resistance to ensure maximum connectivity between the selected nodes or between rows and columns of the neural processor. This option also considers in more detail in the following detailed description of the invention.

In particular, according to the present invention, a method of storing and retrieving information in the memory element with phase transitions containing material memory with phase transitions, keuleneer, moreover, the material with phase transitions is made with possibility of installation of a state with high resistance state to low resistance with the installation of the energy pulse, and the method includes the following stages, in which the information is remembered in the memory element by feeding at least one software energy pulse in the material memory with phase transitions, and at least one software pulse of energy sufficient to install memory material from a state with high resistance to find excellent condition with low resistance, but enough to change memory material, so the accumulation of at least one software energy pulse with at least one additional program energy pulse sets the memory material from a state with high resistance to find excellent condition with low resistance, and retrieve information stored in the memory element, by filing in the memory element additional software energy pulses as long as the memory element will not be forced to switch to find the balance of the x pulses, filed in order to cause switching of the memory element in a state with a low resistance.

In addition, according to the present invention, a method is proposed for the control element of the relationship to change connections in the neural network, and element relationship contains a single cell, which includes a material with phase transitions, having at least a state with high resistance state to low resistance, while the material with phase transitions is made with possibility of installation of a state with high resistance state to low resistance through the installation of energy and momentum from a state with low resistance state with a high resistance with energy reset pulse, and the method includes the following steps, in which: serves energy reset pulse to the unit cell for the installation of material from phase transitions to the initial state with a high resistance, and served in the unit cell software energy pulses with the selected weights and durations based on the management strategy of the neural network, and at least several software energy instanee with low resistance, but enough to change the material with phase transitions, so that the accumulation of at least several program energy pulses with at least one or more additional program energy pulses sets material with phase transitions from a state with high resistance, which form the first level of connectivity in the state with a low resistance, forming the second level of connectivity that is different from the first level to a state with high resistance.

In addition to these methods, according to the present invention, the proposed device controls the level of connectivity between nodes in the mesh network system, neural network, comprising: a unit cell containing material with phase transitions, having at least a state with high resistance state to low resistance, and the material with phase transitions is made with possibility of installation of a state with high resistance state to low resistance through the installation of energy and momentum from a state with low resistance state with a high resistance with energy reset pulse, the first and is ergie in material with phase transitions with the aim of switching material with phase transitions from the high resistance state to low resistance and back, and (2) to set the channel holding signal through the material with phase transitions, when the material with phase transitions is in a state of low resistance,
the output control and output signals, which are both electrically connected with the first electrode,
total output for the control signal and connected to a second electrode,
moreover, the output signal is electrically connected to the first node in the mesh network, and the total output of the control signal and electrically connected with the second node of the mesh network to control the level of connectivity between the first and second nodes,
control system, neural network, electrically connected to the output management and General output control signal and for supplying particulate control pulses in the material from phase transitions to force the material from phase transitions to switch from a state with high resistance state to low resistance and thereby increase the level of connectivity between the first and second nodes when the cumulative effect of the control pulses will exceed the level of the threshold switching material with phase transitions.

These and various other variations and applications of the present invention, and is bretania.

Brief description of drawings:
Fig. 1 is a graphical representation of the universal memory element according to the present invention, where the resistance of the device pending on the ordinate, and the amplitude of the applied current pulse delayed by the abscissa, while the graph shows the different programming modes universal memory element;
Fig. 2 is a block diagram illustrating an embodiment (embodiment) of the method according to the invention for recording data in a universal memory element according to the invention;
Fig. 3 is a block diagram illustrating an embodiment of the method according to the invention for reading data from the portable memory element according to the invention;
Fig. 4 is a block diagram illustrating another embodiment of the method according to the invention for reading data from the portable memory element according to the invention;
Fig.5 is a block diagram of an embodiment of a device according to the invention for writing data to and reading data from the portable memory element according to the invention;
Fig.6 is a cross section of a memory element according to the present invention, having first and second contacts, each of which is adjacent to the volume of memory material;
Fig.7 - matrix scheme is part of the neural process is of;
Fig. 8 is a schematic illustration of a unit cell structure of the neural network according to the principles of the present invention;
Fig. 9 is a schematic representation of the site, consisting of two located one above the other planes of the unit cell structure of the neural network according to the principles of the present invention;
Fig. 10 is a schematic representation of another embodiment of a unit cell structure of the neural network according to the principles of the present invention, including bus ban and excitation;
Fig. 11 is a schematic illustration of another unit cell structure of the neural network according to the principles of the present invention, including a separate control bus;
Fig. 12 is a schematic illustration of another unit cell structure of the neural network according to the principles of the present invention, including tires excitation and prohibition, controlled by a common input bus;
Fig. 13 is a top view of a possible layout of the multiple memory elements, which can be used for storing data in accordance with the principles of the present invention, where, in particular, shows how can be connected to the memory elements to the set of address buses X-Y;
Fig.14 is a diagram of a matrix of memory elements, to the spine, shows how the insulating elements, for example, diodes, connected in series with the memory elements to electrically isolate the memory cells from each other;
Fig. 15 is a schematic representation of the single-crystal semiconductor substrate with an integrated matrix memory according to the principles of the present invention having electrical connection with the IC chip to which operatively attached address shapers/decoders; and
Fig.16 is a diagram of an embodiment of the present invention used to control the connectivity between nodes in the mesh network in the system of the neural network.

Detailed description of the invention
In Fig. 1 presents a graph of the relationship between the amplitude of the applied current pulse and a resistance device for a universal memory element according to the present invention. In Fig.1 shows the different programming modes. In the left part of the curve, the resistance of the device remains essentially constant (i.e. in a state of high impedance) until the device to be set to the initial state by a reset pulse is issued with sufficient energy. The device then again moves from a state with high resistance state of the safety device increases when the transition from a state with low resistance state with a high resistance. This increase is gradual and reversible, as shown by the arrows indicating the direction up or down on the right side of the curve. In this mode, the memory element Ushinskogo can be programmed to any resistance within the dynamic range of resistance values by filing a current pulse of appropriate amplitude. This type of scheme programming provides an analog storage device for data with multiple conditions and direct overwriting and represents the programming mode, described in patents Ushinskogo.

In the programming method according to the present invention uses the left part of the curve in Fig.1. In this mode, important as the amplitude and duration of the current pulses used for programming the device. The transition occurring in this part of the curve, is not reversible, as shown by the single arrow on the left side of this curve. That is, as soon as the device is translated from a state with high resistance state to low resistance, it may not be re-established in a state with a high resistance by filing a programming pulse with a reduced amount of current. Instead, the device is (i.e. "reset pulse"), which raises the resistance on the right side of the curve. As described above and described in more detail below, the digital multivalue device when programming in this mode arises from the ability of the memory device Ushinskogo "accumulate" or "integrate" the energy of each programming current pulse applied to the device.

Universal memory element according to the invention can store a lot of information bits in one memory element and, as described in more detail below, can be used to create a variety of compounds that provide the linkage between neurons or nodes of the neural network artificial intelligence.

Referring to Fig.1, assume that the device is in a state with a high resistance in the far left position on the left side of the characteristic curve in Fig.1. As explained above, if the unit is a single reset pulse with sufficient energy, it will be set in a state with a low resistance. As further explained above, that disclosed in the present invention and that really should be paid special attention in connection with the universal memory elements Ushinskogo, - etiam in the state with a low resistance can be divided into pointervalue or programming pulses, with the submission of each programming pulse, the resistance of the memory device is not actually modified until the total accumulated duration of the programming pulses becomes equal to or exceeds the above "installation length". As soon as the last programming pulse will take the last increment of energy, the device enters a state with a low resistance.

Thus, the installation impulse can be divided into several potentially pulses at regular intervals, each of which represents a bit of stored data. For example, if you want to remember in one memory element full eight-bit bytes, in one embodiment, the amplitude and height pointervalue pulse can be separated in such a way that to make the transition to a state with a low level will require eight pulses. Then eight levels of memorization will be the pulses from 0 to 7 for storing decimal values from "0" to "7". If, for example, on the item initially served 0 pulses for storing "0", then you will need 8 pulses for moving the element in a state with a low resistance, and this condition can be read as "0" by wiiti in each case determined by subtracting from the number 8 the number of pulses, needed to transfer the memory element in a state with a low resistance. For example, if you stored the number "7", the number of pulses necessary for transfer of the item in the condition of low resistance, will be 1, and therefore, the stored decimal value will be equal to "7". For storing and retrieving information in a universal memory elements according to the invention can be chosen in different logical protocols.

For further explanation refer now to the block diagrams in Fig.2, 3 and 4. In Fig.2 presents a flowchart illustrating a method of storing multi-bit information according to one variant of the invention. In this method, the step S10 is initiated operation start recording in memory. In step S11, the memory element is first set to a state with a high resistance. This is done in order to ensure a complete installation of the memory element in a state with a high resistance before beginning to write. In step S12 is selected multi-bit value or the number to be remembering, and the pulse counter is set to the preset reference value corresponding to the number of pulses which must be filed in the memory element. In the example above colocating values from "0" to "7". In step S13 in the memory element is served potentially impulse. In step S14 in the pulse counter adds one pulse count and reads the number of pulses that has been accumulated by the pulse counter.

In step S16 is determined, the value is the number of pulses accumulated in the counter at the moment, the reference number of pulses recorded in the counter. If the number of pulses read from the pulse counter is equal to the reference number stored in the counter, then in step S16, the operation is terminated. If the number of pulses read from the counter is less than the reference number stored in the counter, then return to step S13 in the memory element serves another potentially pulse, and the operation is repeated until the number potentially pulses becomes equal to the stored reference number, and at this point, the operation in step S16 is terminated.

In Fig. 3 presents a block diagram of a specific logical Protocol corresponding to the above example for wasmainly system for storage in a single memory element in the binary number from "000" to "111". In this method, the step S20 is initiated by a read operation of PAYE of the memory element. Next, in step S23 is defined below whether the resistance of the memory element threshold value corresponding to a state with a low resistance. If the memory element has not yet switched to a state with a low resistance, then in step S24 in the pulse counter adds one pulse count, and return to step S21 in the memory element serves another potentially impulse.

When it is determined that the resistance of the memory element is less than the threshold value, which indicates that toggles the state of low resistance, the method proceeds to step S25, at which the pulse counter is added to the unit of the pulse and triggers the reprogramming of the memory element. Reprogramming of the memory element can be realized, for example, by applying the method shown in the above-described flowchart in Fig.2.

Then, in step S26, it reads the counted number of the pulse counter, and in step S27, the number of pulses read from the counter is subtracted from the code described in the above example, to retrieve the stored binary value, which is read in step S28. For example, if a translation memory element in a state with no what I memorized the binary value "1". If the translation memory element in a state with a low resistance requires five pulses, the number five is subtracted from the number eight, to get the decimal number corresponding to the binary value of "011".

In the embodiment according to Fig.3, a read operation from the memory always starts with the filing of pointervalue pulse. In this embodiment the maximum amount of input pulses equal to the maximum value of the number stored in the memory element. However, in another embodiment the maximum amount of pulses per pulse is less than the maximum value memory number. In this embodiment, the resistance of the memory element can be set at a low resistance when a read operation from the memory began.

Sequence reads for this embodiment is shown in block diagram in Fig.4. In this embodiment, a read operation from the memory is initiated at step S31 and, since the memory element may already be installed in the state with a low resistance, the resistance of the memory element is read in the first step S31. If in step S32 it is determined that the resistance of the memory element is less than the threshold value, which indicates the presence of the element is Agay S33. However, if in step S32 it is determined that the resistance of the memory element is above a threshold, indicating the presence of a memory element in a state with a high resistance, then in step S34 in the memory element is served potentially pulse, and the resistance of the memory is read at step S35. If the resistance of the memory element is still above the threshold according to the determination in step S36, step S37 in the pulse counter is added to the unit of the pulse, and in step S34 in the memory element serves another potentially impulse.

When the resistance of the memory element is switched to a value corresponding to the state with a low resistance, as it is determined in step S38, the counter adds one pulse count, and in step S38 is reprogramming of the memory element. Then, in step S39, the system reads the pulse counter, and counts the number is subtracted from the code in step S40 to the step S33 to receive the stored binary number. In this embodiment, with reference to the above example of storing eight-bit byte, the selected code is 7. Thus, the subtraction of the zero pulse from the code number seven gives a decimal number seven that meet the ol, corresponding to the stored binary value "000".

In each case, the logical Protocol for recording the values stored in accordance with the method according to Fig.2, is chosen to match the Protocol read any of the selected variants according to Fig.3 or Fig.4, either consistent with any other Protocol that can be selected for storing information based on the number potentially pulses fed and read in the General case as described above.

In Fig.5 shows a device for the implementation in practice of the methods read and write to memory according to the present invention. In the embodiment of Fig.5 read operations and write to memory is performed by a device that includes a logical device 100 I/o and memory addressing, which is controlled by the commands read and write, applied to the input 102. The device 100 is connected to the pulse generator and counting device 104, which, in turn, is connected to the system 106 addressing reading and writing to memory and matrix memory 108, including universal memory elements of the present invention. The state of each memory element is addressed and determined and fed back with the team read and write to memory applied to the input 102 are implemented using the methods described above. For example, the read command input device 102 100 I/o and memory addressing for reading the selected multi-bit values from the selected memory cell causes a reaction device 100, which establishes the pulse generator and counting device 104 on the reference count value, and the response in the feedback circuit from the system 110 to determine when they have reached a reference value account. Addressing system read and write memory addresses specific memory cell, which must be filed with the read command.

The device 110 addressing memory status, feedback and output determines the state of the memory element in the addressable memory cell and either sends a signal back to supply additional subintervals pulses from the device 104, or reads the stored result to the output device 112. The write operation acts in the same way, by implementing the above methods.

As mentioned above, the multi-bit information stored in the universal memory element according to the invention in accordance herewith ways, is stored in non-detectable and therefore is the invention with the use of such device, what is shown in the embodiment of Fig.5. This helps to ensure efficient encryption of data stored in the universal memory elements.

In order to retrieve stored data shall be known as the amplitude and duration of unique pointervalue pulse. Any attempt to determine this experimentally or will not give any result at all, if the pulse amplitude is below a threshold, or will lead to a complete Erasure of the stored data, if the pulse amplitude is too large. Even if the amplitude and pulse duration are known, it is necessary to know also the code number and the Protocol that is selected for storing data, in order to get able to correctly read the stored data. For example, if the Protocol stored data required to undertake a reading as shown in the embodiment according to Fig. 3, and the read attempt would be made using the Protocol shown in the embodiment according to Fig.4, would have been an erroneous reading. Similarly, if the code number is, for example, six, not eight, it also would have been an erroneous reading. These additional levels of protection to complement the protection provided by the characteristics of the performance or complete failure when restoring or complete destruction of data without recovery.

Can also be entered and various other protocols to provide even more additional layers of protection. For example, the configuration of the device according to Fig.5 may be performed in such a way that before the resolution of reading the stored information in the output device 112 will need the correct programming of each memory element for the correct replacement of each stored multi-bit values. In this embodiment, if the data from the matrix memory 108 is read with errors and then, being read, being reprogrammed with errors, the output device 112 does not output the stored information and the original data will be destroyed.

In the above embodiments are used pointervalue pulses with equal amplitudes and durations. In other embodiments of the invention these pulses differ from each other in different settings. A more complete discussion of the parameters that affect the unique characteristics potentially pulses, and programming energy pulses in General follows.

Universal memory element according to the present invention contains a certain amount of material to memory with phase transitions, and this material has, on labradorite. The state with high resistance is characterized by high electrical resistance, and the state with a low resistance, low electrical resistance, which can be detected and distinguished from States with high electric resistance.

At least part of the volume of memory material is capable of passing from a state with high resistance state to low resistance in response to input of one energy pulse, which is defined here as "the installation of the energy pulse". The installation of the energy pulse has an amplitude and duration sufficient to transfer part of the volume of memory material from a state with high resistance state to low resistance. The amplitude of the installation of the energy of the pulse is defined here as the "adjusting the amplitude, and the duration of the installation of the energy of the pulse is defined here as "installation length". The act of translation of the volume of memory material from a state with high resistance state to low resistance is defined here as "installing" or "install", and so on) of the volume of memory material from a state with high resistance state is, can be of any kind, including (but not limited to) electrical energy, the energy of the beam particles, optical energy, thermal energy, electromagnetic energy, acoustic energy and pressure energy. Electrical energy can take the form of electric current or voltage. Preferably, the electrical energy had the appearance of an electric current, and the installation of energy-momentum is represented by the installation of the current pulse with the amplitude equal to the "adjusting the amplitude and duration equal to "installation length", which are necessary and sufficient to set the volume of memory material from a state with high resistance state to low resistance.

Without overloading the text description of theoretical calculations, we can assume that the energy supplied to the material memory with the installation of the energy momentum changes of local order, at least part of the volume of memory material. In particular, the applied energy causes at least part of the volume of memory material to change its state from a less ordered amorphous state to a more ordered "crystalline" state. Note that when used herein, the term "Amor is monocrystal, and has a detectable property, for example high electrical resistance. Used herein, the term "crystalline" refers to the state that from the point of view of the structure relatively more ordered than amorphous, and has at least one, different from the amorphous state, find a property, for example a low electrical resistance. Preferably, the low electrical resistance of the crystalline state is detected and distinguished from a high electrical resistance amorphous state. One set pulse of energy is the energy pulse with an amplitude and duration sufficient to cause crystallization of the material memory to the extent necessary so that he has moved from a state with high resistance state to low resistance. Note that the actual amplitude and duration selected as the setup amplitude and installation duration depend on specific factors, including (but not limited to) the size of the volume of memory material, the material used memory used form of energy, and means for supplying a specified energy in the material memory, etc.

As the op is of low resistance using one energy pulse, defined here as "the installation of the energy pulse". The memory element according to the invention can also be installed from a state with high resistance state to low resistance using multiple energy pulses, defined here as "program energy pulses (to distinguish them from the installation of energy pulse). Unlike the installation of the energy of each pulse from a variety of software energy pulse is insufficient to cause the installation of the memory material from a state with high resistance state to low resistance. However, each program energy pulse sufficient to change at least part of the material so that the accumulation of a multitude of software energy pulse sufficient to cause the transition from a state with high resistance state to low resistance.

Without overloading the text of the description theory, we can assume that each of a variety of software energy pulses supplied to the volume of memory material, "amends" in the material, causing some degree of crystallization (i.e., the formation of active centers and/or growth kriticheskih pulses, by itself, insufficient to cause a state change of the memory element from a state with high resistance state to low resistance. However, the "cumulative" crystallization caused by the joint action of many software energy pulse sufficient to set the memory element from a state with high resistance state to low resistance. Essentially part of the volume of memory material "accumulates" changes (i.e. crystallization) caused by each separate program energy pulse applied to the device.

In the General case, all of the amplitude and duration of each of the many potentially or software energy pulses may be different. In one embodiment, all of the same amplitude and are preferably equal to the amplitude of the installation of the energy pulse (i.e., "installation amplitude"). The duration of each program energy pulse are selected by dividing the time interval of the installation of the energy pulse, "installation length" on many potentialof. (Therefore, the total duration of all potentialof equal "installation dlitelnosti of peginterferon.

Consequently, many potentially or software energy pulses can be used to set the memory element from a state with high resistance state to low resistance, where each software energy pulse has an amplitude equal to the amplitude of the installation of the energy pulse, and every program energy pulse has a duration equal to a unique duration of peginterferon. As discussed above, the resistance of the memory element is not actually changed, remaining relevant state with a high resistance, while the volume of memory material will not be submitted latest software pulse of energy. As soon as the last software pulse of energy is filed, the device enters a state with a low resistance.

Again it should be noted that the energy supplied to the volume of memory material may be a pulse of electric current. Therefore, the memory element can be installed from a state with high resistance state to low resistance using a variety of software current pulses, where each software current pulse alone is not enough to have the pulse", can be divided into putinterval. Many programming current pulses may be filed in the memory material, each software current pulse has an amplitude equal to the amplitude of the installation of the current pulse, and each software current pulse has a duration equal to a unique duration of peginterferon. Installation of the device will occur after the filing of the final software current pulse.

In one embodiment, data may be written into the memory element by filing one or more software energy pulses in the volume of memory material. In the General case, all of the amplitude and duration of software energy pulses can be different. The amplitude of each program energy pulse can be chosen to be equal to the "adjusting the amplitude of the" installation energy pulse described above. The duration of each program energy pulse is such that each pulse in itself is insufficient to set the volume of memory material from a state with high resistance state to low resistance, and the total duration of all software energy pulse is less than or equal ustanovovala memory may be submitted in the form of current pulses. Again refer to Fig.1, where it is shown that when the amplitude of the applied current pulse increases to a sufficient value, the device switches from a state with high resistance state to low resistance. One current pulse sufficient to install memory material from a state with high resistance state to low resistance, is defined here as "the installation of the current pulse with the amplitude, defined as "the distribution amplitude, and duration, defined as "installation length".

Data can be written into the memory element by filing in the volume of memory material of one or more software current pulses, with each software current pulse is insufficient to install the device. In the General case, all of the amplitude and duration of the software current pulses can be different. In one embodiment, the amplitude of each software current pulse is equal to the installation amplitude, defined above. In addition, the duration of each program current pulse is (1) so that each pulse itself is insufficient to cause a state change material from a state with high SoH pulses is less than or equal to "installation length", defined above.

In one embodiment of this method of programming, as described above, the duration defined by the "installation length", is divided into putinterval. The number of peginterferon selected one less than the required number of all possible States programming. For example, if you want only five States programming, the time interval "installation length" is divided into four putinterval (so that the total duration of all four potentialof equal "installation length"). Preferably, all potentially were the same (however, there may be other embodiments of using unequal putinterval).

The element can be programmed in the desired "programmed state" by filing one or more software current pulses, where each software current pulse has a duration equal to the duration of potential, and amplitude equal to the "adjusting the amplitude of the installation of the current pulse. In the example, which uses only five States, if the software current impulse is not filed, the memory element remains in state I, if there is one software current pulse, elbolet to be in condition III, if filed three potentially pulse, the memory element will be in condition IV, and if filed four potentially current pulse, the memory element will be in state V.

Note that the resistance of the memory material is not actually modified until the total duration potentially pulses becomes equal to or exceeds the "installation length". In the above example, the resistance does not actually change until you submitted the fourth
potentially impulse. After the submission of the fourth pulse, the resistance of the memory element is changed from a state with high resistance state to low resistance.

The programmed state of the memory element can be read by filing additional software current pulses, while the material of memory installed in the state with a low resistance and is counting the amount of additional pulses. In the above example, when the data in the memory element was originally filed one software current pulse, the programmed state is the state II. In this case, in order to set the memory element to a state with a low resistance the condition can be determined by subtracting the number of additional pulses (in this case 3) of the total number of possible States (in this case 5). Therefore, the programmed state is 5-3=2 (that is, condition (II).

Therefore, as described in connection with the above mentioned variants of embodiment of the invention, the device may be read by determining first whether the portion of the volume of memory material in a state with low resistance. If not, then served additional programming pulse of energy, and re-evaluates the resistance of the device. If the memory element is still not in a state with a low resistance, then served one additional programming pulse of energy, and is again determined resistance of the device. This procedure is repeated until then, until it is determined that the device is in a state with low resistance. Count the number of additional software current pulses required for installation of device (i.e. every additional software required energy pulse counter status can step by step increase), and this number is used to determine the programmed state.

The programming method may further include the step of erasing a mini-reset pulse is this pulse of energy sufficient to change the resistance of the volume of memory material from a state with low resistance state with a high resistance. Preferably this pulse of energy sufficient to change at least part of the volume of memory material from a more ordered crystalline state to a less ordered amorphous state. Note that the above software energy pulse (or software current pulse) are not sufficient to change the resistance of the volume of memory material from a state with low resistance state with a high resistance. As noted above, energy can be an electric current. Therefore, the current reset pulse" is a pulse of electric current sufficient to change the resistance of the volume of the memory element from a state with low resistance state with a high resistance.

Although the above discussion was mostly carried out in terms of current pulses, it should be noted that to implement the method of programming according to the present invention can be used any kind of energy. These forms of energy include electrical energy, APU and pressure energy. As discussed above, in one embodiment of the present invention described here, the programming method uses pulses of electric current to program the memory element by feeding current pulses, while the memory element of the present invention further includes a means for delivery of electrical energy, at least in part of a volume of memory material. In the General case, the "current" is defined as the flow of electric charges. Examples of electric charges are electrons, protons, positive and negative ions and charged particles of any other type. The flow of electric charges can occur because of a charged particle beam, for example beam of electrons or protons.

In one embodiment of the present invention the means for delivery of energy pulses) are the first contact and the second contact. Each of the contacts is adjacent to the volume of memory material. Used here contact "adjacent" to the volume of memory material, if at least part of the contact is really about memory material.

In another embodiment of the invention the first and second contacts are a pair of spaced flat contacts, compact layers. In Fig.6 shows the cross-section version of the memory element is performed on the single crystal silicon semiconductor substrate 10. The memory element includes a memory material 36, the first spaced contact 6 adjoining the volume of memory material and the second spaced contact 8A, adjoining the volume of memory material. In the shown embodiment of the invention the first and second contacts 6, 8A are flat contacts. At least one of the contacts 6, 8A may contain one or more thin-film layers. An example of a memory element, where the first and second contacts 6, 8A have two thin-film layer, has been described in the patent application U.S. 08/739080 owned by the present applicant, which is referred to as links.

The layer of memory material 36 is applied to a thickness of preferably from aboutto aboutmore preferably from aboutto aboutand most preferably from aboutto about
The memory element shown in Fig.6 may be performed during a multi-step process. First NAPA to get the area of contact between the memory material 36 and the contact layer 8A. Then napylyaetsya layer memory 36 and a contact layer 6, and the entire set of layers 8A, 46, 36 and 6 is subjected to etching to a selected size. On top of the entire structure of the deposited layer of an insulating material 39. Examples of insulating materials are SiO2Si3N4and oxysulfide tellurium (e.g., TeOS). The layer of insulating material 39 is subjected to etching and is deposited aluminium layer 42 to create a grid structure 42 of the second electrode, which is located in a perpendicular direction with respect to the conductors 12, and terminates the connection grid XY individual memory elements. Complete integral structure is covered with a sealing layer of a suitable sealant, for example Si3N4or plastic, for example polyamide, which protects the structure from moisture and other external elements that can cause aging of the material and the performance deterioration. Sealant Si3N4can be applied, for example, during a low-temperature plasma spraying. The polyamide material may be applied by centrifugation and subjected to annealing after deposition, in accordance with known methods for the formation of hermeti is e, one "cone-shaped" contact. The cone - shaped contact is a contact that tapers to the top, adjoining the volume of memory material. Version of the memory element which uses a cone-shaped contact, described in U.S. patent 5687112 issued Ushinskogo and others, referred to as links.

Means for feeding can also represent at least one field emitter. The field emitters are discussed in U.S. patent 5557596 issued by Gibson (Gibson), and others, referred to as links. The emitter of the field is narrowed to the apex, which is located in the immediate vicinity of the volume of memory material. Used the term "in close proximity" means that the field emitter in fact is not in contact with the volume of memory material. Preferably, the emitter of the field was at a distance of approximatelyto aboutfrom the volume of memory material. More preferably, the emitter of the field was at a distance of approximatelyfrom the volume of memory material. The field emitter emits electrons from its conical top. As discussed in the patent '596 may be located annular shutter and created an electric potential difference between the field emitter and the gate. In an alternative embodiment, the electric potential difference can be created between the field emitter and the actual volume of memory material. In one embodiment, the contact (for example, a flat contact) can be located so that it will abut to the volume of memory material and located at a distance from the emitter of the field. The electric potential difference can be created between the field emitter and the flat contact, so that the electron beam is directed into the volume of memory material and bombards the material memory. Can also be used multiple emitters of the field.

The field emitters can be created in several ways. One way is discussed in Spinda (Spindt and other "Physical Properties of Thin-Film Field Emission Cathodes With Molybdenum Cones", published in the Journal of Applied Physics Vol. 47, No 12, December 1976. Another way is discussed in the article by Betsy (Betsui) "Fabrication and Characteristics of Si Field Emitter Arrays", published in the Tech. Digest of the IV-th Int. Vacuum Microelectronics Conf., Nagahama, Japan, page 26, 1991.

Between the field emitter and the volume of memory material may be a partial vacuum. As discussed in the patent '596, a partial vacuum may be, at least, 133, 32210-5PA (10-5Torr). Methods of manufacturing) is the work of Jones (Jones) "Silicon Field Emission Transistors and Diodes", published in IEEE Transactions on Components, Hybrids and Manufacturing Technology, 15, page 1051, 1992. In an alternate embodiment between the field emitter and the volume of memory material may be a gas.

In another embodiment of the present invention the means for supplying electric current represents the tunneling contact, which is located in the immediate vicinity of the volume of memory material. Tunneling contact may be similar to the emitter of the field. It can be narrowed to the apex, which is located in the immediate vicinity of the volume of memory material. Tunnel contact in fact does not apply to material memory, but it is located within the width of the quantum-mechanical potential barrier. Preferably, this distance was less than.

Examples of materials with phase transitions proposed in U.S. patent 3271591 and U.S. patent 3530441, which are referred to as links. Other examples of materials with phase transitions can be found in U.S. patent 5166758, 5206716, 5534711, 5536947, 5596522 and 5687112 referred to as a reference and owned by the present applicant.

Material with phase transitions should be preferably "non-volatile". Used here Terme, memorized in the memory cell (the selected limit error), without the need for its periodic updates.

The volume of memory material may contain a mixture of dielectric material and the material described above with phase transitions. "Mixture" can be either a heterogeneous mixture or a homogeneous mixture. Preferably, the mixture was heterogeneous. Material memory that contains a mixture of material with phase transitions and dielectric material, disclosed in patent application U.S. 09/063174 referred to as a reference and owned by the present applicant.

Used herein, the term "material with phase transitions" is defined as material that can switch from differing from each other detectable States with a large local order (more crystalline state) in States with smaller local order (less ordered or more amorphous state) and back by feeding energy into electrical energy or other form. Materials with phase transitions according to this invention additionally exhibit properties, which consists in the ability to perceive the portion of energy that is below the level required for the occurrence of detectable changes in local order, but is the reception of the change in local order after submitting several portions of energy.

Preferably, the material with phase transitions according to the invention include one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys. Material with phase transitions preferably includes at least one chalcogenide element and may include at least one element of metals of the transition groups. Preferably, the chalcogenide element selected from the group consisting of Te, Se and mixtures or alloys. More preferably, the chalcogenide element was a mixture of Te and Se.

Used herein, the term "transition metal group" refers to elements 21 through 30, 39 through 48, 57 and 72 to 80. Preferably, an element of transition metals group selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys. Most preferably, the metal of transition group was Ni. Specific examples of such multiple systems are outlined hereinafter with reference to the system Te:Ge:Sb with or without Ni and/or Se.

Additionally we assume that the size of the crystals that exist in the mass of semiconductor material memory is relatively small, preferably of the order of less than
Many materials with phase transitions according to the present invention have a tendency to form larger or smaller crystals per unit volume. It is established that the size of the crystals lying in the most broad preferred range of materials embodying the present invention, much less aboutand in General smaller than the range of values of the order ofwhich was typical for the materials of the prior art. The crystal size is defined here as the diameter of the crystals or "characteristic size", which is equivalent to the diameter when the crystals are not spherical in shape.

It was determined that the composition in the state with high resistance for materials of class TeGeSb that meet the criteria of the present invention typically show actually low concentrations in relation to known existing materials for the electrically erasable memory. Examples of materials TeGeSb shown in U.S. patents 5534711, 5536947 and 5596522 owned by the present applicant. In one composition, which provides significantly enhanced performance in an electric switch, medium, from about 23% to about 58% of Those and the most preferred range is from about 48% to 58% of Those. Ge concentration above about 5% and range on average from about 8% to about 30% in the material, where the concentration remains below 50%. Most preferably, the Ge concentration lying in the range of from about 8% to 40%. The other main ingredient in this composition was Sb. Data percentages are atomic (percentage) concentrations, which amounts to 100% of the atoms of the constituent elements. Thus, this structure can be described as ThoseandGEbSb100-(a+b). These ternary alloys Te-Ge-Sb are useful starting materials for the development of additional materials with phase transitions with better electrical characteristics.

Materials with phase transitions according to the present invention preferably include at least one chalcogenide element and may include one or more metals of the transition groups. Materials with phase transitions, which include transition metals group, simply modified forms of materials in the three-component system of Te-Ge-Sb. To have simply modified materials with phases of acacia is achieved by incorporating transition metals group in the basic three-component system of Te-Ge-Sb with or without additional chalcogenide element, for example Se. In the General case simply modified materials with phase transitions are divided into two categories.

The first category materials with phase transitions include Those of Ge, Sb and a transition metal group with a ratio (TeaGebSb100-(a+b))withTM100-cwhere the indices are expressed in atomic percent concentrations that adds up to 100% of the constituent elements, TM is one or more metals of the transition groups, a and b have been explained above for the three-component system of Te-Ge-Sb, and lies in the range of from about 90% to 99.99%. The metals of the transition groups preferably include Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys.

The second category of materials with phase transitions are Those, Ge, Sb, Se and a transition metal group with a ratio (TeaGebSb100-(a+b))cTMdSe100-(c+d)where the indices are expressed in atomic percent concentrations that adds up to 100% of the constituent elements, where TM is one or more metals of the transition groups, a and b have been explained above for the three-component system of Te-Ge-Sb, lies in the range of from about 90% to 99.5%, a d - in the range of from about 0.01% to 10%. The metals of the transition groups may preferably include Cr, Fe, is ostanovochnyy values of resistance. However, if the resistance value of the material with phase transitions is not rejected ("drifting") from the initially set value, to compensate for such changes can be used "compositional modification described below. Used herein, the term "nonvolatile" refers to the condition in which the set value of resistance remains virtually constant over time intervals of storage. Of course, to assure the total absence of "drift" resulting in exceeding the allowable limit of error, can be used software tools (including the above feedback system).

Defined here, the term "compositional modification" includes any means of modifying the composition of the material from phase transitions to ensure almost stable values of resistance, including adding items to stretch the width of the forbidden zone, to increase her resistance material. One example of compositional modification is the gradual inclusion of compositional heterogeneities in thickness. For example, in the material volume phase transitions can be made gradual change from Pervov is any form, which reduces the drift of the set resistance value. For example, gradual compositional change is no need to limit the first and second alloy of the system are the same alloys. Gradual change can also be accomplished with a number of alloys more than two. Gradual change can be homogeneous and continuous either heterogeneous or non-continuous. A specific example of the gradual compositional changes, which leads to the reduction of drift values of the resistance, includes uniform and continuous gradual transformation of Ge14Sb29Te57on one surface Ge22Sb22Te56on the opposite surface.

Another way to use compositional modification to reduce the drift resistance is the split of the volume of material with phase transitions. That is, the volume of material with phase transitions can be formed from many separate relatively thin layers of different composition. For example, the volume of material with phase transitions may include one or more pairs of layers, each of which is made of a different alloy of Te-Ge-Sb. Again, as in the case of gradually changing composition compositions can be placed. Layers can have the same thickness or may be of different thickness. Can be used any number of layers, and the volume of memory material may be multiple layers of the same alloy, either contiguous or separated from each other. Can also be used layers of any number of different alloys. A specific example of a composite bundle is the volume of memory material that includes alternating pairs of layers, GE14Sb29The57and Ge22Sb22Te56.

Another type of compositional heterogeneity to reduce the drift resistance is accomplished by a combination of gradual compositional changes and compositional stratification. In particular, the above-mentioned gradual compositional change can be performed in combination with any of the above compositional stratification for the formation of a volume of memory material with stable resistance. Examples of volumes of material with phase transitions, where it is used this combination are: (1) the volume of material with phase transitions, which includes a discrete layer of Ge22Sb22Te56followed by gradually changing the composition of Ge14Sb29T is the layer Ge14Sb29Te57and gradually changing the composition Ge14Sb29Te57and Ge22Sb22Te56.

The memory material may be performed using techniques such as sputtering, evaporation or chemical vapor deposition (CVD), which can be improved by using plasma technology, for example radio frequency glow discharge. It is most preferable to create the material memory of the radio-frequency sputtering or evaporation. It can be performed with the use of technology sputtering from a variety of sources using a variety of targets - usually the target material with phase transitions and the target of a dielectric material. When the location of these targets on the substrate against each other sputtering is performed when the substrate is rotated relative to each target. Can also be used a target containing the material with phase transitions and dielectric material. In addition, for a controlled change of the morphology of the material with phase transitions within the composite memory material formed due to the effect of crystal growth and aggregation of crystals due to the displacements of the surface, the present invention is a network of parallel processing, for example the network, which can be used in neural networks and computing systems, artificial intelligence. Network parallel processing contains interconnected vertically set for parallel distributed data processing, which includes many stacked on top of each matrix of unit cells. Each unit cell has a connection for data transmission, at least one other single cell on adjacent planes. Preferably, a single cell on this plane were to some extent linked. Thus can be installed high degree of connectivity between individual cells of the set. Network parallel processing are disclosed in U.S. patent 5159661 referred to as a reference and owned by the present applicant.

Neural computation based on the imitation of the method of calculation used by neurons in animals. Neuron accepts electrical signals from many other neurons. Each of these signals neuron assigns a weight or importance. Assigned weight "recognized" by the system empirically. When the sum of the weighted input signals exceeds a threshold value of the other neurons.

Universal memory elements of the present invention can be included in a system of neural networks so that they behaved in much the same way. In a specific embodiment of the universal memory element served a number of weighted pulses until it reaches the threshold and the element will not turn on or "excited". An additional advantage of the present invention is that the pulse should not be submitted simultaneously. The impact of each pulse is stored in non-volatile form and remains in memory until it is filed on the next pulse in addition to the already memorized the pulses. Thus can be supported by the behavior of a neuron that uses a serial pulse applied in any order in time.

This provides a simple regular structure in the form of a set of memory elements to perform logical functions of neurons. One embodiment of the present invention, included in a processor of the neural network shown in Fig.7. In this embodiment of the universal set of memory elements 200 of the present invention is formed with isolating diodes 202. As shown in the figure, the output columns are set to the input lines of namorada separate memory element 200 is in a state of high resistance, the degree of connectivity between the row and column to which it is connected is low due to high resistance.

Weighted pulses of current pathogens in a generic memory elements 200 through isolating diodes 202 using management strategy, according to which the decision when to apply pulses and what weight to assign to them. The impact of these pulses cumulatively stored in each memory element. When in any given memory element is reached the selected threshold level, the item is switched or "excited" by moving into a state with a low resistance, to increase the level of connectivity between the row and column to which it is connected, because of the low resistance of the installed link.

A single cell that can be used in this embodiment and in other embodiments, shown in Fig.8, illustrating a typical single cell, which can be used in the present invention. The unit cell includes a bus 10 data entry and bus 12 data output. The relationship between the two tires 10, 12 is installed through the universal memory element 14 of the present invention. In Fig.9 schematically depicts ice, United through vertical vias 44. It is assumed that a similar stacked on top of each matrix are included in the scope of the present invention shown here for other unit cells.

The unit cell further includes an isolation device, for example a diode 16. Usually the unit cells are arranged in a set, where the bus 10 data entry and tires 12 output data contain the number of rows and columns, and in this embodiment, the insulating unit 16 is designed to prevent crosstalk between adjacent unit cells. The insulating device is depicted in the form of a diode 16 and as such may include a thin-film diode, for example polycrystalline silicon diode, although likewise there can be used an amorphous, polycrystalline or crystalline diodes of various other materials, as well as other devices, for example transistors. In the manufacture of structures containing the chalcogenide elements and polycrystalline diodes, the diodes are typically performed by spraying in the form of amorphous devices using thin-film technology, and then these diodes crystallize. According to the present invention, it was found that the crystallization of the material documento, single high speed of crystallization of the material of the diodes without destroying the chalcogenide material.

The cell of Fig.8 is a part of the matrix in the General case of identical cells arranged in rows and columns. The processor of the present invention includes a set of such stacked on top of each of the matrices, and at least some cells of the first matrix are connected with the cells in the second matrix, so that the output data of the cell on the first plane 140 is connected to the input of the cell on the second plane 142.

Note that the vertical vias 44 in Fig.9 provide a means of connection between the bus 10 data input of the first unit cell in the matrix 140 and the bus 12 data output of the second unit cell in the matrix 142. As can be seen from Fig.9, the communication occurs through the volume of memory material, at least one unit cell. The connection between the bus 10 data entry in the matrix 140 and the bus 12 output matrix 142 is determined by distinguishable programmed States of the chalcogenide material on the basis of multivalued digital memory element with phase transitions.

The network data may additionally include a means for programming each unit cell in one the sky signal in the volume of memory material, each unit cell. In Fig.10 depicts a single cell, including the input excitation 18 and the input prohibition 20, and a bus 12 data output. Version additionally includes universal multi-valued digital memory element 14 and the insulating unit 16 associated with each of the input tyres 18, 20. The unit cell of this type can receive bipolar data, which either encourage or prohibit the output response. In the above single cell multi-valued digital memory element Ushinskogo is programmed by signals on bus 10, 18, 20 data entry and bus 12 data output.

In Fig.11 depicts another embodiment of the present invention, which further includes a field-effect transistor 22 having its source and drain connected in series with the bus 10 data entry and multi-valued digital memory element 14 Ushinskogo. The shutter 24 of the transistor receives a signal from a separate bus 26 management. In the unit cell of this type, the data supplied to the bus 26 management can modify or add data to the bus 10 of the input, so that further affect the installation and return to its original state multivalued digital memory element 14 Ushinskogo.

In Fig. 12 shows another paplasinasanai 22 with its source and drain, series-connected with a universal multi-valued digital memory element 14 and an isolating diode 16. The control gates 24 of each of the transistor 22 is performed on the shared bus 28 management. When the work of a single cell of this type is common bus 28 control receives the input data, for example data from the pixel of the image sensor and transmits the data to the unit cell. These excitation and barring, in appropriate tyres 18, 20 alter the response of cells to these data, generating an output signal which is transmitted to other cells in the network data processing.

Note that the network parallel processing according to the present invention includes a tool for parallel input data set. Means for parallel input data set may also include means for detecting a pre-selected chemical contaminants and generating in response to this electric signal.

In addition, a means for parallel input data set may include a means for parallel input electrical data. Also a tool for parallel input data set may include a means for parallel input optical data. Means for parallel-input protected areas is about to convert the optical data into electrical data may include a photosensitive substrate from the silicon alloy.

It is clear that the above illustrates a specific configuration of a unit cell of a neural network, which can be used in the present invention. Similarly can be used and other variations of a single cell. The present invention covers all the sets for parallel distributed processing data having interconnected unit cells, which include universal multi-valued digital memory element according to the present invention. The present invention is easily adapted for production computing systems, neural networks, and various other devices parallel data processing.

In the context of the present invention it is preferable that the volume of memory material was a material on the basis of chalcogenide elements. Materials based on chalcogenide elements include one or more chalcogenide elements, group IVa of the periodic table. The volume of memory material may include one or more elements from the group consisting of carbon, silicon, germanium, tin, lead, phosphorus, arsenic, antimony, fluoride and bismuth.

Another use of the memory elements of the present invention includes (m the data in multiple memory elements. As shown in this figure, device form the matrix X-Y memory elements. Horizontal bars represent the set of electrode grids X-Y addressing of individual elements. Vertical bars represent the set Y address buses.

Each memory element is electrically isolated from the others through the use of insulating elements of any type. In Fig.14 shows the layout of the memory devices, where it is shown as it may be made of electrical insulation using diodes. The schema contains a grid of X-Y with elements 14 memory, electrically connected in series with an isolation diode 16. Address bus 12 and 42 are connected to external circuits addressing method, well known to specialists in this field of technology. The purpose of isolating elements is to allow read and write for each individual memory element without interference from the data stored in adjacent or remote memory elements of the matrix.

In Fig. 15 shows a portion of the single crystal semiconductor substrate 50 formed with the matrix 51 memory according to the present invention. On the same substrate 50 formed matrix 52 addressing, which respectively padcadiarce signals, which defines and manages the installation and reading of the pulses supplied to the matrix 51 memory. Of course, the matrix 52 addressing can be combined and manufactured simultaneously with the solid matrix 51 memory.

In another embodiment, shown in Fig.16, a universal memory element according to the invention is included as a linking element in the mesh network system of the neural network. As shown in Fig.16, the generic element of the memory 302 according to the invention has the configuration in the form of a device with three conclusions, which is the output 304 to control the output 306 for signals and a common output 308 to control and signals. Conclusions 304 and 306 are connected to one electrode 310 of the device 302, and the output 308 is connected to another output 312 of this device. The electrodes 310 and 312 are connected to the element 314 with phase transitions for controlling its switching as described above.

Conclusions 306 and 308 are connected respectively to nodes 316 and 318 mesh network system of the neural network. Thus, the element 302 memory connected to control the connectivity between nodes 316 and 318. That is, when the element 302 is in a state with a high resistance, the connectivity between nodes 316 and 318 minimum, and when the element 302 is in the condition shown in the embodiment using the system 320 of the control neural network, which is connected to the electrode 310 through the control pin 394 and electrode 312 through the common output 308. System 320 of the control neural network delivers the weighted pulses on the universal element 302 memory through the conclusions 304 and 308, using control strategy, according to which the decision when to apply pulses and what weight to assign to them. The impact of these pulses cumulatively stored in the element memory 302. When the element 302 of the memory is reached the selected threshold level, the item is switched or "excited" by moving into a state with a low resistance, to increase the level of connectivity between nodes 316 and 318. If required, between the node 316 and the output 306 to isolate the mesh network from the control pulses, which are fed to the output 304 of the control, can be inserted blocking diode.

Conclusions 304, 306 and 308 can be located next to the element 302, or the distance from the element to easily provide communication with other devices and circuits. For example, when using the embodiment according to Fig.16 in the integrated design conclusions 304, 306 and 308 can be positioned to best suit the stages of formation and metallization element in integral/p> In the embodiment according to Fig.16 shows only a pair of nodes in the mesh network, which contains many nodes, and it should be clear that all or any selected part of the nodes in the network can be interconnected with elements of connectivity according to the invention as shown in Fig.16.

As previously discussed, the programming method of the present invention is applicable in the field of cryptography. One of the main methods of cryptography is the use of the encryption key. This key is used to encrypt and decrypt transmitted data. The problem of using the key is that if the key is known to a third party, the encrypted information can be decoded. Currently, the best available encryption keys have a length in the hundreds and thousands digits. No one can remember such a long number. Therefore, the encryption key for the data transmitted, for example, via the Internet, can be stored on the hard drives of the computers involved in the transfer of data. Storage on the hard disk makes it available to any person who gains access to these computers by simply reading information directly from the hard disk. Thus, to obtain the encryption key is not extending t the PTO disclosed here, for storing encryption keys eliminates the problem of unauthorized readout of the encryption key. In other words, due to the fact that reading necessary to determine the state of each memory element has a destructive character, face, trying to read the key programmed in the universal set of memory chips according to the invention, without knowing the width, amplitude and other parameters of programming pulses used to program the memory elements will not be able to reliably read data stored in the memory element.

For example, suppose that during programming of the memory element Ushinskogo as the total number of pulses required to switch the device from a state with high resistance state to low resistance, was used 8 pulse duration of 40 NS. Furthermore, assume that the memory was programmed using 5 pulses, which means that it will take another 3 pulse to install the device within the required total time of 120 NS. Now suppose that some people who do not know how it was programmed, the device will attempt to read the status of this software, ustroystva they will attempt to read information from the device, they are more likely to correctly select the duration of the programming pulse. Suppose, for example, that they will choose the programming pulses with a length of 60 NS to try to read data from the device. They will be served on the device only two pulse before it switches from a state with high resistance state to low resistance. Therefore, even if they knew the total number of States of the programming, they will get the wrong result equal to 6, instead of the programmed 5. Additionally, if the total number of States of the programming is not known, it is impossible to know the number from which is subtracted the number of pulses required to install the device in a state with a low resistance.

Therefore it is clear that, without knowing the parameters of the programming of memory elements, it is impossible to read the programmed state of the device.

It is clear that the detailed description of examples of embodiment of the invention is intended for a full and complete statement of the present invention, and that these details should not be construed as limiting the actual amount of patent protection this izobreteniya

1. Method of storing and retrieving information in the memory element with phase transitions containing material memory with phase transitions, having at least a state with high resistance and discover excellent condition with low resistance, and the material with phase transitions is made with possibility of installation of a state with high resistance state to low resistance with the installation of the energy pulse, and the method includes the following steps, which are: remember the information in the memory element by feeding at least one software energy pulse in the material memory with phase transitions, moreover, at least one software pulse of energy sufficient to install memory material from a state with high resistance to find excellent condition with low resistance, but enough to change memory material, so that the accumulation of at least one software energy pulse with at least one additional program energy pulse sets the memory material from a state with high resistance detectable ex in the memory element additional software energy pulses until while the memory element will not be forced to switch to discover excellent condition with low resistance, and calculate the number of additional software energy pulses filed in order to cause switching of the memory element in a state with a low resistance.

2. The method according to p. 1, in which said energy is electrical energy.

3. The method according to p. 1 in which the said material with phase transitions contains one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys.

4. The method according to p. 3, in which the said material with phase transitions comprises at least one chalcogenide element and at least one element of metals of the transition groups.

5. The method according to p. 4, in which the chalcogenide element selected from the group Te, Se and mixtures or alloys.

6. The method according to p. 3, in which the chalcogenide element is a mixture of Te and Se.

7. The method according to p. 6, in which at least one element of metals of the transition groups are selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys.

8. The method of controlling the element in the relationship to change connections in the neural network, and ENISA as the state with the high resistance state to low resistance, when this material with phase transitions is made with possibility of installation of a state with high resistance state to low resistance through the installation of energy and momentum from a state with low resistance state with a high resistance with energy reset pulse, and the method includes the following steps in which: serves energy reset pulse to the unit cell for the installation of material from phase transitions to the initial state with a high resistance, and served in the unit cell software energy pulses with the selected weights and durations based on the management strategy of the neural network, and at least several program energy pulses separately is not enough to install memory material from a state with high resistance state to low resistance, but enough to change the material with phase transitions, so that the accumulation of at least several program energy pulses with at least one or more additional program energy pulses sets material with phase transitions of so, forming the second level of connectivity that is different from the first level to a state with high resistance.

9. The method according to p. 8, in which said energy is electrical energy.

10. The method according to p. 8 in which the said material with phase transitions contains one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys.

11. The method according to p. 10, in which the said material with phase transitions comprises at least one chalcogenide element and at least one element of metals of the transition groups.

12. The method according to p. 11, in which the mentioned chalcogenide element selected from the group Te, Se and mixtures or alloys.

13. The method according to p. 12, in which the mentioned chalcogenide element is a mixture of Te and Se.

14. The method according to p. 13, in which at least one element of metals of the transition groups are selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys.

15. The control device level connectivity between nodes in the mesh network system neural network containing a single cell containing material with phase transitions, having at least a state with a high resistance and a state of low resistance is the opposition in the state with a low resistance through the installation of energy and momentum from a state with low resistance state with a high resistance with energy reset pulse, the first and second electrodes, electrically connected with the material with phase transitions for (1) supply electrical energy into the material with phase transitions with the aim of switching material with phase transitions from the high resistance state to low resistance and back, and (2) to set the channel holding signal through the material with phase transitions, when the material with phase transitions is in a state of low impedance, the output control and output signals, which are both electrically connected with the first electrode, the total output for the control signal and connected with the second electrode, moreover, the output signal is electrically connected to the first node in the mesh network, and the total output of the control signal and electrically connected with the second node of the mesh network to control the level of connectivity between the first and second nodes, and a control system, neural network, electrically connected to the output management and General output control signal and for supplying particulate control pulses in the material from phase transitions to force the material from phase transitions to switch from a state with high resistance state to low the influence of the control pulses will exceed the level of the threshold switching material with phase transitions.

16. The device according to p. 15, in which said energy is electrical energy.

17. The device according to p. 15, in which the said material with phase transitions contains one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys.

18. The device under item 17 in which the said material with phase transitions comprises at least one chalcogenide element and at least one element of metals of the transition groups.

19. The device according to p. 18, in which the mentioned chalcogenide element selected from the group of Te, Se and mixtures or alloys.

20. The device according to p. 19, in which the mentioned chalcogenide element is a mixture of Te and Se.

21. The device according to p. 20, in which at least one element of metals of transition group selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys.

 

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