A method of manufacturing a semiconductor element with a partially held in the wiring substrate, and also made by this method, the semiconductor element

 

The invention relates to the manufacture of secure integrated circuits, namely the method of manufacturing a semiconductor element passes at least partially in the substrate wiring, but also the semiconductor element. According to the stages of the method of manufacture includes at least one passing in the semiconductor substrate and at least one passing on the semiconductor substrate conductive connection. In the semiconductor element manufactured according to the invention, can be used in those cases when it comes to high reliability against external manipulations. 2 C. and 10 C.p. f-crystals, 7 Il.

The invention relates to a method of manufacturing a semiconductor element with a partially held in the wiring substrate, and is made this way, the semiconductor element. Semiconductor elements with partially held in substrate systems are known, for example, from DE 3502713 A1 and DE-AS 1614250.

Integrated circuits, particularly CMOS, made with many technological operations. The manufacturing costs of these schemes are defined in this complex process and the technological operations and many days for the technological cycle of the product.

Part of the technological operations are having to spend on the production of wiring, which connects individual active elements or provides connection of the integrated circuit to the "outside world". Usually this connection is implemented through one or more planes of conductive tracks of the aluminium.

There are, however, areas where the plane of the conductive tracks of the aluminium first, too expensive, and secondly, it requires a large area. In addition, the integrated circuit can be implemented using aluminum wiring, are not sufficiently protected from external manipulation or further analysis schema.

In order to be able to manipulate integrated circuit, first, as a rule, to analyze an integrated circuit. This requires layer upon layer to remove a passive layer or insulating layers between the conductive planes of the tracks, so that you can explore that opens, thus the plane of the wiring. If the plane of the wiring is made in the form aluminum wiring, circuit analysis can be performed relatively simply.

The basis of the invention lies therefore the task of creating the way the go with this method, the semiconductor element, whose analysis of integrated circuits, as well as subsequent manipulation with it much more difficult.

Next, a method of manufacturing such a wiring must be better coordinated with the method of manufacturing transistors and require as little additional technological operations.

This problem is solved by a method according to p. 1 of the claims and by the semiconductor element on p. 12. Other preferred forms of implementation, modifications and aspects of the present invention are given in the dependent claims, the description and the attached drawings.

According to the claimed invention a method of manufacturing a semiconductor element, at least partially held in the wiring substrate, and is provided, at least one passing in the semiconductor substrate and at least one passing on the semiconductor substrate conductive connection. The method according to the invention includes the following steps: a) preparing a semiconductor substrate having at least two areas, and in the first region have the transistors of the first type and the second field - effect transistors of the second type; b) on the semiconductor podlozkou subsequent crossings between passing in the semiconductor substrate and on the semiconductor substrate conductive compounds and/or alloying impurity of the second conductivity type is injected into the second region in the area subsequent crossings between passing in the semiconductor substrate and on the semiconductor substrate conductive connections; g) on the first insulating layer is applied conductive layer; d) through the industrial process is applied to the first mask, in which the first region is almost completely covers mostly only track gates formed by transistors of the first type, and optionally passing on a semiconductor substrate a conductive connection and the second region; (e) in accordance with this first mask conductive layer converts the second insulating layer or removed and at least one alloying impurity of the first conductivity type is introduced into the semiconductor substrate; and (g) through industrial process applied to the second mask, which the second region is almost completely covers mostly only track gates formed by transistors of the second type, and optionally passing on a semiconductor substrate a conductive connection and the first region; C) in accordance with this second mask conductive layer converts the second insulating layer or removed and at least one alloying impurity of the second conductivity type is introduced into the semiconductor substrate, so that due to the dopants introduced in the zone of intersection points and through the first or second masks, briny be conducted in the order specified, in particular, operations b) and C) can also be reversed. With so manufactured semiconductor element according to the invention can be implemented in a low diving under plane shutter, which greatly complicates subsequent analysis of the scheme. The semiconductor element according to the invention can be applied, therefore, in those cases, when it comes to high reliability against external manipulations.

The method according to the invention has, furthermore, the advantage that for the formation of at least two types of transistors, such as p-MOS and n-MOS transistors, and passing the substrate wiring it requires only three Fotolia, whereas traditional manufacturing methods usually require 6 or more films. The method according to the invention obtained through the industrial process masks are used in the relevant field for structuring tracks paddles, and to enter dopant, in order to obtain the area of the source and drain or held in the substrate connection. By saving three films of the process is greatly simplified and accelerated, which ensures cost-effective production. Such integrated circuits Dah.

The method according to the invention is preferably, in particular, if between the first and second regions is provided by the zone (or zones) that are not covered by both masks. Thus, it is guaranteed that in the plane of the conductive layer only really provided connections create a conductive connection between the first and second regions.

Further preferably, if the conductive layer is applied, in particular, oxide-nitride-oxide layer is removed after application of the mask in accordance with masks.

Also preferably, if a conductive layer is polycrystalline silicon layer.

According to one form of the present invention, the polycrystalline silicon layer transform by oxidation in the second insulating layer. Thus, in particular, preferably, if the polycrystalline silicon layer to convert the second insulating layer by removing part of the polycrystalline silicon layer, and the remaining part by oxidation is converted into a layer of silicon oxide.

Further preferably, if the alloying impurity introduced into the semiconductor substrate by implantation and subsequent heat treatment. Thus for an input dopant can the temperture of the process.

In addition, preferably, if the first and the second region are each zone, provided for the contacts of the substrate, the first mask over the areas in the second region provided for the contacts of the substrate, holes and covers the area in the first area, provided for the contacts of the substrate, and if the second mask over the areas in the first area provided for the contacts of the substrate, holes and covers the area in the second area, provided for the contacts of the substrate.

Further preferably, if the selected areas, which should be formed by the transistors is provided by an insulating zone, in particular thick oxide isolation or miloslava isolation, which limit the transistors.

The invention is explained in more detail below using the drawing, which depict:
- Fig.1-5: schematic cross-section of the various stages of the method according to the invention;
- Fig.6 and 7: types above is shown in Fig.4 in cross section the structure.

In Fig.1 shows a semiconductor substrate 1 is prepared as a starting point for the method according to the invention. In the semiconductor substrate 1 of the p-type pocket 2 is provided n-type. The length of the pocket 2 of n-type is as conducting connection. Next, the semiconductor substrate 1 of the p-type pocket 4 is provided to p-type. The length of the pocket 4 of the p-type also determines, therefore, one of the areas 5, which later takes the diffusion of a donor impurity as a conducting connection.

Additionally, there are thick oxide insulation 6, which horizontally isolated from each other separate connections. To improve insulation under thick oxide insulation can be ion-implanted through the protective layer of the oxide region 7.

This pre-structured semiconductor substrate 1 was applied oxide layer 8 as an insulating layer between the thick oxide insulation. This oxide layer 8 is lower than in other areas of the semiconductor substrate 1 as a gate oxide for forming transistors (not shown). The resulting structure is shown in Fig.1.

Through industrial process in the pocket 2 of n-type semiconductor substrate 1 are implanted atoms 33 boron (energy implantation of 20 Kev, implantation dose 21014cm-2). While the boron atoms are implanted into the zone 23, which later forms vodnikova substrate conductive connection 14 (Fig.6).

Through the next industrial process in pocket 4 of the p-type semiconductor substrate 1 are implanted atoms 35 phosphorus (energy implantation of 20 Kev, implantation dose 21014cm-2). When the phosphorus atoms are implanted in an area of 25, which later forms the intersection between passing in the semiconductor substrate a conductive connection 24' and passing on the semiconductor substrate a conductive connection 18 (Fig.6). The resulting situation is shown in Fig.2.

Then by the method of chemical deposition from the gas phase on the oxide layer 8 and the thick oxide isolation 6 is applied polycrystalline silicon layer 10 as a conductive layer. This polycrystalline silicon layer 10 is, for example, a thickness of 150 nm and doping of donor impurity 21020cm-3). This doping may occur in situ during deposition due to subsequent implantation or the so-called POCL coverage. Followed by the deposition of oxide-nitride-oxide layer on the polycrystalline silicon layer 10, and oxide-nitride-oxide layer is then due to oxidation occurs oxide-nitride-oxide layer 11 in the quality of erwou the mask 12. The first mask 12 covers above the pocket 2 of p-type, basically, only the connection 14, while the pocket 4 of the p-type almost completely covered.

Above zone 19 (Fig.4) between the two pockets 2,4 mask 12 is slightly moved back, so that this zone is open.

In accordance with this first mask 12 open part of the oxide-nitride-oxide layer 11 are removed by etching. Further in accordance with this first mask 12 public portion of the polycrystalline silicon layer 10 is removed to a predetermined thickness. Finally, in accordance with the first mask 12 in the semiconductor substrate 1 are implanted atoms 15 boron and thick oxide isolation 6 (energy implantation of 20 Kev, implantation dose 21015cm-2). Because implanted in the thick oxide isolation 6 atoms of boron in the future do not play a role, in Fig.3 shows only the boron atoms implanted in the semiconductor substrate 1.

The mask 12 can be removed after the structure of the protective layer 11 or delete after the structuring of the conductive layer 10, however, it is preferable to leave the mask 12 until, until you have completed the implantation of the dopant. Thus, it is possible to use h substrate.

Upon completion of the implantation of boron, the first mask 12 is removed and through the next industrial process applied to the second mask 17. After this, the second mask 17 covers above the pocket 4 of the p-type connections only 18, while the pocket 2 of n-type is almost completely covered.

Above zone 19 (Fig.4) between the two pockets 2,4 mask 17 is slightly shifted ago, so this area is open.

In accordance with this second mask 17 is still available, now exposed part of the oxide-nitride-oxide layer 11 are removed by etching. Further in accordance with this second mask 17 is it not yet available, the public portion of the polycrystalline silicon layer 10 is removed to a predetermined thickness. This leads, including that in the area 19 between the first and second regions not covered by both masks, the polycrystalline silicon layer 10 is completely removed.

Finally, in accordance with this second mask 17 in the semiconductor substrate 1 are implanted atoms 20 phosphorus and/or arsenic and thick oxide isolation 6 (phosphorus: energy implantation 130 Kev, implantation dose 11014cm-2; arsenic:
energy implantation of 150 Kev, implantation dose 21015cm-2). Because implantaten only implanted in the semiconductor substrate 1, the dopant atoms.

Upon completion of the implantation of phosphorus or arsenic second mask 17 is removed, and carry out the oxidation of the remaining and not protected by a protective layer 11 of the polycrystalline silicon layer 10, resulting oxide layer 22 as an insulating layer. Covered with oxide-nitride-oxide layer 11 connection 14,18 not oxidized. Oxidation of the polycrystalline silicon layer 10 is, for example, in a humid atmosphere at a temperature of about 950oWith over 80 minutes This elevated temperature is used simultaneously to enter in the semiconductor substrate dopants boron or phosphorus/arsenic, in order to form, thus passing in the semiconductor substrate conductive connection 24,24'.

The concentration of dopants is selected so that passing in the semiconductor substrate conductive connection 24,24' have in zones 23,25 intersections 32,34 sufficient conductivity. This prevents the formation of transistors at intersections 32,34. The resulting situation is shown in Fig.5.

According to another form of execution of the method according to the invention, the polycrystalline silicon layer 10 is removed during the etching not only Satania remaining polycrystalline silicon is no longer necessary. In this case, carry out only a relatively short heat treatment to enter the dopants in the semiconductor substrate (950oC for about 20 min).

In Fig. 6 depicts a top view shown in Fig.5 in cross section the structure. It is shown in Fig.5 structure occurs due to the section along the line a - a' in Fig.6 and subsequent folding.

We see that the tracks 14,18 paddles are held on the semiconductor substrate 1 a conducting connection, which connects, for example, the gate electrodes of the two transistors (not shown). On the contrary, the diffusion region 24,24', which at a later stage of the method are in contact through the contact holes 30, are conducting connection, passing in the semiconductor substrate 1.

If someone will attempt to analyze so manufactured integrated circuit, depicted in Fig.6 when viewed from above, the layout will seem to him the location of two CMOS transistors. The only difference lies in the concentration of dopant in the areas 23,25. This concentration of dopant can be installed later, but only with very high costs. Therefore the subsequent is but difficult.

In Fig.7 when the top view depicts the device according to the invention, in which the diffusion region 24,24' lie on the same line. Line a - a' here, in contrast to Fig.6 is stretched. On the contrary, track 14,18 paddles are angled to each other.

In conclusion, carry out the deposition of an additional insulating layer, for example, from borophosphosilicate glass and an additional conductive layer, for example, of aluminum for the formation of the first layer of metallization. Depending on the complexity of our scheme can be applied to additional insulating layers and additional conductive layers. For simple one layer of metallization, as a rule, however, enough so that it can be precipitated one passivating layer.


Claims

1. A method of manufacturing a semiconductor element passes at least partially in the wiring substrate, and is provided, at least one passing in the semiconductor substrate (1) a conducting connection (24, 24') and at least one passing on the semiconductor substrate (1) a conducting connection (14, 18), comprising the following operations: a) prepare poluprovodnikov type and a second region (5) of the first conductivity type to the transistors of the second type, b) on the semiconductor substrate (1) put the first insulating layer (8), C) doping the impurity of the first conductivity type is introduced into the first region (3) in the zone of subsequent intersections between passing in the semiconductor substrate a conductive connection (24, 24') and passing on the semiconductor substrate a conductive connection (14) and/or alloying impurity of the second conductivity type is injected into the second region (5) in the zone of subsequent intersections between passing in the semiconductor substrate a conductive connection (24, 24') and passing on the semiconductor substrate a conductive connection (18), g) on the first insulating layer (8) is applied conductive layer (10), d) by industrial process put the first mask (12), which almost completely covers the second area (5), and in the first region (3) covers only track gates formed by transistors of the first type, as well as passing on a semiconductor substrate (1) a conducting connection (14), (e) the first mask (12) is used to convert the conductive layer (10) in the second insulating layer (22) or to remove the conductive layer (10)and also to enter in the semiconductor substrate (1) one dopant (15) of the first conductivity type to perform khnichenkova process is applied to the second mask (17), that covers the first region (3), and the second region (5) covers only track gates formed by transistors of the second type, as well as passing on a semiconductor substrate a conductive connection (18), C) this second mask (17) is used to convert the conductive layer (10) in the second insulating layer (22) or to remove the conductive layer (10), and also to enter in the semiconductor substrate (1) one dopant (20) of the second conductivity type to perform one of the passes in the semiconductor substrate compounds (24, 24') in the second region (5), and by increasing the temperature by doping impurities introduced in the crossing area and using the first or second mask, to form passing in the semiconductor substrate (1) a conducting connection (24, 24').

2. The method according to p. 1, characterized in that between the first (3) and second (5) areas provided by area (19) not covered by both masks (12, 17).

3. The method according to one of the p. 1 or 2, characterized in that the conductive layer (10) is applied a protective layer (11), which is removed after application of the mask (masks) (12, 17) in accordance with a mask (masks) (12, 17).

4. The method according to p. 3, characterized in that the protective layer (11) is posledovatelno RoboTask layer (10) is a polycrystalline silicon layer.

6. The method according to p. 5, characterized in that the polycrystalline silicon layer (10) transform due to oxidation in the second insulating layer (22).

7. The method according to p. 5, characterized in that the polycrystalline silicon layer (10) converts the second insulating layer (22) due to the fact that part of the polycrystalline silicon layer (10) is removed, and the remaining part of the transform due to oxidation in the layer (22) of silicon oxide.

8. The method according to one of paragraphs.1-7, characterized in that the doping impurity (15, 20) is introduced into the semiconductor substrate (1) through implantation and subsequent heat treatment.

9. The method according to p. 8, characterized in that the doping impurity (15, 20) is introduced into the semiconductor substrate (1) due to the high temperature oxidation of polycrystalline silicon.

10. The method according to one of paragraphs. 1-9, characterized in that the first (3) and second (5) areas have each zone (32, 34), provided for the contacts of the substrate, the first mask (12) has over zones (32) in the second region (5) provided for the contacts of the substrate, holes and covers areas (34) in the first region (3), provided for the contacts of the substrate, while the second mask (17) has over zones (34) in the first region (3), provided for contacts p the persons in one of the paragraphs.1-10, characterized in that in selected areas (3, 5), which must be formed by the transistors is provided by an insulating zone (6), in particular thick oxide isolation silicon oxide or miloslava isolation, which limit the transistors.

12. Semiconductor element passes at least partially, in the wiring substrate, characterized in that it is manufactured by a method according to one of paragraphs.1-11.

 

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