The memory cell

 

The invention relates to the field of pulse technique and can be used in computer equipment and control systems. The technical result is to increase the amount of recorded information. The memory cell includes a switch, a serial RC circuit, three multiplexer, asynchronous trigger, pulse counter, two triggers, the element OR NOT and shaper short pulses. 2 Il.

The invention relates to the field of pulse technique and can be used in computer equipment and control systems.

A known memory location (see and. C. the USSR 1706362 from 02.04.90, MKI H 03 K 3/037, "Trigger device", Eryomin A. N., Shishkin, I., publ. 28.08.97, bull. 24), containing D-trigger, the first, second and third elements OR NOT, the element AND-NOT bi-directional key, a resistor and a capacitor. One of the conclusions of the resistor across the capacitor is connected to the shared bus. The first and second inputs of the first element OR NOT connected respectively with the first installation of the input device and the output of the second element OR NOT. The first and second inputs of the second element OR NOT connected respectively with the second installation input devices and direct D-flip-flop. Tectomy inputs respectively of the first and second elements OR NOT. Output bi-directional key is connected to the information input of D-flip-flop and the other output resistor, the input - output of the first element OR NOT, and control input - output element. The first and second inputs of the element AND IS NOT connected respectively with the output of the third element OR NOT, and with additional input devices.

The disadvantage of this memory cell is the small amount of stored data.

A known memory location (see RF patent 2042268 from 28.06.91, MKI H 03 K 23/64, "the Count of pulses in the code gray", Dikarev I. I. Shishkin, I., publ. 20.08.95, bull. 23), containing the digits zero through N-th serial RC circuit on the number of digits, demultiplexer, two switches and each category of asynchronous D-flip-flop and a multiplexer, which contains two bi-directional key and the element OR NOT, the inputs of which are the address inputs of the multiplexer. Each discharge outputs of the bidirectional keys are connected to the input of the trigger and to the corresponding input of the first switch, the output of which is connected to the output of the second switch, the inputs of which are connected with the first conclusions of the respective RC circuits, the latter findings are connected to a common bus. The input of the demultiplexer is connected to the first input bus, the address inputs of the elements OR IS NOT relevant bits the second input of the element OR NOT each discharge is connected with the control input of the first bi-directional key and an entry permit recording of information, and the output connected with the control input of the second bi-directional key, the input of which is connected to the direct output of the flip-flop. Information on the second input bus is changed when the signal on the first input bus. Input the first bi-directional key information is the input of the discharge cell memory.

The memory cell is closest to the technical nature of the claimed device and is taken as a prototype.

The disadvantage of the prototype is the complexity of the device.

The technical challenge is to create a device which is simple circuit implementation.

The memory cell containing the switch, serial N RC-circuits, the first conclusions which are connected to respective inputs of the switch, and the latter findings - with a shared bus, the multiplexer and asynchronous D-flip-flop, an input connected to the output switch and the output of the multiplexer, and the output from its corresponding input, two other input of the multiplexer is connected to the input bus. What is new is the fact that additionally introduced counter pulses, d is th flip-flop with bus read the second input to the S-input of the second trigger and bus entry and exit - with R-input of the counter, With the input connected to the first address input of the multiplexer and the control bus, and the outputs from the respective address inputs of the switch, the output of the high-order bit of the counter is connected to the R-inputs of the triggers, the output of the second trigger is connected with the second address input of the multiplexer, inverted output of the first flip-flop connected to the first input of the element OR NOT, a second input connected to an inverted output of D-flip-flop, and the output from the output bus.

This combination of features allows you to simplify the diagram.

Schematic diagram of the memory cell shown in Fig.1. In Fig.2 shows time diagrams of the specified memory cell.

The memory cell contains 4 digits (zero through three), the input "I", the output "O" of the bus, the bus read "CQ", bus write "Zap", bus "control Panel", the multiplexer 1, the switch 2, the asynchronous D-flip-flop 3, which consists of two inverters, two RS-flip-flop 4, 5, the pulse counter 6, the shaper short pulses 7, the element OR NOT 8, serial RC circuit 9 (9-0. . .9-3), the first conclusions which are connected to respective inputs of the switch 2, and the latter findings - with a shared bus.

The memory cell operates as follows.

When the power supply voltage on all tyres device signals are absent (signal logic "0"), the channels HH multiplexer 1 and switch 2 is open, the input of D-flip-flop 3 is connected to its output, an RC-circuit 9-0 also connected to the input of D-flip-flop, the rest of the RC-circuit is disabled. When applying control pulses (chart 1, Fig.2) the pulse counter 6 (dial information in the memory cell is as follows. On the bus "Zap" signal (chart 5, Fig.2), which establishes a direct output of the trigger 5 in the state of logical "1", this signal is supplied to one input of shaper short pulses, which generates a pulse which is fed to the reset input of the pulse counter. Information from the inputs x2, X3 multiplexer 1 (chart 4, Fig.2) is fed to the input of switch 2. The recording signal is present on the bus "Zap" during the entire write cycle. This is necessary in order to eliminate the effect of interference on the bus "Zap".

Reading of information is performed as follows.

On the bus, "Mid" signal (figure 6, Fig.2), which sets the inverted output of the RS-flip-flop 4 in the state of logical "0", the signal of which is fed to one of the inputs of the element OR NOT, to another input of which receives the signal from the inverted output of D-flip-flop 3, the entrance of which in turn is connected to one of the RC circuit 9, as a result, the output bus of the information written in the memory cell (figure 7, Fig.2). The signal reading is also fed to the second input of the shaper short pulses, which also performs the function of "OR" in the pulse counter 6 is reset to zero when signals recording or the pulse 6.

In order to confirm the feasibility of the claimed memory cell and the positive effect achieved from its use, manufactured and tested laboratory sample performed by the circuit of Fig.1.

As the hardware components of the device selected CMOS series 564. Shaper short pulses made by the scheme (see S. Biryukov A. Digital devices in MOS integrated circuits. - M.: Radio and communication, 1990, - s., S. 58, Fig. 105,b), the entrance of which is connected to the output of the element OR NOT.

The tests have shown the feasibility of the present invention and confirmed its practical value.

Claims

The memory cell containing the switch, serial N RC-circuits, the first conclusions which are connected to respective inputs of the switch, and the latter findings - with a shared bus, the multiplexer and asynchronous D-flip-flop, an input connected to the output of the multiplexer, and the output from its corresponding input, two other input of the multiplexer is connected to the input bus, characterized in that the input pulse counter, two triggers, the element OR NOT and shaper short pulses, the first input connected to the S input of the first trigger and bus read th is connected to the first address input of the multiplexer and the control bus, and the outputs from the respective address inputs of the switch, the output of which is connected to the output of the multiplexer, the output of the high-order bit of the counter is connected to the R-inputs of the triggers, the output of the second trigger is connected with the second address input of the multiplexer, inverted output of the first flip-flop connected to the first input of the element OR NOT, a second input connected to an inverted output of D-flip-flop, and the output from the output bus.

 

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Magnetic materials // 2244971

FIELD: magnetic materials whose axial symmetry is used for imparting magnetic properties to materials.

SUBSTANCE: memory element has nanomagnetic materials whose axial symmetry is chosen to obtain high residual magnetic induction and respective coercive force. This enlarges body of information stored on information media.

EFFECT: enhanced speed of nonvolatile memory integrated circuits for computers of low power requirement.

4 cl, 8 dwg

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