Complementary bipolar transistor structure integrated circuit


H01L27/082 -

 

(57) Abstract:

Usage: microelectronics, complementary bipolar transistor structure integrated circuits. The inventive complementary bipolar transistor structure integrated circuit includes a bipolar n-p-n and p-n-p transistors, made in multilayer semiconductor structure and isolated regions of the dielectric. Guides to the areas of the emitter, base and collector of each transistor connected to corresponding areas and isolated by dielectric layers. The area of the collector p-n-p transistor is separated from the substrate p-type conductivity region of n-type conductivity. Guides to the areas of the emitter n-p-n transistor and the base of p-n-p transistor formed from a layer of polycrystalline silicon of the first level, doped donor impurity, guides to areas of the base n-p-n transistor and the emitter of p-n-p transistor formed from a layer of polycrystalline silicon of the second level, the doped impurity. The field emitters of these transistors are formed by diffusion from the doped polysilicon conductors to these areas. Guides to the areas of the collectors of the transistors are made of metal and attached to the regions of the transistors is determined by the thickness of the dielectric layers, insulating the conductors. The invention provides increased packing density and performance of IP. 2 C.p. f-crystals, 2 Il.

The invention relates to microelectronics, and more specifically to the development of a complementary bipolar transistor structures in the manufacture of integrated circuits.

For the implementation of a number of schematic solutions requires the complementary bipolar transistor structures on a single chip in a single technological cycle. And p-n-p and n-p-n transistors must be of acceptable parameters. Currently, there are a number of technological developments that enable the realization of such structures, but most of them implements a p-n-p transistor in the lateral performance that dramatically affects its characteristics and makes it possible to implement it in the integrated circuit.

Known complementary bipolar transistor structure of the integrated circuit containing bipolar vertical n-p-n and p-n-p transistors, made in multi-layer p-n-p-n structure and isolated areas of dielectric guides to the areas of the emitter, base and collector of each transistor connected to corresponding areas on the bottom of the formed article is fast complementary bipolar transistor structure of the integrated circuit, containing bipolar n-p-n and p-n-p transistors made in a multilayer semiconductor structure on a substrate of p-type conductivity and isolated areas of dielectric guides to the areas of the emitter, base and collector of each transistor connected to corresponding areas and isolated by dielectric layers, and the area of the collector p-n-p transistor is separated from the substrate p-type conductivity region of n-type conductivity [2].

The disadvantages of the known structures can be attributed to a large area occupied by the transistor, the contact regions of the transistors are separated by a considerable interval. Large sizes of the transistors do not allow to achieve a high degree of integration and limit the speed of the integrated circuit, making an integrated circuit critical to the defeat of defects, which reduces the percentage of yield. In addition, the disadvantages of the known structures can be attributed to the impossibility of obtaining a narrow impurity profiles, a significant effect of the use nezamescennych technology area p-n junctions, the length of the process cycle, which ultimately affects the structure parameters.

The technical result of the invention is to decrease the collector resistance which in turn provides increased packing density and performance of IP it also greatly reduces production cycle patterns.

This is achieved by the complementary bipolar transistor structure of the integrated circuit containing bipolar n-p-n and p-n-p transistors made in a multilayer semiconductor structure on a substrate of p-type conductivity and isolated areas of dielectric guides to the areas of the emitter, base and collector of each transistor connected to corresponding areas and isolated by dielectric layers, and the area of the collector p-n-p transistor is separated from the substrate p-type conductivity region of n-type conductivity, guides to the areas of the emitter n-p-n transistor and the base of p-n-p transistor formed from a layer of polycrystalline silicon of the first level, doped donor impurity, guides to areas of the base n-p-n transistor and the emitter of p-n-p transistor formed from a layer of polycrystalline silicon of the second level, doped with an acceptor impurity, the field emitters of these transistors are formed by diffusion from the doped polysilicon conductors to these areas, guides to the areas of the collector of n-p-n and p-n-p transistors are made of metal and attached to sootvetstvuuschey and base and between the conductors to the areas of the base and collector of each transistor in the place of connection of the conductors to the respective areas defined by the thickness of the insulation of the conductors of the dielectric layers. As the acceptor impurity doping layer of polycrystalline silicon can be used Bor, and as a donor impurity doping layer of polycrystalline silicon can be used arsenic. As the metal of the conductors to the areas of the collectors of transistors may be used aluminum.

The concentration of dopant in the layer of polycrystalline silicon is selected from the conditions of forming the conductors of polysilicon, as well as of the conditions of formation of the emitter regions of the transistors.

This design involves the formation of polysilicon conductors to the areas of the emitter and base of both types of transistors layer of doped polycrystalline silicon of the two levels, while the conductors are separated from each other by the corresponding layer of insulating dielectric, which significantly reduces the footprint of the structure. Simultaneous formation of the conductors to the fields of both types of transistors of a single layer of doped polycrystalline silicon allows to obtain complementary bipolar transistor structure without substantially increasing the number of lithographs. In addition, ispolzovaniya transition, to increase the concentration gradient of the impurity, while creating the contact to the emitter.

In Fig. 1 presents transistors offer complementary bipolar transistor structure of the integrated circuit, the incision of Fig.2 - structure, top view.

In a semiconductor structure on a substrate of p-type conductivity 1 formed of n-p-n and p-n-p transistors surrounded by insulating regions 2 of silicon dioxide with protivotarannymi areas 3. The field emitter 4, a base 5 and the collector 6 of the n-p-n transistor formed respectively in the region of n-type conductivity, is additionally formed in the layer of p-type conductivity in the layer of p-type conductivity and a layer of n-type conductivity semiconductor structure. The field emitter 7, a base 8 and the collector 9 p-n-p transistor formed respectively in the region of p-type conductivity formed in the layer of n-type conductivity in the layer of n-type conductivity and a layer of p-type conductivity semiconductor structure. The conductor 10 to the field emitter n-p-n transistor and the conductor 11 to the area of the base p-n-p transistor formed from a layer of polycrystalline silicon of the first level, doped donor impurity. The conductor 12 to the area of the emitter p-n-p transistor and pehlivanova an acceptor impurity. The conductor 14 to the collector region of the n-p-n transistor and the conductor 15 to the collector region of p-n-p transistor formed of metal and attached to corresponding areas on the bottom are formed in the structure of the recesses. Guides to the areas of the emitter, base and collector of the transistors are isolated from different sides of the layer 16 of dielectric material.

To obtain presents complementary bipolar transistor structure of the integrated circuit in a semiconductor substrate of p-type conductivity to form the n+the hidden layer n-p-n transistor and the n-pocket with p+a hidden layer for p-n-p transistor. Mask n-p-n transistor layer of oxide and conduct ion doping of boron for forming the collector region of p-n-p transistor. After forming the collector region of p-n-p transistor conducting ion doping of arsenic for forming the base region of p-n-p transistor, remove oxide from the surface of the n-p-n transistor, mask p-n-p transistor with a layer of photoresist, followed by ion doping with boron, forming a base region of n-p-n transistor. Then form a layer of polycrystalline silicon doped with arsenic, to form a polysilicon conductor to the field emitter n-p-n transistor and to the field Budnikov by drawing on the conductors, covered with a layer of masking oxide, oxide layer and the etched oxide from horizontal surfaces of the structure. Then form the polysilicon conductors to the field base n-p-n transistor and to the emitter of p-n-p transistor layer of polycrystalline silicon of the second level, doped with boron. Form the lateral insulation of the polysilicon conductors conduct heat treatment for forming the emitter regions. Then form the wires to the collector regions of the transistors of aluminum.

Example. Was manufactured device on a silicon substrate of p-type conductivity (concentration of impurities of 1014cm-3), which were sequentially formed local hidden layer of n+-type conductivity (concentration of impurities of 1021cm-3thickness 1.5 μm), low-alloyed region of n-type conductivity (concentration of impurities of 1015cm-3the thickness of 4 μm), which formed a local hidden layer p+-type conductivity (concentration of impurities of 1020cm-3thickness 1.5 μm), and then grown epitaxial film of n-type conductivity (concentration impurity 51015cm-3, thickness 1.0 μm).

Using planar technology was izgotovlenie (concentration of impurities of 1017cm-3under her. Then in Mesa-area p-n-p transistor while masking Mesa region of the n-p-n transistor was formed the collector region of p-type conductivity using ion implantation of boron with subsequent thermal annealing (concentration of impurities of 1016cm-3depth of 1.0 μm). Then in the same meso-region was formed area of the base p-n-p transistor of n-type conductivity using ion implantation of arsenic, followed by thermal annealing at a temperature of 950oC (the concentration of the impurities of 1017cm-3depth of 0.3 μm).

Then in the Mesa region of the n-p-n transistor, when masking Mesa-area p-n-p transistor has been formed, the base region of p-type conductivity using ion implantation of boron with subsequent thermal annealing (concentration of impurities of 1017cm-3depth of 0.4 μm). After that, the surface was conformally deposited layer of polysilicon with a thickness of 0.2 μm and implantation of this layer with arsenic to a concentration of impurities of 1021cm-3. After vapor deposition of low temperature oxide layer of silicon, conducting photolithography and anisotropic plasma etching with a mask of the photoresist Ocidente p-n-p bipolar transistors. After removal of the photoresist was performed conformal deposition of a layer of oxide of silicon with a thickness of 0.3 μm with subsequent plasma-chemical anisotropic etching of this layer. Resulting in the layer of silicon oxide is removed from all horizontal and remains on vertical surfaces of the structure, forming the lateral dielectric isolation polysilicon contacts to the areas of the emitter and the base, and the polysilicon wiring of the first level.

Similarly wiring are formed of the second level polysilicon contacts to the base region of the n-p-n and to the emitter p-n-p transistors. In this case, the second layer of polysilicon was legionalla boron ions to a concentration of impurities of 1019cm-3and after chemical etching of the layers of oxide and polysilicon were performed additional anisotropic etching of silicon to dissection of the area of the base p-type to n-p-n transistor and n-type to n-p-n transistor with a depth of not less than 0.2 μm in an epitaxial film of n-type conductivity for n-p-n transistor and a p-type and p-n-p transistor.

After that was formed lateral dielectric isolation polysilicon contacts to the base region of p-n-p emitter n-p-n transistors and polysilicon responsestream. Using sequential masking transistors were ponteginori phosphorus collector contact n-p-n transistor and boron collector contact p-n-p transistor.

The final formation of the diffusion regions of the passive base emitter n-p-n and p-n-p transistors is carried out by diffusion of an impurity from the respective polysilicon contacts in the final thermal annealing. Then run the contact window to the polysilicon conductors and aluminum wiring, including contacts to the collectors of the bipolar transistors.

1. Complementary bipolar transistor structure of the integrated circuit containing bipolar n - p - n and p - n - p transistors made in a multilayer semiconductor structure on a substrate of p-type conductivity and isolated areas of dielectric guides to the areas of the emitter, base and collector of each transistor connected to corresponding areas and isolated by dielectric layers, and the area of the collector p - n - p transistor is separated from the substrate p-type conductivity region of n-type conductivity, characterized in that the guide to the areas of the emitter n - p - n transistor and the base of p - n - p transistor is Nicky to the areas of the base n - p - n transistor and the emitter of p - n - p transistor formed from a layer of polycrystalline silicon of the second level, doped with an acceptor impurity, the field emitters of these transistors are formed by diffusion from the doped polysilicon conductors to these areas, guides to areas of reservoirs n - p - n and p - n - p transistors are made of metal and attached to corresponding areas on the bottom are formed in the structure of the recesses, thus the distance between the conductors to the areas of the emitter and base and between the conductors to the areas of the base and collector of each transistor in the place of connection of the conductors to the respective areas defined by the thickness of the insulation of the conductors of the layers of dielectric.

2. Structure on p. 1, characterized in that the doped donor impurity layer of polycrystalline silicon of the first level used arsenic, and as an acceptor impurity doping layer of polycrystalline silicon of the second level used Bor.

3. Structure on PP.1 and 2, characterized in that the metal of the conductors to the areas of the collectors of the transistors used aluminum.

 

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