A method of manufacturing the state tobacco monopoly-memory cell, the memory cell matrix and the drive based on it

 

(57) Abstract:

The invention relates to microelectronics and can be used to create a program memory with high information density on the basis of the state tobacco monopoly-effect transistors, in particular, reprogrammable by the injection of hot charge carriers. The essence of the invention as a memory cell used MOS transistor containing side gate spacer elements. Dielectric under side of the shutter is the structure of SiO2-Si3N4-SiO2. Due to the small width of the spacer region of the injection of hot holes in the gate insulator covers the area of capture of negative information charge. Due to this increased efficiency erase and cyclostationary memory cells. Based on the proposed state tobacco monopoly-memory cell designed drive with individual samples in all modes, protected from changes in the logical state of the unselected memory cells when writing and erasing information. 3 S. and 9 C.p. f-crystals, 1 tab., 11 Il.

The invention relates to non-volatile electrically reprogramming storage devices (program memory) with high information density, including radiation-resistant Elo structures of memory cells and drives program memory, as well as methods of their production [1-3]. Among them currently one of the most promising devices based on the memory cells, programmable hot electrons and holes. In particular, there is a method of manufacturing the state tobacco monopoly-cell non-volatile memory [4], according to which the silicon substrate is grown multilayer storage dielectric film of SiO2-Si3N4-SiO2(OHO-structure) and the adjacent layer of gate dielectric SiO2for stable MIS-structures, forming isolated from the substrate managing polysilicon gate so that it covers the interface, called the dielectric films, and then in the substrate to create the source-drains of the diffusion region, combined with the polysilicon gate.

Made in this way, the memory cell has the following serious drawbacks. For complete removal of the negative charge of the storage dielectric film when erasing information and obtain tikoustoychivyh of memory), it is necessary that the area of the injection of hot holes overlaps the region of localization of the negative charge. Otherwise, the storage layer directorytree section of the channel is determined photolithographically, and its original topological value must exceed the error defined by the possibilities of technological equipment (0.2 to 0.4 μm). The size of the same area of the injection of hot holes is one or a few tenths of a micron and, as a rule, is lower region of the injection of hot electrons. Thus, this method does not produce cyclostyle memory cell.

Known design memory [5], based on a MOS transistor on a semiconductor substrate containing a source-stock diffusion region, between which is the area of channel MOS transistor, a control gate located over a channel region of a MOS-transistor, the first gate dielectric, an insulating region channel MOS transistor to the control gate, side gate, made as polysilicon spacer at the side wall of the control gate located over a channel region of a MOS-transistor, the second gate dielectric, an insulating region channel MOS transistor on the side of the shutter. In this memory cell gate spacer elements is variable and is used to store information charge. As the gate di is Chen is the memory cell has poor radiation resistance. Additionally, there is no possibility of a direct control potential of the spacer elements of the shutter, which limits the functionality of the cell and drive.

A known design matrix of drives that can be used for the state tobacco monopoly-memory cells, reprogramming the injection of hot charge carriers [4,6]. In particular, the matrix drive [6] performed based on the memory field-effect transistors with side gates, made in the form polysilicon spacers along the side boundaries of the control gates, and contains polysilicon address bus, directed along the rows of the matrix metal stock and ishikawae bit bus, directed along the columns of the matrix, diffusion of stock area, located by the side gate and electrically connected to the metal bit of stock tires, diffusion ishikawae area, interconnected and electrically connected with the metal stokovye bit tires performed periodically between the metal bit tires.

The disadvantage of the prototype in the case of using it as nakapatay and erasing of information is accompanied by partial loss of negative information charge in the unselected memory cells with a high value of threshold voltage, with common stock bit bus is selected. This is caused by the generation of hot holes in back-biased stock transitions, which takes place when the voltage on the drain is less than the breakdown voltage.

The present invention is directed to creating tikoustoychivyh the state tobacco monopoly-cell non-volatile memory, reprogrammable by the injection of hot charge carriers, as well as matrix drive on the basis of such a memory cell that is protected from erasing information in an unselected cells in reprogramming the memory.

In respect of the method of manufacturing the memory cells of obtaining the desired result is achieved by the fact that, initially, on the surface of a semiconductor substrate sequentially grown gate dielectric film and the first conductive layer of polysilicon, of which lithographically formed managing polysilicon gate and combined with it the layer of gate dielectric, and then sequentially grown multilayer storage dielectric film and the second conductive layer of polysilicon, of which by using anisotropic dry etching to form spacers along the side boundaries of the polysilicon control gate.

In some cases, to simplify the control cell after forming spacers along both side boundaries of the polysilicon control gate of one of the spacers is removed, closing another spacer mask of photoresist, and then form the source-drains of the diffusion region. But with a loss of one bit of information per cell.

In other variations of the method after forming a polysilicon control gate and combined with it the layer of gate dielectric in a semiconductor substrate to create one of the source-drains of the diffusion regions, for example istokov. In this case, the dielectric storage medium located, for example, from the source, does not cover the channel of the memory cell and does not affect its threshold voltage.

The positive effect from the use of this type of method is that in this case there is no need for a delete operation one and the planned result is achieved by the second gate dielectric is carried out in a multilayer structure comprising a layer of dielectric medium, and the side gate is connected to the output of an external source of control. In particular, the second gate dielectric can be made with OHO-structure, and the side gate is electrically connected with the control gate.

The technical result from the use of the proposed design is to expand the scope of memory cells and to increase design freedom in designing the memory.

In the design matrix drive obtaining the desired result is achieved by the fact that the side gates in the United spacer elements tires, directed along the rows of the matrix, and the gate dielectric, an insulating spacer elements tires from areas of the channels of the memory MOS transistor, includes a layer of dielectric medium, in particular, made with OHO-structure.

Spacer elements tires can be electrically connected with the corresponding polysilicon address tyres or connected to the findings on external sources of control.

The technical result from the connection of the spacer elements tires to external sources and in reprogramming. It will be demonstrated below in the description of the control method of the drive.

When connecting to external sources of control spacer elements are just the drive or its fragments can be joined together, in particular, by using periodically made of polysilicon or metal tyres, directed along the columns of the matrix.

In this case, the technical result is to simplify management of storage and the reduction of the area of the storage device in the integrated design, although losing the possibility of individual sample memory cells in the erase mode information.

In Fig. 1 schematically shows a memory cell, a method of manufacturing which is taken as a prototype, where 1 is a semiconductor substrate, 2 - IT-structure, 3 - adjacent layer of SiO2, 4 - managing polysilicon gate, 5 - channel, 6 and 7, respectively, of stock and Itokawa diffusion region.

In Fig. 2-6 presents the sequence of manufacturing the memory cell and three modifications of its structure, where the 8 - layered storage dielectric film 9 and the second conductive layer of polysilicon, 10 and 11 - spacer elements closures, rasstroena drive used as a prototype, where 12 - polysilicon address bus 13 - floating spacer elements closures 14 and 15, respectively, of stock and ishikawae metal bit bus, 16 - pin open, 17 - the border of the active region 18 and 19, respectively, of stock and ishikawae diffusion region.

In Fig. 8 and 9 shows fragments of two varieties of topological construction of the proposed drive, where 20 - spacer elements bus 21 bus from the second layer of polysilicon, the spacer elements uniting tires.

In Fig. 10 and 11 illustrate the fragments of an electrical circuit of the two varieties offer the drive, where VgVcVdand Vsaccordingly, the voltage on the bolt, spacer elements, stock and stokovoj tires.

The table shows the values of the voltages supplied to the various modes on the tires of the proposed drive.

Consider the sequence of technological operations in the proposed method of manufacturing a memory cell.

On the surface of the semiconductor substrate 1 (Fig. 2), in particular, P-type sequentially growing a layer of gate dielectric, such as thermal film SiO2the thickness 35 of the second structure 3-4. After that grown multilayer dielectric film 8 (Fig. 3) and a second conductive polysilicon layer 9 with a thickness of 50 nm. Multilayer dielectric film may be made by thermal oxidation of silicon to a thickness of 6 nm, the subsequent pyrolytic deposition of a layer of Si3N4the thickness of 25 nm, and further growing the layer of SiO2by thermal oxidation of Si3N4water vapor at an elevated pressure to a thickness of 10 nm. Using dry anisotropic etching of the second polysilicon layer to form the spacers 10 and 11 (Fig. 4) along both side boundaries of the polysilicon gate 4. Then, in the substrate by ion doping and thermal activation of the impurity creates a diffusion of stock and stockbuy region 6 and 7, combined with the limits of spacer elements tires.

In Fig. 5 shows a memory cell made in accordance with another modification of the way. This construction can be obtained if, after a dry anisotropic etching of the spacer elements, the shutter 11 is removed by etching, after closing the other spacer elements shutter 10 by the photoresist. To protect the control gate 4 when the etched spacer immediately after deposition of the first conductive loyalty one of the spacers. As the protective film, you can use a layer of SiO2or Si3N4.

In Fig. 6 shows a memory cell made in accordance with the third kind of way. To obtain this structure after formation of the composite structure 3-4 one of the boundaries of the polysilicon gate covered with a photoresist and type impurity by ion doping sovmesheno with opposite sides of the shutter.

In Fig.8 and 9 shows fragments of two varieties of topological construction of the proposed drive, in which the spacer elements bus connected to external sources of control, and Fig. 8, each spacer elements bus connected to an individual source, and Fig. 9 all of the spacer elements of the bus is shown a fragment of a memory interconnected by means of bus from the second polysilicon. The circuit diagram shown in Fig. 10 and 11 correspond to fragments of the drive of Fig. 8 and 9. Association spacer elements tires, and connecting each spacer elements bus to an external source can be done if before performing anisotropic dry etching of the second polysilicon layer to close the mask of the photoresist region commuting tires. How ishodovati. This can be used any of the proposed modifications of the method of manufacturing the cell.

Let us consider possible ways to manage the proposed drive (Fig.8, 10, table). The record is feeding on stock tire selected memory cell voltage programming Vpfor example, 8 In, and the bolt and spacer elements bus - voltage Vppfor example, the 12th Century To protect from Erasure information charge in the unselected memory cells with a high value of threshold voltage with common stock bus is selected, all of the spacer elements tires drive serves a constant positive voltage, for example, VRR.

In erase mode spacer elements on the bus selected memory cell serves a negative voltage Vgefor example, 10 V, and the stock tire through the high-ohmic resistor is a positive voltage Vdeexceeding the breakdown voltage of stock transition at a given value of voltage at bus spacer elements. All other spacer elements tyres to protect the unselected memory cells from erasing information charge serves a positive voltage Vcefor example, the 10th Century Bus control gates of all memory reset.

In ishape reading stock tire selected memory cells are reset to zero. Thus there are two options for applying voltage to spacer elements tires. In accordance with option a all of them are under the constant voltage Vccequal to, for example, 5 C. In accordance with option b, the voltage at each bus spacer elements is equal to the voltage on the corresponding gate bus.

Ways to control the drive with the joint spacer elements tires (Fig. 9, 11) similar to the above, in particular the methods of writing and reading (option a) fully coincide with them. The difference has to erase mode, when a negative voltage Vgeserved simultaneously on several joint spacer elements tires. Therefore, the erasing of information occurs simultaneously in several cells connected to the selected stock bit bus. As indicated above, the Association spacer elements tires saves memory area, because it reduces the number of interconnects and elements of the decoder. However, it lost the possibility of individual sample memory cells during erasing of information.

1. A method of manufacturing the state tobacco monopoly-cell non-volatile memory, including growing on a silicon substrate in a multilayer storage dielectric film of SiO2Si3N4SiOthe e isolated from the substrate polysilicon control gate and the creation of the substrate, the source-drains of the diffusion regions, wherein the first surface of the semiconductor substrate sequentially grown gate dielectric film and the first conductive layer of polysilicon, of which lithographically formed managing polysilicon gate and combined with it the layer of gate dielectric, and then sequentially grown multilayer storage dielectric film and the second conductive layer of polysilicon, of which by using anisotropic dry etching to form spacers along the side boundaries of the polysilicon control gate.

2. The method according to p. 1, characterized in that after forming spacers along both side boundaries of the polysilicon control gate of one of the spacers is removed, closing another spacer mask of photoresist, and then form the source-drains of the diffusion region.

3. The method according to p. 1, characterized in that after forming a polysilicon control gate and combined with it the layer of gate dielectric in a semiconductor substrate to create one of the source-drains of the diffusion regions, for example istokov.

4. The non-volatile memory cell based on a MOS transistor on poluprovodnikov transistor, a control gate located over a channel region of a MOS-transistor, the first gate dielectric, an insulating region channel MOS transistor to the control gate, side gate, made as polysilicon spacer at the side wall of the control gate located over a channel region of a MOS-transistor, the second gate dielectric, an insulating region channel MOS transistor on the side of the shutter, wherein the second gate dielectric is made in the form of a multilayer structure comprising a layer of dielectric medium, and the side gate is connected to the output of an external source of control.

5. Cell under item 4, wherein the second gate dielectric is made with the structure of SiO2Si3N4SiO2.

6. The cell on the PP.4 and 5, wherein the side gate is electrically connected with the control gate.

7. Matrix drive is performed based on the memory field-effect transistors with side gates, made in the form polysilicon spacers along the side boundaries of the control gates, and containing polysilicon address bus, directed along the rows of the matrix metal stock and the side of the side gates and electrically connected to the metal bit of stock tires, diffusion ishikawae area, interconnected and electrically connected with the metal stokovye bit tires performed periodically between the metal bit of stock tires, characterized in that the side gates in the United spacer elements tires, directed along the rows of the matrix, and the gate dielectric, an insulating spacer elements tires from areas of the channels of the memory MOS transistor, includes a layer of dielectric medium.

8. The drive p. 7, wherein the gate dielectric, an insulating spacer elements tires from areas of the memory channels of field-effect transistors made with the structure of SiO2Si3N4SiO2.

9. The drive PP.7 and 8, characterized in that the spacer elements of the bus connected to the output pins on external sources of control.

10. The drive p. 9, characterized in that the spacer elements are just the drive or its fragments joined together.

11. The drive p. 10, characterized in that the spacer elements tyres are United among themselves by means of periodically made of polysilicon or metal tyres, directed along the columns of the matrix.

12. The drive PP.7 and 8, the balance of the us.

 

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