(H01L21/8238)

H   Electricity(227141)
H01   Basic electric elements(70435)
H01L21/8238              (15)

ethod for manufacturing high-temperature cmos soi integrated circuits // 2643938
FIELD: manufacturing technology.SUBSTANCE: invention relates to manufacturing semiconductor devices and super-large integrated circuits based on a silicon substrate using a hidden insolator (SOI), intended for using in medias with a maximum temperature of up to 250C. Summary of the invention: a method for manufacturing high-temperature CMOS SOI integrated circuits, comprising steps of forming regions of fine slit insulation STI, ion implantation in the pocket area of n- and p-channel MOS transistors, forming a layer of a gate isolator, depositing a layer of polycrystalline silicon, and forming shutters of MOS transistors, ion implantation in the area of drainage and source of MOS transistors, forming contact windows to the active areas and forming a metallization system, characterized be the fact that in ion implantation in a drain region and source region of MOS transistors of n-type, the dose of arsenic ions is from 21015 to 31015 cm-2, the beam energy is from 63 to 77 keV, and for drain source regions of MOS-transistors of n-type, the dose of boron ions is from 2.81015 to 4.21015 cm-2, the beam energy is from 6 to 8 keV.EFFECT: invention provides increased stability of integrated circuits to high temperatures.4 cl, 19 dwg, 2 tbl

ethod to produce local low-resistance areas of titanium silicide in integrated circuits // 2474919
FIELD: electricity.SUBSTANCE: invention relates to the technology of making integrated circuits on the basis of complementary transistors with the structure of metal - oxide - semiconductor (CMOS IC). The method to produce local low-resistance areas of titanium silicide in integrated circuits consists in generation of active and passive elements of CMOS IC on the basis of areas of n and p type of conductivity in a silicon substrate and a layer of polycrystalline silicon, deposition of a blocking layer, formation of a photoresistive mask, etching of the blocking layer, removal of the photoresistive mask, cleaning of the silicon surface, application of the titanium layer onto the surface of silicon and the blocking layer, annealing of the titanium layer in nitrogen, removal of titanium, which did not react with silicon, and additional annealing in nitrogen. The blocking layer is a film of titanium nitride with thickness of 5-20 nm, produced by means of physical spraying of a titanium target in nitrogen atmosphere, and the blocking layer is removed in process of removal of titanium, which did not react with silicon.EFFECT: preservation of electrophysical and structural parameters of active and passive elements in integrated circuits on the basis of complementary transistors with a structure of metal - oxide - semiconductor when generating titanium silicide.5 dwg, 1 tbl

Radiation-resistant lsic manufacturing method // 2434312
FIELD: electricity.SUBSTANCE: radiation-resistant LSIC (large-scale integrated circuit) manufacturing method involves creation on initial substrate of field silicon oxide and active areas of transistors, channel stoppers, gate silicon oxide, polysilicon areas of gates of transistors and interconnections, masks for alloying with n- and p-type impurities of channel active stoppers and active areas of transistors, interlayer insulation, contact windows and metal coating of LSIC. During creation of active areas between channels, drains, sources of n-type transistors and p-type channel stoppers there formed are additional buffer channel sections, and gate silicon oxide is created after field silicon oxide is formed. During formation of transistor gates there created are additional polysilicon gate channel stoppers fully overlapping buffer channel sections of active areas. Mask for alloying active n-type areas partially opens field areas and additional polysilicon gate areas in the sections adjacent to channels of n-type transistors. Mask for alloying active p-type areas partially opens additional polysilicon gate areas in the sections adjacent to p-type channel stoppers.EFFECT: improving integration degree and simplifying the method.13 dwg

ethod of field cmos transistor formation using dielectrics based on metal oxides with high inductive capacity rate and metal gates, and structure of field cmos transistor // 2393587
FIELD: electricity.SUBSTANCE: method of field CMOS transistor formation involves precipitation of 1-10 nm thick dielectric layer with high inductive capacity rate on semiconductor substrate and application of 0.15-0.41 nm thick antimony (Sb) layer onto the dielectric layer. Metal gate is made of nickel silicide (NiSi) of 300-3000 nm thickness. Semiconductor substrate can be made of silicon (Si) with 0.1-1 nm thick SiO2 sublayer on it. Also invention claims structure manufactured by the described method.EFFECT: control of field n-type transistor switching voltage, reduction of switching voltage of field n-type transistor with switching voltage stability increasing.14 cl, 3 dwg, 1 ex

ethod of field cmos transistor formation using dielectrics based on metal oxides with high inductive capacity rate and metal gates (versions) // 2393586
FIELD: electricity.SUBSTANCE: method of field CMOS transistor formation using dielectrics based on metal oxides with high inductive capacity and metal gates involves precipitation of dielectric layer with high inductive capacity rate on semiconductor substrate, application of insulation layer onto the dielectric layer and precipitation of metal gate. Surface of precipitated dielectric layer with high inductive capacity rate is annealed in vacuum at 500-800C for 3-10 minutes under residual gas pressure under 10-5 mbar and further cooled down in vacuum.EFFECT: control of switching voltage of field n-type and p-type transistor, reduction of switching voltage of field n-type and p-type transistor with switching voltage stability increased.21 cl, 1 dwg, 1 tbl, 1 ex

ethod of cmos transistors manufacturing with raised electrodes // 2329566
FIELD: electrical engineering.SUBSTANCE: in method of CMOS transistors manufacturing with raised electrodes after opening of windows for drain-source regions and formation of separating dielectric on walls of windows, amorphous silicon is formed on windows walls, single-crystal electrodes in drain-source windows are formed by method of hydride epitaxy, as a result of which in windows that are opened to single-crystal silicon, mono-silicon is growing, and above amorphous silicon - polycrystalline silicon, polycrystalline silicon is removed by chemical-mechanical polishing and selective etching of dielectric that is installed above locking and isolating regions is carried out. Single-crystal electrodes of drain-source regions reduce series resistance of transistor, which increases its fast-action.EFFECT: increase of proper items production by prevention of high leakage currents of p-n transitions or short circuit of gate - (drain-source regions), base - (drain-source regions).3 cl, 8 dwg
ethod for enhancing radiation resistance of cmos circuit components on soi substrate // 2320049
FIELD: microelectronics.SUBSTANCE: proposed method for enhancing radiation resistance of CMOS circuit components on SOI substrate includes development of work and insulation regions of circuit on SOI substrate, doping of silicon work regions by ionic implantation of boron, implantation of silicon-hidden oxide interface with fluoride ions at dose rate of 1012 to 1014 ion/cm2, chemical cleaning of surface, formation of gate insulator, formation of gates, doping and annealing of drain-source regions, and metal deposition.EFFECT: enhanced reliability of complementary metal-oxide-semiconductor circuits on silicon-on-insulator substrate, facilitated manufacture.1 cl, 2 dwg

is ic manufacturing process // 2308119
FIELD: integrated microelectronics.SUBSTANCE: proposed MIS IC manufacturing process includes organization of pocket regions on semiconductor silicon wafer, formation of gate insulator, field-effect gate electrodes, and mask, doping of gates, sources, and guard regions of one polarity of conductivity with low impurity concentration; formation of mask and doping of drain, source, and guard regions of other polarity of conductivity with low impurity concentration; deposition of silicon oxide layer and formation of separating zones between drain, source, and guard regions therein; formation of mask and doping of drain, source, and guard regions of one polarity of conductivity with high impurity concentration; formation of mask and doping of drain-source and guard regions of other polarity of conductivity with high impurity concentration; deposition of silicon oxide layer and its chemical and mechanical polishing until gate surface is opened; opening of contact windows in mentioned silicon oxide layer to provide access to diffusion regions; metal plating and formation of interconnections.EFFECT: enhanced yield due to greater reproducibility of characteristics of passive and active integrated-circuit components; enhanced speed due to reduced throughput capacities of transistors in surface concentration of impurities in drain, source, and guard regions.1 cl, 11 dwg

The amplifier circuit radio circuit of the radio frequency mixer and containing radio // 2217862
The invention relates to a structure oriented on the radio, in particular, to the structure of the CMOS circuits for digital radio transceiver

A method of manufacturing a semiconductor element with a partially held in the wiring substrate, and also made by this method, the semiconductor element // 2214649
The invention relates to the manufacture of secure integrated circuits, namely the method of manufacturing a semiconductor element passes at least partially in the substrate wiring, but also the semiconductor element

A method of manufacturing a cmos ic base matrix crystals (bmc) // 2124252
The invention relates to microelectronics, and more particularly to a method of manufacturing a CMOS integrated circuits (ICS) base matrix crystals (BMC) with samozavestna polysilicon gate and polysilicon or Poliziano distributing the first level and can be used both in digital and in analog and analog-digital integrated circuits low-cost manufacturing

A method of manufacturing integrated circuits for mos transistors // 2100873
The invention relates to electronic devices and can be used in the manufacture of integrated circuits, especially when it is necessary to minimize the number of operations lithography

A method of manufacturing a mos ic // 2099817
The invention relates to integrated microelectronics and can be used in the design and manufacture of single and complementary MOS IC digital, linear and analog applications
 
2551080.
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