Digital stores characterised by the use of particular electric or magnetic storage elements and storage elements therefor and and (G11C11)

G   Physics(393877)
G11   Information storage(18772)
G11C11                 Digital stores characterised by the use of particular electric or magnetic storage elements; storage elements therefor (g11c0014000000-g11c0021000000; take precedence);;(3053)
G11C11/02 - Using magnetic elements(148)
G11C11/061 - (6)
G11C11/063 - (14)
G11C11/065 - (7)
G11C11/067 - (8)
G11C11/14 - Using thin-film elements(737)
G11C11/155 - (51)
G11C11/18 - Using hall-effect devices(6)
G11C11/20 - Using parametrons(4)
G11C11/21 - Using electric elements(4)
G11C11/26 - Using discharge tubes(2)
G11C11/28 - Using gas-filled tubes(6)
G11C11/34 - Using semiconductor devices(104)
G11C11/38 - Using tunnel diodes(23)
G11C11/39 - Using thyristors(20)
G11C11/40 - Using transistors(553)
G11C11/401 - (38)
G11C11/402 - (1)
G11C11/403 - (5)
G11C11/406 - (34)
G11C11/4063 - (16)
G11C11/407 - (8)
G11C11/408 - (1)
G11C11/409 - (12)
G11C11/4091 - (5)
G11C11/4093 - (4)
G11C11/413 - (1)
G11C11/419 - (5)
G11C11/4193 - (4)
G11C11/4197 - (1)

Semiconductor memory device // 2641478
FIELD: physics.SUBSTANCE: semiconductor memory device capable of performing the first mode with the first delay and the second mode with the second delay, greater than the first delay, contains a block of pads configured to accept external address and command; the first delay circuit configured to delay the address at the time corresponding to the first delay; the second delay circuit including shift registers connected in series and configured to delay the address at the time corresponding to the difference between the first delay and the second delay; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode, wherein the first mode and the second mode are write operations or read operations, the controller is able to perform one of the first mode and the second mode.EFFECT: reducing the number of shift registers used for the delay.12 cl, 32 dwg

ethod of increasing banding strip in station remembering devices // 2636670
FIELD: radio engineering, communication.SUBSTANCE: device contains at least two data channels; At least two memory chips installed one on top of another in the form of a stack. The memory chips include at least two memory units and at least a portion of the first data channel and a second data channel portion; And at least the first and second chip-chip connections. The first chip-chip connection is configured to connect the respective portions of the first data channel included in the first and second memory chips to form a first data channel, and the second chip-chip connection is configured to couple corresponding portions of the second transmission channel data included in the first and second memory chips to form a second data channel. Each of the communication channels thus formed is selectively connected to the first and second memory units included in the first chip of the memory and to the first and second memory units included in the second memory chip. Each of the memory units included in the first memory chip is configured to provide data into one channel from the formed data channels, and each of the memory units entering the second memory chip is configured to provide data to another channel from the generated data channels.EFFECT: increase the data transfer speed and system memory bandwidth.25 cl, 10 dwg

Semiconductor memory device // 2634217
FIELD: physics.SUBSTANCE: device contains memory blocks, each of which includes an array of memory cells; word lines connected to the lines of each of the memory blocks; an address latch-circuit configured to capture a complete address for determining one of the word lines, wherein the full address includes the first address and the second address; and a control circuit configured to ignore the reset operation for the first address as the target of the setup operation and to rewrite the first address in accordance with the setup operation upon receiving the first instruction for determining the reset operation for the storage unit and the setting operation for the first address.EFFECT: implementing a memory device that is capable of high-speed operation and has a large capacity.14 cl, 10 dwg

agnetic memory and method of management of it // 2628221
FIELD: physics.SUBSTANCE: magnetic memory comprises an array of cells including a plurality of memory cells disposed along the first and second directions, the array of cells including a first region and a second region around the first region, and each memory cell includes an element with a magnetoresistive effect in the quality of the memory element; and a reading circuit to read data from a memory location selected based on the address signal from the number of memory cells, wherein the reading circuit selects one definition layer from the plurality of determination levels based on a region of the number of the first and second regions in which the selected memory location is located and uses the selected detection level to read data from the selected memory location.EFFECT: increase the reliability of magnetic memory.20 cl, 11 dwg

emory device based on change in resistance // 2620502
FIELD: information technology.SUBSTANCE: according to one of the embodiments, memory device based on the resistance change includes a memory cell, a reading amplifier and a global bit line. Memory cell is in the location of crossed local bit line and word line. Memory cell is connected both to a local bit line and a word line. Reading amplifier reads the data stored in the memory cell by read current supply to the memory cell. Global bit line is connected between the local bit line and the reading amplifier. Global read bit line delivers read current supplied through the reading amplifier to the local bit line. Reading amplifier charges the global bit line before the local bit line and the global bit line are connected to each other.EFFECT: reduction of recording and reading time.20 cl, 9 dwg

A semiconductor memory device // 2618368
FIELD: electricity.SUBSTANCE: first device comprises word lines, connected to the memory cell array; second word lines connected to the spare area; The first line of a decoder configured to perform a selection of the first word lines on the basis of the row address; determination circuitry operable to determine whether or not a spare area replacing operation based on alternate-address included in the address line; and second lines of the decoder configured to perform a selection of the second word lines. Address lines include a first row address and a second row address input means in order of time-sharing. The first address line includes a full back-up address.EFFECT: increase in speed of the memory device.13 cl, 7 dwg

Low power electronic system architecture using non-volatile magnetic memory // 2616171
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering. Computer system comprises multiple functional modules, each functional module contains a functional unit and a magnetic random access memory (MRAM) unit, connected to operating unit, wherein MRAM unit is configured to store operational condition of functional unit during hibernation of functional module containing said functional unit; wherein computer system is configured to switch one of functional modules into standby state, when other functional modules are in an on state.EFFECT: technical result consists in reduction of consumed power and time for reading and recording.15 cl, 8 dwg

ethod for phase memory material production // 2610058
FIELD: physics.SUBSTANCE: invention relates to preparation of ⋅chalcogenide semiconductor alloys used in the non-volatile phase memory devices. The method for production of the phase memory material, including grinding and mixing of the initial components selected from the following ratio: 66.7 mol. GeTe% and 33.3 mol. % Sb2Te3, while 0.5-3 wt % of tin (Sn) is added to the charge, then the prepared charge is placed into a quartz ampule, which is then evacuated to a residual pressure of 10-5 mm Hg and sealed off, and then the ampule with the material is heated stepwise to a temperature of 500°C at a rate of 3-4°C per minute, kept at a temperature of 500°C for 4-6 hours, with subsequent heating to a temperature of 750°C at a rate of 1-2°C per minute, at that the ampule with the material is rotated around its axis at a rate of 1-2 rpm for 4 hours during heating. The ampule is further cooled down in a switched-off furnace, followed by annealing of the synthesized material at a temperature of 500°C for 12 hours, after which the material is used for phase memory material production. Thin films of the memory phase material are prepared by vacuum thermal evaporation of the synthesized material. During deposition of the thin films, the residual pressure in the chamber was 210-3 mm Hg, the substrate temperature did not exceed 50°C, which allowed to obtain a thin film in an amorphous state.EFFECT: invention provides phase memory material with increased optical contrast that improves functional characteristics of rewritable optical discs.2 dwg

Architecture of optical memory expansion // 2603553
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering. Optical storage device expansion system contains the first electric logical circuit for transmitting data in accordance with the point-to-point interconnection protocol for data packet transmission in accordance with the full data transmission rate; the first intermediate circuit connected to receive data from the first electric circuit via the electric communication line, herewith the first intermediate circuit is made with the possibility of data conversion into the optical format intended for transmission at a rate of at least twice exceeding the full data transmission rate; the second intermediate circuit connected to receive data in the optical format from the first intermediate circuit via the optic communication line, herewith the second intermediate circuit is configured to convert data into the electric format corresponding to the point-to-point interconnection protocol for data packet transmission; and the second electric logical circuit connected to receive data from the first electric logical circuit, herewith the optic communication line is initialized in accordance with optical training states.EFFECT: technical result is the increase of the storage device bandwidth.36 cl, 24 dwg, 2 tbl

agnetic random access memory cell with improved dispersion of switching field // 2599956
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering. Magnetic random access memory (MRAM) cell comprises a tunnel magnetic junction having the first ferromagnetic layer, the second ferromagnetic layer with the second magnetization, which can be oriented relative to the axis of anisotropy of the second ferromagnetic layer at a predetermined high-temperature threshold, and a tunnel barrier between the first and the second ferromagnetic layers; the first current transmission line extending along the first direction and being in communication with the tunnel magnetic junction; herewith the first current transmission line is configured able to provide the magnetic field to orient the second magnetization while transferring the field current; wherein the MRAM cell is configured relative to the first current transmission line in such a way, that while providing the magnetic field at least one magnetic field component is perpendicular to the said axis of anisotropy; the second ferromagnetic layer is of asymmetric shape along at least one of its dimensions, so that the second magnetization contains the pattern of C-shape condition.EFFECT: technical result is the reduction of power consumption and improved dispersion of the switching field.12 cl, 6 dwg

Self-referenced magnetic random access memory element comprising synthetic storage layer // 2599948
FIELD: computer engineering.SUBSTANCE: element of random-access memory (MRAM) comprises a magnetic tunnel junction having: memory layer; reading layer; and a tunnel barrier layer enclosed between storage layer and reading layer; memory layer contains a first magnetic layer having a first storage magnetisation; second magnetic layer having a second storage magnetisation; and a non-magnetic binding layer separating first and second magnetic layers so that first storage magnetisation is substantially antiparallel to second storage magnetisation; wherein first and second magnetic layers are configured so that at reading temperature first storage magnetisation is substantially equal to second storage magnetisation; and at write temperature, which is higher than read temperature, second storage magnetisation is greater than first storage magnetisation.EFFECT: providing low power consumption and increased rate of recording and reading of memory cell.11 cl, 10 dwg

ram cell and method for writing to mram cell using thermally assisted write operation with reduced field current // 2599941
FIELD: computer engineering.SUBSTANCE: method for writing to a magnetic random-access memory (MRAM) cell using a thermally assisted write operation, comprising a magnetic tunnel junction, formed from a memory layer having magnetisation memory; reference layer having reference magnetisation, and a tunnel barrier layer, located between read and memory layers; and a current line which is electrically connected with said magnetic tunnel junction; wherein method includes passing heating current via magnetic tunnel junction for heating magnetic tunnel junction; passing field current for switching storage magnetisation in written direction according to polarity of field current, wherein value of heating current is such that it acts as a spin polarised current and causes adjustment of spin transfer on storage magnetisation; and heating current polarity is such that it causes adjustment of spin transfer on storage magnetisation in said written direction.EFFECT: low field current.6 cl, 4 dwg

Cell of magnetic random access memory (mram) with self reference inlcudning ferrimagnetic intrinsic layers // 2599939
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering. Cell of magnetic random access memory (MRAM) comprises a magnetic tunnel junction including a storage layer having a net magnetization for writing data, which is controlled from the first direction to the second direction when the magnetic tunnel junction is heated to high temperature threshold, and which is fixed at low-temperature threshold; reading layer having a net magnetization for reading, which is reversible; and a tunnel barrier layer separating the reading layer from the storage layer; besides, at least one of the memory layer and reading layer contains material of ferrimagnetic 3d-4f amorphous alloy containing subarray of atoms of transition 3d-metals providing the first magnetisation, and subarray of atoms of rare-earth 4f-elements, providing a second magnetisation, so that at compensation temperature of said at least one of the memory layer and reading layer the first magnetisation is equal to the second.EFFECT: technical result ensured MRAM cell recording and reading with a weak recording/reading field.9 cl, 3 dwg

agnetic recording element // 2595588
FIELD: computer engineering.SUBSTANCE: magnetic recording element comprises a set of layers, which is a magnetic recording layer, wherein set includes central layer, at least of magnetised magnetic material, magnetisation direction parallel to plane of central layer, which is located between first and second outer layers of non-magnetic material; and device for recording current passing through second external layer and a central layer in direction of current, parallel to plane of central layer and making angle α in 90°±60° with said direction of magnetisation for driving in central layer effective magnetic field, wherein said current passes either in first direction, or in second direction opposite first magnetisation direction, for orientation of magnetisation direction in first magnetisation direction or in second direction of magnetisation opposite first magnetisation direction, direction of magnetisation is oriented in response to spin-orbital field, which is generated by recording current.EFFECT: providing recording operations without application of external magnetic field.33 cl, 12 dwg

Self-referential mram cell with optimised reliability // 2591643
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering. Element of magnetoresistive random access memory (MRAM), suitable for thermal recording and self-referential reading operation, has magnetic tunnel junction having first and second parts, each part has layer for storing, reading layer and tunnel barrier layer; wherein magnetic tunnel junction further comprises antiferromagnetic layer between two layers of memorising, fixing storage magnetisation of every layer storage at low temperature threshold and releasing at high temperature threshold, so that during recording operation free magnetisation of each layer is capable of reading on magnetic saturation in accordance with direction of magnetic field recording at application of this field and storage magnetisation are capable for switching in the direction, in fact, parallel and corresponding to direction of saturated free magnetisations.EFFECT: technical result consists in improvement of efficiency of heating the magnetic tunnel junction at minimisation of risks of breakdown and ageing tunnel barrier layers.9 cl, 1 dwg

agnetic memory element // 2585578
FIELD: physics.SUBSTANCE: group of inventions relates to a writeable magnetic element and writable magnetic device. Writable magnetic element comprises a stack of layers. Magnetic writing layer is made of at least one magnetic material having a direction of magnetisation that is parallel or perpendicular to central layer plane. Said writing layer is located between first and second outer layers made of different first and second non-magnetic materials, where second non-magnetic material is electrically conductive. Writable magnetic element also comprises a device for passing a write current only through second outer layer and magnetic writing layer, where write current flows in current direction parallel to magnetic writing layer plane and does not pass through stack of layers in a direction perpendicular to plane of layers, and a device for applying magnetic field with magnetisation direction and magnetic field perpendicular to each other.EFFECT: inversion of magnetisation is ensured due to magnetic layer which functions without passing current perpendicularly to plane of layers.24 cl, 25 dwg

Element and circuit for storage of magnetic state // 2584460
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering. Spin state storage element comprises magnetic device with variable resistivity configured to receive magnetic control signal to control resistance of said magnetic device with variable resistivity; and magnetic logic switching device connected with magnetic device with variable resistivity, wherein magnetic logic switching device is configured to receive magnetic logic input signal and perform logical operation based on magnetic logic input signal, as well as possibility of generating output signal based on magnetic resistance of above magnetic device with variable resistivity.EFFECT: technical result consists in creation of spin state storage element.25 cl, 16 dwg, 5 tbl

Recordable magnetic element // 2580378
FIELD: physics.SUBSTANCE: invention relates to a recordable magnetic element. The element comprises a stack of layers with a magnetic recording layer made of at least one magnetic material having a magnetisation direction perpendicular to the plane thereof, located between the first and second external layers made of the first and second nonmagnetic materials. The second nonmagnetic material is electroconductive. The recordable magnetic element includes a device which forces recording current to flow through the second external layer and the magnetic recording layer in the direction parallel to the plane of the magnetic recording layer, and a device for applying, in the presence of the said recording current, a magnetic recording field along the direction of the magnetic field, which is perpendicular to the plane of the magnetic recording layer. Memory is recorded in one direction or another direction by acting on the direction of the applied magnetic recording field.EFFECT: enabling the change of direction of magnetisation.19 cl, 13 dwg

emory unit of complementary metal-oxide-semiconductor structure ram // 2580072
FIELD: computer engineering.SUBSTANCE: invention can be used in static CMOS RAM blocks. Apparatus comprises an output bus of the storage unit, a memory consisting of two groups of transistors each connected through transmission gates four-bit data lines, two sense amplifiers, the first and second inputs of the first sense amplifier connected to the first and second bit lines of data, the first and second inputs of the second sense amplifier coupled to third and fourth bit lines of the data memory unit is provided with first and second additional transistors and gate NOR, and a bias line to the voltage across it is greater than threshold values, wherein the sense amplifiers are reflectors current pairs transistors with the structure of the metal-oxide semiconductor and the channel hole conductivity, the inputs of OR-NO elements are connected to the outputs of the first and second sense amplifiers, which are connected, respectively, drains of the first and second additional transistors, the gates of which are connected with the line offset voltage on it larger than the threshold, and the output of OR-NO element is connected to the output bus of the memory block.EFFECT: technical result is to increase the reliability of data read from the memory cells under the influence of a single nuclear particles in a state where the memory cell is based on two groups of transistors are temporarily stored in an unsteady state.1 cl, 1 dwg, 5 tbl

emory cell for complementary metal-oxide-semiconductor ram structure // 2580071
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering and can be used in units os multi-port static CMOS RAM. Memory cell for complementary microcircuit of metal-oxide-semiconductor structure RAM includes trigger, consisting of two groups of transistors, ports data recording and reading ports arranged on-chip integrated circuit, outputs of data recording ports are connected to corresponding outputs of two groups of transistors of trigger, according to the invention cell is equipped with two inverters and two inverters to third state, first outputs of first and second groups of transistors are connected to trigger input of first inverter, second outputs of first and second groups of transistors are connected to trigger input of second inverter, third output of first group of transistors of trigger and third output of second groups of transistors of trigger are connected to first inputs of first and second inverters to third state, output of first inverter is connected to second input of first and third input of second inverters to third state, output of second inverter is connected to third input of first and second input of second inverters to third state outputs of which are connected to inputs of data read ports.EFFECT: technical result consists in improvement of reliability of reading data from memory cell at impact of single nuclear particles in conditions when trigger memory cell based on two groups of transistors is in unbalanced state.2 cl, 3 dwg, 3 tbl

Film magnetic structure for electrically controlled uhf devices // 2575123
FIELD: electricity.SUBSTANCE: structure contains thin film metal ferromagnetic layers, each of them is separated from the adjacent layer by a nonmagnetic dielectric layer. All the thin film metal ferromagnetic layers are divided to multiple electrically insulated areas, their dimensions are below one eighth of the length of the electromagnetic wave in the layer of the nonmagnetic dielectric.EFFECT: increased activity of the film magnetic structure, ie its ability to change its HF effective magnetic permeability under the action of an external control magnetic field.3 cl, 5 dwg

agnetic random access memory cell with low power consumption // 2573757
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. A magnetic random access memory cell comprises a magnetic tunnel junction having an upper electrode; a first ferromagnetic layer having a first magnetisation direction; a second ferromagnetic layer having a second magnetisation direction which can be adjusted relative to the first magnetisation direction; a tunnel barrier layer between the first and second ferromagnetic layers; and an external layer, wherein the second ferromagnetic layer is situated between the external layer and the tunnel barrier layer; wherein the magnetic tunnel junction further comprises a magnetic or metallic layer on which the second ferromagnetic layer is deposited; and wherein the second ferromagnetic layer has a thickness between 0.5 nm and 2 nm, and is configured to provide the magnetic tunnel junction with magnetoresistance which is greater than 100% by annealing at temperature of 280°C-360°C during an annealing time period of 30 min to 2.5 h, with application of a magnetic field of 0.5-2 T.EFFECT: low spin polarised writing current with magnetoresistance of 100% or higher.16 cl, 5 dwg

agnetic tunnel junction having polarising layer // 2573756
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. A method of making a magnetic tunnel junction to be written with a spin polarised current, the magnetic tunnel junction having a tunnel barrier layer between a first ferromagnetic layer having a first magnetisation with a fixed orientation and a second ferromagnetic layer having a second magnetisation being freely oriented, and a polarising layer having a polarising magnetisation; comprising: depositing the first and second ferromagnetic layers and the tunnel barrier layer; annealing the deposited ferromagnetic layers at a first annealing temperature of 300°C or higher such as the tunnel magnetoresistance of the magnetic tunnel junction is equal to or greater than 150%; depositing the polariser layer; and annealing the deposited polariser layer at a second annealing temperature between 150°C and 250°C so as to orient the polarising magnetisation perpendicular to the first and second magnetisation, said annealing of the deposited ferromagnetic layers at the first annealing temperature being performed prior to depositing the polariser layer.EFFECT: providing high tunnel magnetoresistance, which is equal to or greater than 150%.6 cl, 1 dwg

ultibit cell with synthetic storage layer // 2573457
FIELD: physics, computer engineering.SUBSTANCE: invention relates to electronics, particularly to a method of recording and reading more than two bits of data for a magnetic random access memory (MRAM) cell. A MRAM cell comprises a magnetic tunnel junction formed from a read magnetic layer having a read magnetisation, and a storage layer comprising a first storage ferromagnetic layer having a first storage magnetisation, a second storage ferromagnetic layer having a second storage magnetisation. The method includes heating the magnetic tunnel junction over a high temperature threshold; orienting the first storage magnetisation at an angle relative to the second storage magnetisation for the magnetic tunnel junction to reach a resistance state level determined by the orientation of the first storage magnetisation relative to the orientation of the read magnetisation; and cooling the magnetic tunnel junction.EFFECT: enabling storage of at least four distinct state levels in a MRAM cell using only one current line to generate a writing field.15 cl, 14 dwg

Cell of static random access memory // 2573226
FIELD: electricity.SUBSTANCE: cell of static random access memory comprises a group of four n-MOS transistors including the first, second, third and fourth triggers, a group of four p-MOS transistors including the first, second, third and fourth triggers, the first and second bit record pass transistors, the first and second bit inversion pass transistors, a supply voltage input, a Zero Volt input, a bit value input, a bit inversion value input, a record input, a data output, at that the cell includes additionally the second group of four n-MOS transistors, the second group of four p-MOS transistors, the third and fourth bit record pass transistors, the third and fourth bit inversion pass transistors, the second inverse data output.EFFECT: fail-safety improvement in regard to the irreversible failure of the transistors.5 dwg, 1 tbl

agnetoelectric memory // 2573207
FIELD: physics.SUBSTANCE: magnetoelectric memory comprises a magnetic element, having two directions of stable equilibrium of its magnetisation, wherein said directions are not opposite to each other; an piezoelectric or electrostrictive substrate which is mechanically linked to said magnetic element; and at least a first and a second electrode, configured to apply an electric field to the piezoelectric or electrostrictive substrate such that said substrate acts on said magnetic element with non-isotropic mechanical stress which causes transition of the magnetisation state of said magnetic element due to magnetostrictive coupling.EFFECT: eliminating the energy barrier between two stable states during transition.19 cl, 23 dwg

ultilevel magnetic element // 2573205
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. A multilevel magnetic element comprises a first tunnel barrier layer between a sensitive layer having magnetisation which can be freely aligned and a first storage layer having magnetisation which is fixed at a first low temperature threshold and can be freely aligned at a first high temperature threshold, wherein the magnetic element further comprises a second tunnel barrier layer and a second storage layer having magnetisation which is fixed at a first low temperature threshold and can be freely aligned at a second high temperature threshold, the sensitive layer being formed between the first and second tunnel barrier layers.EFFECT: longer service life of the magnetic element owing to low heating current required to heat the magnetic element.12 cl, 3 dwg, 4 tbl

agnetoresistive memory cell and method for use thereof // 2573200
FIELD: physics.SUBSTANCE: magnetoresistive memory cell comprises a remagnetisable layer and a non-remagnetisable layer separated by a barrier layer, and writing and reading means. The memory cell further includes a fastening layer made of p- or n-type semiconductor material, the next layer of semiconductor material with an opposite type of conductivity, forming a p-n junction, comprises an address line and a bit line, situated on both sides of the listed layers of the memory cell, means of generating write currents in the address and bit lines, reading means in the form of means of measuring electrical resistance of the memory cell, as well as means of setting polarity and the value of relative electrical bias between the address and bit lines.EFFECT: simple technique of making a magnetoresistive memory cell.2 cl, 1 dwg

agnetic random access memory cell with dual junction for ternary content addressable memory applications // 2572464
FIELD: physics, computer engineering.SUBSTANCE: invention can be used as ternary content addressable memory. A magnetic random access memory (MRAM) cell includes a first tunnel barrier layer enclosed between a soft ferromagnetic layer, having free magnetisation, and a first hard ferromagnetic layer, having a first storage magnetisation; a second tunnel barrier layer enclosed between a soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetisation; wherein the first storage magnetisation can be freely oriented at a first high predetermined temperature threshold and the second storage magnetisation can be freely oriented at a second predetermined high temperature threshold; wherein the first high predetermined temperature threshold is higher than the second predetermined high temperature threshold.EFFECT: enabling use of a MRAM cell as ternary content addressable memory (TCAM) with a smaller cell size.15 cl, 2 dwg, 2 tbl

Random access thermal magnetic element with longer service life // 2565161
FIELD: physics, computer engineering.SUBSTANCE: present invention provides a magnetic memory element (1) which is suitable for a writing operation with thermal switching, comprising a current line (4) in electrical communication with one end of a magnetic tunnel junction (2), where the magnetic tunnel junction (2) comprises: a first ferromagnetic layer (21), having a fixed magnetisation; a second ferromagnetic layer (23) having magnetisation which can be freely set up with a given high temperature threshold; and a tunnelling barrier (22) which is provided between the first and second ferromagnetic layers (21, 23); where the current line (4) is adapted to transmit heating current (31) through the magnetic tunnel junction (2) during a write operation; where said magnetic tunnel junction (2) further comprises at least one heating element (25, 26) adapted to generate heat when heating current (31) passes through the magnetic tunnel junction (2); and a thermal barrier (30) in series with said at least one heating element (25, 26), where said thermal barrier (30) is adapted to limit heat generated by said at least one heating element (25, 26) within the magnetic tunnel junction (2).EFFECT: producing a magnetic memory element (1) suitable for a write operation with thermal switching.11 cl, 2 dwg

ethod of making static random access memory and static random access memory (ram) // 2559768
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. A method of making static random access memory includes arranging data bit storage units and data read buses and data write buses in space, wherein a memory cell is structurally divided into three types of modules: a data bit storage module, a write port module and a read port module, wherein the write port module is arranged separately from the storage module and connected to the input of the data bit storage module, and the read port module is arranged separately from the storage module and connected to the output of the storage module.EFFECT: improving noise-immunity of the RAM by reducing the capacitance of parasitic capacitors between components of the device.3 cl, 3 dwg

ultibit magnetic random access memory cell with improved read margin // 2556325
FIELD: physics, computer engineering.SUBSTANCE: magnetic random access memory (MRAM) cell comprises a magnetic tunnel junction comprising a tunnel barrier layer between a first magnetic layer having a first magnetisation direction, and a second magnetic layer having a second magnetisation direction being adjustable from a first direction to a second direction so as to vary junction resistance of the magnetic tunnel junction from a first to a second junction resistance level. Said magnetic tunnel junction further comprises a resistive switching element electrically connected to the magnetic tunnel junction and having a switching resistance which can be switched from a first to a second switching resistance level when a switching current passes through the resistive switching element. The MRAM cell resistance can have at least four different cell resistance levels depending on the resistance level of the junction resistance and the switching resistance. The tunnel barrier layer consists of a resistive switching element.EFFECT: improved readability for a MRAM cell.13 cl, 6 dwg, 3 ex

emory cell for complementary microcircuit of metal-oxide-semiconductor structure // 2554849
FIELD: electricity.SUBSTANCE: memory cell for complementary microcircuit of metal-oxide-semiconductor structure consists of pairs of interconnected NMOS and PMOS transistors, with power supply bus and selection lines and data lines placed at the integrated circuit crystal. Transistors are united into two pairs, each of them containing one pair of NMOS and PMOS transistors with jointed drains, one NMOS transistor and one PMOS transistor interconnected by their gates with jointed drains of this pair. These two groups of transistors are placed at the integrated circuit crystal at distance from each other, which is equal or more than threshold distance in order to exclude simultaneous impact of single nuclear particle to both groups of transistors with level bigger than the threshold value.EFFECT: improving failure resistance to impact of single nuclear particles without excess increase in square area occupied by one memory cell at crystal included into composition of integral CMOS random access memory.2 cl, 3 dwg, 2 tbl

agnetic device with optimised heat confinement // 2553410
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. A magnetic element to be written using a thermally-assisted switching write operation comprises a magnetic tunnel junction formed from a tunnel barrier being disposed between first and second magnetic layers, said second magnetic layer having a second magnetisation the direction of which can be adjusted during a write operation when the magnetic tunnel junction is heated to a high threshold temperature; an upper current line connected at the upper end of the magnetic tunnel junction; and a strap portion extending laterally and connected to the bottom end of the magnetic tunnel junction; the magnetic element further comprising a bottom thermal insulating layer extending parallel to the strap portion and arranged such that the strap portion is between the magnetic tunnel junction and the bottom thermal insulating layer.EFFECT: reduced heat loss in the magnetic tunnel junction.14 cl, 7 dwg

ethod for writing in mram-based memory device with reduced power consumption // 2546572
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. A method of writing in a memory device comprising a plurality of magnetoresistive random access memory (MRAM), wherein each MRAM cell to be written by using a thermally-assisted switching (TAS) write operation, includes a magnetic tunnel junction (MTJ) having a resistance that can be varied during a write operation when the MTJ is heated to a high threshold temperature, and a selected transistor electrically connected to the MTJ; a plurality of word lines and bit lines connecting MRAM cells along a row and a column, respectively; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the MTJ of a selected MRAM cell; once the MTJ has reached the high threshold temperature, varying the resistance of the MTJ; and cooling the MTJ to freeze said resistance in its written value; said word line voltage is a word line overload voltage which is higher than the base operating voltage of the MRAM cells such that the heating current has a magnitude that is high enough for heating the MTJ to the predetermined high threshold temperature.EFFECT: reduced power consumption when writing in a memory device.8 cl, 3 dwg

Radiation-resistant complementary metal-oxide-semiconductor transistor based element library // 2539869
FIELD: physics.SUBSTANCE: invention relates to microelectronics. An element library based on complementary metal-oxide-semiconductor (MOS) transistors, comprising a p-type substrate and an n-type pocket, n- and p-type MOS transistor active regions, p+ and n+ contacts for the zero potential and supply bus, further includes an extended n+ protection located along the outer boundary of the pocket and which fills the entire free area of the pocket, as well as an annular p+ protection around each of the n-type transistor groups with drain/gate regions of transistors with different potential, which fills the entire free area of the substrate.EFFECT: creating a radiation-resistant element library based on complementary metal-oxide-semiconductor transistors with a smaller area of elements on the chip and faster operation.5 dwg

emory chip-based storage // 2531576
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. Storage based on microcircuits with a rectangular hysteresis loop with full-point magnetic element electronics, with electrical rewriting, wherein the memory has a virtually unlimited scanning frequency, and a completely magnetic design.EFFECT: designing a storage based on magnetic materials only.3 dwg, 7 tbl

agnetic element and method to control parameters of magnetic vortex in ferromagnetic discs // 2528124
FIELD: measurement equipment.SUBSTANCE: group of inventions relates to the field of magnetic micro- and nanoelements, represents a magnetic element for monitoring of parameters of a magnetic structure of "vortex" type, which may be used as a basis to create a magnetoresistive random access memory, and also the method of such monitoring applicable for diagnostics of nanomaterials. The concept of the invention is as follows: a magnetic element of two ferromagnetic discs of various diameter is formed on a substrate from silicon, and the discs are asymmetrically arranged on each other and separated with a layer from non-magnetic materials, having a disc shape. Dimensions of the magnetic element are such that in a large disc with no induced magnetic field available a vortex state is generated, and in a small disc - a single-domain one. Depending on the angle of magnetic field application, a vortex state is generated in the large disc with certain chirality, and in the small disc - a single-domain state with controlled direction of magnetisation.EFFECT: design of a magnetic element makes it possible to create an asymmetric configuration of a magnetic structure, which is a necessary condition for monitoring vortex parameters as it is generated in a large disc, and provides an opportunity to control chirality of a vortex generated in a large disc, and direction of magnetisation in a small disc It is achieved during application of magnetic field at the angles of 0, 90, 180 or 270 degrees relative to the axis that connects centres of discs.10 cl, 4 dwg, 1 ex

ethod of producing thin-film polymer nanocomposites for superdense magnetic information recording // 2520239
FIELD: chemistry.SUBSTANCE: method of producing polymer nanocomposites in form of thin films for superdense information recording involves producing a precursor consisting of polyvinyl alcohol, water and a mixture of water-soluble salts of ferric and ferrous iron, followed by treatment with at least one water-soluble dialdehyde at pH 0-3 in the presence of an acid as an acidifying agent, obtaining a thin film on a dielectric nonmagnetic substrate depositing the precursor on a substrate rotating on a centrifuge to form a gel film, treating the obtained gel film with an alkali, the alkali being added in an amount allows complete alkaline hydrolysis of the mixture of iron salts to form a mixture of magnetite or maghemite. The obtained gel film is treated with the alkali in ammonia vapour which is formed from aqueous ammonia solution (NH4OH) or hydrazine hydrate (N2H4·H2O) for 5.0-15.0 hours.EFFECT: reduced particle size dispersion of magnetite and maghemite nanoparticles, obtaining a nanocomposite with a uniform structure, the obtained structure can be used as storage medium for superdense magnetic information recording.2 dwg, 1 ex

Spin-torque transfer magnetoresistive mram memory array integrated into vlsic cmos/soi with n+ and p+ polysilicon gates // 2515461
FIELD: physics, computer engineering.SUBSTANCE: invention relates to spin-torque transfer MRAM (Magnetic Random Access Memory) array cell circuits. The array-type device includes a plurality of devices on spin-torque transfer magnetic tunnel junctions (MTJ), arranged into an array of memory cells; an information writing/reading device for a specific MTJ device, connected corresponding MTJ devices to change magnetisation polarity of the free layer of each MTJ device, an amplifier unit for reading data at the output of the array of memory cells, capable of detecting the signal level and generate a binary output signal based on comparison of the signal level in the bit of the array of memory cells in a comparator. When forming the topology, the MTJ device is made in form of an ellipse with the easy magnetic axis directed on its large axis.EFFECT: high density of arranging separate transistor structures of the MOS technology and memory cells of an array, as well as high resistance to non-steady transient processes from the effect of ionising radiations.12 cl, 37 dwg, 11 tbl

emory cell of static storage device // 2507611
FIELD: information technology.SUBSTANCE: memory cell of static random access memory (RAM) has three series-connected CMOS inverters connected between a supply bus and an earth bus; a first transmission gate consisting of two series-connected address transistors whose gates are connected to a write address bus and a column selection address bus; a second transmission gate in form of an address transistor whose gate is connected to the read address bus; a written data acknowledgement circuit consisting of two parallel-connected complementary transmission gates, one of which is connected to non-inverting and inverting inputs of the write address bus, and the other to the non-inverting and inverting inputs of the column selection address bus. The input of the first CMOS inverter is connected through the first transmission gate to a first bit line; the output of the first CMOS inverter is connected to the input of the second CMOS inverter; the output of the second CMOS inverter is connected to the input of a third inverter and through the written data acknowledgement circuit to the input of the first CMOS inverter; the output of the third CMOS inverter is connected through the second transmission gate to a second bit line.EFFECT: high reliability and fault-tolerance of random access memory.2 cl, 1 dwg

Redundant register in multi-phase code // 2486611
FIELD: information technologies.SUBSTANCE: redundant register comprising memory cells of information signals Ra, from which by signals from a control bus the data arrives into a block of correction, besides, the register includes memory cells of reference signals Rx and blocks of error correction, inputs of which are connected with the block of correction and with elements of memory cells Rx, Ra, at the same time outputs of error correction blocks in the reference part X'(x1', x2', x3') and information part A'(a1'…am') are connected with elements of the memory cells Rx, Ra accordingly, and are the outputs of the register.EFFECT: higher reliability and noise immunity of electric drives with digital control due to higher validity of functioning of devices comprising memory cells.6 dwg

Electromechanical device for protection of information placed on digital usb flash storage against unauthorised access // 2486583
FIELD: information technologies.SUBSTANCE: electromechanical device for protection of information placed on a digital USB flash storage, against unauthorised access comprises a casing that contains a ferromagnetic frame, inside of which there are coaxially arranged a fixed inductor and a movable anchor made of an electroconducting material and a striker made of a ferromagnetic material. The anchor is made in the form of a disc with an inner cylindrical bushing and is connected with a striker. The frame is made in the form of a magnetic conductor and in the cross section covers the inductor, the anchor and the space of anchor and striker travel. The lower wall of the frame is made with a curve designed for a digital USB flash storage. In the frame there are two double flat springs, which are made as capable of moving the digital storage along the longitudinal axis of the z frame.EFFECT: higher efficiency of information protection, reduced dimensions and higher reliability of a device.14 cl, 14 dwg

emory cell for fast erasable programmable read-only memory and method of its programming // 2481653
FIELD: information technologies.SUBSTANCE: memory cell comprises an n(p)-MOS-transistor, a capacitor, an address discharge bus, differing by the fact that it additionally comprises the first and second diodes and a numerical bus, at the same time the cathode (anode) of the first diode is connected with the numerical bus by a source of the n(p)-MOS-transistor, its anode is connected to the anode of the second diode, with the gate area of the n(p)-MOS-transistor and the first output of the capacitor, the second output of which is connected to the gate of the n(p)-MOS-transistor and to the address bus, and the cathode of the second diode is connected with the area of the drain of the n(p)-MOS-transistor and the discharge bus.EFFECT: increased efficiency, reliability and integration of nonvolatile electrically programmable read-only memories.4 cl, 5 dwg

Dual power scheme in memory circuit // 2480850
FIELD: information technology.SUBSTANCE: dual voltage semiconductor memory device having a plurality of write drivers receiving low voltage data input signals; a plurality of bit lines connected to the plurality of write drivers, wherein the plurality of write drivers is configured to write low voltage data input signals in the plurality of bit lines in response to reception of low voltage data input signals; a timing tracking circuit configured to delay a high voltage number line signal in accordance with the time associated with the plurality of write drivers which write low voltage data input signals; and a plurality of memory cells which react to the high voltage number line signal and the plurality of write drivers writing the low voltage data input signals.EFFECT: reduced power consumption.30 cl, 6 dwg

ethod for regeneration and failure protection of dynamic memory and apparatus for realising said method // 2477880
FIELD: information technology.SUBSTANCE: method for regeneration and failure protection of dynamic memory, involving serial reading of data, detecting errors in the data contained in memory, modifying the data by correcting the detected errors at each memory address and reading with a period of time which is not greater than the memory regeneration time, wherein the modified data are recorded at the same memory address with a lower priority, and during the recording latency period, access to the same memory address is listened and stability errors are then analysed.EFFECT: faster operation and failure safety of the system.4 cl, 2 dwg

Recording operation for magnetoresistive random access memory with spin transfer torque with reduced size of bit cell // 2471260
FIELD: information technologies.SUBSTANCE: magnetoresistive random access memory with spin transfer torque (STT-MRAM) having source lines. Besides, each source line is substantially arranged in parallel to a word line connected to the first row of bit cells. Each source line is substantially arranged perpendicularly to bit lines connected to the first row of bit cells. Besides, the STT-MRAM device comprises the following components: a device for setting lower voltage in a line of bits of the selected bit cell during recording operation; a facility for setting high voltage in lines of bits of non-selected bit cells during recording operation; a selector of source lines connected to multiple selection lines. Each of selection lines is connected to one of many source lines and arranged as capable of activating the selection line, and an activated line of selection activates a source line; a setting module of a source line connected to each of many source lines, and arranged as capable of setting high voltage on an activated source line during recording operation.EFFECT: improved stability of recording and reduced dimensions of a bit cell in STT-MRAM.21 cl, 18 dwg

Static memory cell with two address inputs // 2470390
FIELD: physics, computer engineering.SUBSTANCE: invention relates to computer engineering. The static memory cell with two address inputs based on MOS transistors consists of a flip flop, two selection switches and an AND logic element which controls the switches, wherein the flip flop consists of first and second n-channel MOS transistors and third and fourth p-channel MOS transistors, and has an additional common bus for flip flops which is connected to sources of the first and second MOS transistors, wherein the potential of the common bus for flip flops is higher than that of the common bus of the cell.EFFECT: high noise-immunity.3 dwg

emory cell for high-speed eeprom with controlled potential of under-gate region // 2465659
FIELD: information technology.SUBSTANCE: memory cell for high-speed controlled gate-region potential EEPROM, the electric circuit of the memory cell having an n(p)-MOS transistor, first and second diodes, a capacitor, a number, an address and a bit line, wherein the cathode (anode) of the first diode is connected to the number line and the source of the n(p)-MOS transistor, its anode is connected to the anode of the second diode, the region under the gate of the n(p)-MOS transistor and the first lead of the capacitor, the second lead of which is connected to the gate of the n(p)-MOS transistor and the address line, and the cathode of the second diode is connected to the drain region of the n(p)-MOS transistor and the bit line, wherein the electric circuit of the memory cell additionally includes a p(n)-field-effect transistor, a common and control line, wherein its source is connected to the region under the gate of a MOS transistor, the gate is connected to the control line and the drain is connected to the common line.EFFECT: higher reliability of memory cell work.2 cl, 6 dwg

Systems and methods for dynamic power saving in electronic memory operation // 2464655
FIELD: information technology.SUBSTANCE: memory has a series segmented bit line for accessing data in said memory, a latch repeater which controls bit line segments, wherein the latch repeater is controlled by memory address bits and determinants selected from a list of read- and write-enable signals. The method describes operation of said memory.EFFECT: saving power in electronic memory.15 cl, 4 dwg
 
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