Device for dividing modular numbers // 2628179

FIELD: physics.SUBSTANCE: device for dividing modular numbers contains a clock pulse input, a global reset input, a dividend input, a divisor input, an OR element, a positional characteristic calculation unit, an approximation series refinement unit, a quotient derivation unit, and a quotient derivation output. In this case, the positional characteristics calculation unit contains a dividend register, n dividend inverters, n storage registers of module pi, where i =1,…, n, n storage registers of coefficient ki, n dividend integrators, n multipliers of the negative dividend, n multipliers of the positive divisible, an integrator of the value F(A), an integrator of the value F (-A), a storage register of value F (-A), a storage register of value F(A), a divisor register, n divisor inverters, n storage registers of module pi, n storage registers of coefficient ki, n divisor integrators, n multipliers of the negative divisor, n multipliers of the positive divisor, an integrator of value F(B), an integrator of value F (-B), a storage register of value F (-B), a storage register of value F (B), a XOR element, a dividend multiplexer, a divisor multiplexer, a comparison unit. The approximation series refinement unit contains a shift register, a counter, a storage register F (|A|), a minuend storage register, a minuend selection multiplexer, an inverter, a memory of degrees "2" in the residue number system, an integrator, next minuend selection multiplexer, NOT element, AND element. The quotient derivation unit consists of an OR element, a delay element, a holding register, n storage registers of the residue in modulo pi, n integrators in modulo pi, n demultiplexers in modulo pi, n storage registers of the sum in modulo pi, n inverters, n storage registers of the module pi, n integrators, n storage registers of the reciprocal value of the sum in modulo n of multiplexers of sum selection, sign holding register, sum storage register in the residue number system, a storage register of value "1", a storage register of value "-1", multiplexer of dividend and divisor absolute value equality, multiplexer of quotient derivation, a quotient storage register.EFFECT: providing the possibility of division with negative numbers represented in the residue number system.4 dwg

FIELD: physics.SUBSTANCE: number of transitions out of the operating range is determined only by the values of the residues on the working grounds of the UCDS, which can be calculated in advance and taken into account in the structure of the neural network of the correction unit. This makes it possible to avoid the counter of the number of transitions and the additional layer of the neural network that are in the prototype error correction block.EFFECT: reducing hardware costs.2 dwg, 5 tbl

ulti-input adder by module two // 2614370

FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering and can be used in digital computing devices, as well as in end fields GF(2ν) elements formation devices. Technical result is achieved by using new activation function in hidden layer, use of synaptic weights ωi,j, equal to one, which enables to eliminate synaptic weights multipliers from formal neuron structure, as well as elimination from neuron structure of output layer of unit,implementing activation function calculations.EFFECT: technical result consists in reduction of system expenses required for multi-input adder realization by module two.1 cl, 1 dwg

ethod and device for arrangement of groups of numbers in homogeneous units of digital register // 2591009

FIELD: computer engineering.SUBSTANCE: invention relates to special digital computer systems, can be used in communication systems and control of complex objects, is intended for compact arrangement in digital register groups numbers or data presented in modular formats. Device comprises input register, comparator unit, data transmission units, subtractor, output register.EFFECT: reduced information redundancy of digital register, which increases efficiency of distribution of data, efficiency of operation, technological effectiveness of circuit design of homogeneous block register.6 cl, 1 dwg

FIELD: computer engineering.SUBSTANCE: invention can be used as a special-purpose calculator - a versatile class of logical calculations. Apparatus comprises a switch, 2k memory blocks store values of expansion coefficients of polynomials, 2n-k storage memories erection residues in variable i-th degree (i = 0, 1, …, 2n-k-1) modulo P, multi-channel multiplexer allocation coefficient group, multi-channel multiplexer allocation group deductions, 2n-k modulo P multipliers, a modulo P adder, n inputs feed Boolean variable device, control input feeder value of number of variables of decomposition, control input values feeder coefficients, control input of subtraction of feeder construction of a variable in i-th degree modulo P, d outputs of device for outputting Boolean functions.EFFECT: reduced volume of equipment.1 cl, 1 dwg

FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering, in particular to modular neurocomputing tools, and is designed to calculate coefficients of generalised polyadic system (OPS), represented in Galois fields GF(2v). Device comprises a two-layer neural network, each layer of which includes 15 neurons, memory unit 7 and corrective modulo two adders.EFFECT: technical result is to enable error correction coefficients in OPS, which were obtained from code combination presented in polynomial residue class system (PSKV).1 cl, 1 dwg, 4 tbl

Cryptography on simplified elliptical curve // 2574826

FIELD: physics, computer engineering.SUBSTANCE: invention relates to encryption of messages based on use of points on an elliptical curve. A method of authenticating a password or identifying an identifier using cryptographic transformation includes steps of performing cryptographic transformation in an electronic component to obtain a point P (X, Y) on an elliptical curve based on at least one parameter t, associated with said password or identifier; authenticating the password or identifying the identifier using abscissa values (X) and ordinate values (Y) of the obtained point P.EFFECT: high reliability of cryptographic encryption owing to authentication and identification at the same time.7 cl, 3 dwg

Apparatus for expanding modular code bases // 2562366

FIELD: information technology.SUBSTANCE: apparatus for expanding modular code bases is characterised by that the input of the apparatus, to which is transmitted a modular polynomial code A(z)=(α1(z), α2(z), …, αn(z)), where αi(z) are remainders on the base pi(z), i=1, …, n, used in a polynomial modular code, is connected to the first inputs of modulo pi(z) multipliers of a first unit of multipliers, respectively, and the second inputs of said multipliers are connected to the outputs of a first memory unit, the output of the 2.i-th modulo pi(z) multiplier of the first unit of multipliers is connected to the first input of the 4.i-th modulo pn+1(z) multiplier of a second unit of multipliers. The second input of the modulo pn+1(z) multiplier is connected to the output of a second memory unit, the outputs of the multipliers of the second unit of multipliers are connected to inputs of a modulo two adder, the output of which is the output of the apparatus.EFFECT: reducing hardware costs on the base expansion operation in a polynomial modular code.1 dwg

FIELD: physics, computation hardware.SUBSTANCE: invention relates to computer engineering and can be used in arithmetic-logical devices of computer systems operated in the system of remainder classes. This device comprises registers, multiplexers, expanders, demultiplexers, LUT-table, multipliers, subtraction and multiplication units, switches, comparator circuit and control unit.EFFECT: faster response, simplified design.1 dwg, 1 tbl

FIELD: physics, computation hardware.SUBSTANCE: invention relates to computer engineering and can be used in computer systems operated in the system of remainder classes. Proposed device comprises multiplier, multiplexer, comparator circuit, registers, counter, subtractor, memory, control circuit, inhibit elements and switches.EFFECT: higher speed of division, simplified design, enhanced operating performances.1 dwg, 1 tbl

FIELD: physics.SUBSTANCE: device comprises the set of input registers for storage of number composed by the code of symmetric system of remainder classes. Permanent registers are used for storage of interval-position characteristics of constant, i.e., a positive number in symmetric system of remainder classes. Besides, it incorporates the unit for computation of interval-position characteristics and unit to test for accuracy of interval-position characteristics. Also, it includes comparator of interval-position characteristics and two-way binary decoder.EFFECT: higher response and control over accuracy of sign definition.3 dwg

FIELD: information technology.SUBSTANCE: presented positions are provided by using a novel interval-positional characteristic of modular arithmetic, which approximates the relative value of a number in a modular presentation from two sides. The device comprises groups of input registers for storing modular numbers to be compared, units for calculating interval-positional characteristics, a unit for bitwise comparison of modular numbers, units for verifying interval-positional characteristics, a unit for comparing interval-positional characteristics and a two-input binary decoder.EFFECT: faster operation and enabling verification of a comparison result.4 dwg

FIELD: information technology.SUBSTANCE: device has a device start input, a group of shift registers, a synchronisation unit, a device output, three-input AND element units, a modulo 2 adder, a group of data inputs, a group of control inputs of the device, a group of orthogonal base computing units, each having memory units, a modulo adder, a register, an index-to-element converter and a multiplier.EFFECT: high rate of conversion.2 dwg, 2 tbl

FIELD: information technology.SUBSTANCE: method is realised on a universal multi-core computer, having g k-bit cores, each facilitating a system of f operations which include algebraic multiplication and algebraic addition of numbers presented in position integer data formats. When facilitating multiplication operations, each number, multiplier and multiplicand, is presented in a modular-position format with a floating point in form of a (1+k+q·n)-element vector.EFFECT: high rate of computation by replacing the operation of multiplying t-bit position mantissas of multiplicands with n concurrently executed operations of multiplying q-bit character positions of numbers in a residue number system.

FIELD: information technology.SUBSTANCE: device includes input registers for temporary storage of bits of the initial number, memory for storing products and a parallel adder.EFFECT: faster operation of the device for determining the sign of a number and reducing equipment.3 dwg

FIELD: information technology.SUBSTANCE: device includes input registers, sign determining circuits, number polarity shifting circuits, look-up tables (memory) for storing constants and an adder, an XOR element and a number sign analysis circuit.EFFECT: faster operation of the device and cutting hardware costs.3 dwg

ethod of facilitating multiplication of floating-point numbers represented in residue number system // 2500018

FIELD: information technology.SUBSTANCE: method comprises steps of: concurrently writing the remainder on base p1 of a multiplicand in memory elements; concurrently counting the number of units bi in each column of the i-th matrix; shifting the binary number b1 one bit to the right; summing with a number b2; shifting the obtained sum b2s one bit to the right and summing with a number b3. Similarly, the obtained sums are shifted and summed with subsequent numbers to obtain a sum b2*m−1s, wherein the least significant bit of the number b1 is the first multiplication bit s1, the least significant bit of each obtained sum bis is the i-th multiplication bit. The binary number b2*m−1s is shifted; the least significant bit of the obtained number is the (2*m)-th bit of the determined product s2*m. If s is greater than p1, the obtained product s is corrected by successive subtraction of the base p1 from s until s is less than p1, otherwise correction is not performed; similarly, products of m-bit residues on the rest of the bases are calculated and corrected; the powers of multipliers are simultaneously summed up and the resultant sum is the power of the determined product.EFFECT: faster computation.2 dwg

odulo adder-accumulator // 2500017

FIELD: information technology.SUBSTANCE: device has an n-bit adder, an (n+1)-bit adder, a multiplexer and a register.EFFECT: broader functional capabilities due to introduction of the modulo addition operation.1 dwg

ethod of facilitating multiplication of floating-point numbers represented in residue number system // 2485574

FIELD: information technology.SUBSTANCE: remainder on base pi of a multiplicant is concurrently recorded in matrix memory elements of the i-th multiplier; the number of units bi in each column of the i-th matrix is concurrently counted; the binary number b1 is shifted by one bit to the right and summed with number b2; the obtained sum bs 2 is shifted by one bit to the right and summed with number b3. Similarly, the obtained sums are shifted and summed with subsequent numbers to obtain a sum bs 2*m-1, wherein the least significant bit of the number b1 is the first multiplication bit s1, the least significant bit of each obtained sum bs i is the i-th multiplication bit. The binary number bs 2*m-1 is shifted, the least significant bit of the obtained number is the (2*m)-th bit of the determined product s2*m. If si is greater than pi, the obtained product si is corrected by successive subtraction of the base pi from si until si is less than pi, otherwise correction is not performed; powers of multipliers are simultaneously summed up and the resultant sum is the power of the determined product.EFFECT: faster computation.2 dwg

One-bit full modulo adder // 2484519

FIELD: information technology.SUBSTANCE: invention can be used in digital computers as well as digital signal processing devices and cryptographic applications. The device has logic elements NOT, AND, OR.EFFECT: high speed of operation of the adder due to parallel execution of the modulo addition operation.1 dwg, 1 tbl

FIELD: information technology.SUBSTANCE: apparatus has input registers, projection generating circuits, memory units, adders, an analysis circuit, AND logic elements, a flip-flop and a projection counter.EFFECT: high speed of determining functional characteristics and cutting hardware costs.1 dwg

FIELD: information technology.SUBSTANCE: homogeneous computing environment cell has an XOR element, an AND element and two flip-flops.EFFECT: faster operation and reliability.3 cl, 6 dwg, 3 tbl

FIELD: information technology.SUBSTANCE: device for generating remainder on arbitrary modulus of a number has first and second registers, a group of AND elements, a unit of half-adders and a delay element, where the device also includes (K-1) half-adders, to whose second data inputs a modulus code is transmitted, and a number code "1" is transmitted to the first data input of the first half-adder and the second data input of the group of AND elements, the output of the i-th half-adder is connected to the second data input of the group of AND elements and with shift of one bit towards the most significant bits to the first data input of the i+1 half-adder, where i=1,…,K-2, the K-1 output of the half-adder is connected to the second data input of the group of AND elements.EFFECT: cutting the size of equipment.2 dwg

Doubler by module // 2445681

FIELD: information technologies.SUBSTANCE: invention may be used in digital computing devices, and also in devices to generate elements of end fields and in cryptographic applications. The device comprises summators, multipliers, inverters and multiplexors.EFFECT: expanded range of input number values.1 dwg

FIELD: information technologies.SUBSTANCE: device comprises n+1 single-digit parallel summators by module, where n - number of digits of summation numbers, at the same time each single-digit summator by module comprises two single-digit summators, two logical AND elements, a logical OR element, two logical NOT elements.EFFECT: expansion of functional capabilities of the device by introduction of a summation operation by module.2 cl, 2 dwg, 1 tbl

FIELD: information technology.SUBSTANCE: apparatus for generating remainder for given modulo contains T units for generating partial remainders with a data input on n bits, an input for primary remainders on (n-p-1)·(p+1) bits, an initialisation input, a synchronous input and output on (p+q) bits, respectively, two parallel (p+2)- and (p+1)-bit registers with a synchronous input, a data input and output, respectively, a multiplexer with two data inputs, a control input and output, a comparator with two inputs and an output, a subtractor with minuend and subtrahend inputs, as well as a difference output.EFFECT: high efficiency of generating a remainder on a given modulo for a stream of numbers by piping the process of calculating partial and resultant remainders based on precalculation of values of primary remainders.2 dwg, 1 tbl, 2 cl

FIELD: information technology.SUBSTANCE: apparatus has an input register, a switch, a multiplexer, a correction circuit, two half adders, two registers for recording intermediate results of modulus, 2 addition and three output registers.EFFECT: high bitness of binary codes converted in residue number systems.1 dwg

FIELD: information technologies.SUBSTANCE: device comprises inlet registers of dividend and divisor, unit of division with zero balance, unit for conversion of residual code into code of generalised position system, read-only memory, unit of subtractor, multiplication unit, prohibition unit, units of comparison, key, summator.EFFECT: expanded functional capabilities of device since division operation is performed at arbitrary values of dividend and divisor, and reduced volume of equipment.1 dwg, 1 tbl

Device for spectral error detection and correction in codes of polynomial system of residue classes // 2390051

FIELD: information technology.SUBSTANCE: invention relates to modular neurocomputer apparatus and is designed for detecting errors in code structures of the position-independent code of a polynomial system of residue classes (PSRC) presented in augmented Galois fields GF(2V). The device has a register, an interval polynomial calculation unit, a correcting adder, a spectral analysis unit which is a four-layer neural network. The first layer is designed for recording the interval polynomial which is presented in form of a binary code. The second layer is designed for calculating the first spectral components from control bases. The third layer is designed for inverting the obtained values. The fourth layer is designed fro calculating the correction value which is presented in a polynomial system of residue classes.EFFECT: reduced hardware expenses.2 dwg, 10 tbl

FIELD: information technology.SUBSTANCE: invention relates to computer engineering and can be used in digital computing devices, as well as in devices for generating finite field elements and in cryptographic applications. The device has a unit for generating partial remainders in absolute magnitude, unit of modulus multipliers and unit of modulus adders.EFFECT: faster operation.4 cl, 3 dwg

FIELD: physics, computer engineering.SUBSTANCE: invention is related to computer engineering, in particular, to modular neurocomputer facilities and is intended for performance of modular numbers ranging operation. Device comprises inlet layer of neurons, to which remains of ranged number A are supplied by modules pi, where i=1, 2, …, n, neuron networks of finite ring by modules pj, neuron networks of finite ring by modules pk, where modules pj and pk are subsets of set of modules pi, which are separate so that Pj/Pk≈1, where Pj and Pk products of modules of specified subsets, neuron network of finite ring of difference by module of number difference ΔC(A)=Pj-Pk, table multipliers.EFFECT: reduced volume of equipment, increased efficiency and expansion of device functional resources.1 dwg

Computing device // 2356086

FIELD: physics, computer engineering.SUBSTANCE: invention is related to computer engineering and may be used in digital computing devices, and also in devices for formation of finite fields formation in cryptographic applications. Device comprises (n-k+1) summators, (n-k+1) multiplexers, register and delay element.EFFECT: expansion of functional resources of device due to provision of formation of incomplete quotient.1 dwg

Computing mechanism // 2348965

FIELD: physics, computer facilities.SUBSTANCE: computing mechanism concerns computer equipment and can be used in digital computing mechanisms, and also in devices of digital processing of a signal and in cryptographic applications. The device contains 2n-2 adders and n-1 multiplexers.EFFECT: expansion of functionality of the device at the expense of provision of incomplete quotient formation.1 dwg

Device for number module multiplication // 2338241

FIELD: computer engineering.SUBSTANCE: device contains l decoders (l = ]log2(p-1)/2[, where p - device modulus), harmonic signal generator, l controlled phase shifters, harmonic signal phasing tester, phase shifters group for fixed phase value, first coder, first decoder, first OR gate, first group of OR gates, second OR gate, second coder, (l-1) units for multiplying by constant in absolute value, l units of AND gates, second decoder, second group of AND gates, third AND gate, third coder, modulo-two adder, first unit of OR gates, second unit of OR gates, code converter to transform number x to p-x and third unit of OR gates.EFFECT: device functionality enhancement.3 dwg, 2 tbl, 4 ex

Creator of random module reminder of number // 2324972

FIELD: computer engineering.SUBSTANCE: creator comprises units of partial reminder formation, multipliers by module, coefficients allocator, and adder by module. The result is achieved by increase of transformation base.EFFECT: performance improvement by means of decrease of executable operations.2 cl, 2 dwg

FIELD: computer engineering, in particular, modular neuro-computer devices, possible use for performing an operation for modulus multiplication of two polynomials.SUBSTANCE: in accordance to the invention the effect is achieved due to application of neuron network basis and conduction of operations in polynomial system of residue classes of expanded Galois field GF(2V). The device contains eight neurons in first layer, where the first four neurons of first layer are meant for receiving binary code of first operand, and the second four neurons of first layer are meant for receiving binary code of second operand, sixteen neutrons in second layer, which realize the AND operation, four neurons in third layer, which realize the modulo 2 addition operation.EFFECT: simplification of device, reduction of hardware costs.1 dwg, 3 tbl

Neuron network for dividing numbers which are represented in a system of residual classes // 2318239

FIELD: modular neuro-computing systems.SUBSTANCE: neuron network contains input layer of neurons, at inputs of which residuals of number being divided are received through system of modules, (n-1) neuron networks of finite ring for addition, (n-1) neuron networks of finite ring for multiplication, neuron network for expanding a tuple of numerical system of residues, and as output of neuron network for dividing numbers represented in system of residual classes are outputs of neuron network of finite ring for multiplication and output of neuron network for expansion of tuple of numerical system of residues.EFFECT: expanded functional capabilities, increased speed of division, reduced volume of equipment.1 dwg

FIELD: computer engineering, possible use in digital computing devices, and also in devices for forming elements of finite fields.SUBSTANCE: device contains (m-1) adders, (m-1) multiplexers, m keys, (m-2) shift blocks, inverter and modulus adder.EFFECT: expanded functional capabilities of the device.1 dwg

Device for modulus multiplication of numbers // 2313124

FIELD: automatics and computer science, possible use in computing structures functioning in modular notation system.SUBSTANCE: device contains harmonic signal generator, controllable phase shifters, harmonic signal phase meter, phase shifts for fixed phase value, encoder, blocks for modulus multiplication by a constant, blocks of AND elements, decoders.EFFECT: expanded functional capabilities of device due to realization of modular multiplication operation and due to finding of modular remainder of a number.3 dwg

FIELD: computer engineering, possible use for executing arithmetic operations over numbers, represented in non-positional modular computation system.SUBSTANCE: device contains N2 full adders, AND elements, where K=N-1, (N-2)(N-1) OR elements, control inputs.EFFECT: expanded functional capabilities of the device.3 dwg

FIELD: computer engineering, possible use in devices for transformation of numbers from polynomial system of residual classes to positional code.SUBSTANCE: device contains shift register, synchronization block, constant memory block, group of AND elements, positional accumulating adder, error detection block, data storage block, modulus two correcting adder. Error detection block is made in form of three-layered neuron network.EFFECT: increased speed of transformation, expanded functional capabilities of device due to ensured error correction.2 cl, 2 dwg, 5 tbl

Device for spectral detection and correction of errors in codes of polynomial residue classes system // 2301441

FIELD: computer engineering, in particular, modular neuro-computer devices, possible use for determining errors in code structures of non-positional code of polynomial residue classes system, represented in extended Galois fields GF (2V).SUBSTANCE: device contains three information inputs and two control inputs, block for computing interval polynomial, spectral analysis block, permanent memory device, correcting adder, and for correction of result spectral error finding and correcting method is used, and also the neuro-network basis.EFFECT: lower hardware costs of detection and correction of errors in modular codes of polynomial residue classes system.2 dwg

FIELD: computer engineering, possible use in digital computing devices for forming code series, creation of which is based on finite fields theory.SUBSTANCE: device contains block for forming partial remainders, modulus multiplexers, modulus adders.EFFECT: expanded functional capabilities due to creation of remainders by double modulus, by calculating partial remainders from polynomial powers with their following addition in acc to coefficients of polynomial powers.3 dwg

odulus multiplexer // 2299461

FIELD: computer engineering, possible use in digital computing devices, and also in devices for forming finite field elements.SUBSTANCE: device contains multiplier, adders, inverters, constant multipliers, multiplexer.EFFECT: expanded functional capabilities.1 dwg

odulus multiplier by two // 2299460

FIELD: computer engineering, possible use in digital computing devices, and also in devices for forming elements of finite fields.SUBSTANCE: device contains adders, inverters, multipliers, multiplexer.EFFECT: expanded functional capabilities due to expanded range of input number values.1 dwg

Device for transformation of number from a system of remainder classes to positional code // 2293437

FIELD: computer science, possible use in computing devices functioning in system of remainder classes, and also communication equipment for transferring information in remainder classes system codes.SUBSTANCE: device contains a group of constant memorizing devices, a group of registers, discharge-parallel modulus adder.EFFECT: decreased volume of equipment and increased speed of operation when transforming a number from remainder classes system to positional code.1 dwg

FIELD: cryptographic method and chip-card for encoding information, methods for creating electronic signatures.SUBSTANCE: at least one calculation step is performed, providing for realization of E operation of modular exponentiation in accordance to formula E=xd(mod p·q), where d and mod p·q are components of a secret key, while parallel represent first simple multiplier, q is second simple multiplier, d is level coefficient, and x represents base, while operation E of modular exponentiation is performed in accordance to Chinese theorem about remainders.EFFECT: decreased amount of computing operations and machine time costs during simultaneous increase of level of data protection from unsanctioned access.4 cl

Neuron network for rounding and scaling numbers, represented in system of remainder classes // 2271570

FIELD: computer science, in particular, modular neuron-computer means.SUBSTANCE: network has input layer of neurons, neuron network of end ring for determining number rank, neuron network of end ring for calculating remainder at base n+1, n-neuron networks of end ring for calculating scaled number, neuron network for calculating difference in numbers between input remainders and base remainder.EFFECT: decreased volume of equipment, increased speed of numbers rounding and expanded functional capabilities.1 dwg

Device for adding n numbers by module p // 2270476

FIELD: automatics and computer science, possible use for engineering of computing structures functioning in modular computation system.SUBSTANCE: device has encoder, controlled phase shifter, harmonic signal generator, phase shifters for fixed phase value, device for measuring the phase of harmonic signal, multiplexer, commutator, amplitude detector and harmonic signal amplifier.EFFECT: simplified construction of device.3 dwg

FIELD: computer science, possible use for engineering of signals processing microprocessors, and of digital filters.SUBSTANCE: device uses neural-network technologies and polynomial residuals system, wherein as system base minimal polynomials pi(z), where input=1,2,...,n, are utilized, determined in expanded Galois fields GF(2V), while device has clock counter, two blocks for calculating sums of paired results of multiplication by arbitrary base, error correction block, modular adder and block for calculating sums of paired results of multiplication based on control base.EFFECT: decreased hardware requirements, improved speed of operations.2 dwg, 3 tbl